sc520 now builds fine. On to testing.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/amd/sc520/raminit.c

@@ -345,6 +345,12 @@ void sc520_udelay(int microseconds) {
 		;
 }
 
+/* looks like we define this now */
+void
+udelay(int microseconds) {
+	sc520_udelay(microseconds);
+}
+
 
 static void dumpram(void){
   print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n");

src/cpu/amd/sc520/sc520.c

@@ -10,6 +10,19 @@
 #include <bitops.h>
 #include "chip.h"
 
+
+/* hack for now */
+void sc520_udelay(int microseconds) {
+        volatile int x;
+        for(x = 0; x < 1000; x++) 
+                ;  
+}
+
+/* looks like we define this now */
+void
+udelay(int microseconds) {
+        sc520_udelay(microseconds); 
+}
 /*
  * set up basic things ... PAR should NOT go here, as it might change with the mainboard. 
  */