Doxidization, reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
@@ -1,3 +1,6 @@
|
||||
# How does the config tool pick the correct
|
||||
# cpufixup.c to generate cupfixup.o ?
|
||||
|
||||
uses k8
|
||||
uses CPU_FIXUP
|
||||
default k8=1
|
||||
|
@@ -428,5 +428,5 @@ void k8_enable(struct chip *chip, enum chip_pass pass)
|
||||
|
||||
struct chip_control cpu_k8_control = {
|
||||
.enable = k8_enable,
|
||||
.name = "AMD K8",
|
||||
.name = "AMD K8 CPU",
|
||||
};
|
||||
|
@@ -27,13 +27,24 @@ static void early_mtrr_init(void)
|
||||
msr_t msr;
|
||||
const unsigned long *msr_addr;
|
||||
|
||||
/* Enable the access to AMD RdDram and WrDram extension bits */
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
|
||||
wrmsr(msr);
|
||||
|
||||
/* Inialize all of the relevant msrs to 0 */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for(msr_addr = mtrr_msrs; *msr_addr; msr_addr++) {
|
||||
|
||||
for (msr_addr = mtrr_msrs; *msr_addr; msr_addr++) {
|
||||
wrmsr(*msr_addr, msr);
|
||||
}
|
||||
|
||||
/* Disable the access to AMD RdDram and WrDram extension bits */
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
|
||||
wrmsr(msr);
|
||||
|
||||
/* Enable memory access for 0 - 1MB using top_mem */
|
||||
msr.hi = 0;
|
||||
msr.lo = ((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK;
|
||||
|
@@ -13,6 +13,13 @@ earlymtrr_start:
|
||||
xorl %edx, %edx #
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
|
||||
enable_fixed_mtrr_dram_modify:
|
||||
/* Enable the access to AMD RdDram and WrDram extension bits */
|
||||
movl $SYSCFG_MSR, %ecx
|
||||
rdmsr
|
||||
orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
|
||||
wrmsr
|
||||
|
||||
clear_fixed_var_mtrr:
|
||||
lodsl (%esi), %eax
|
||||
testl %eax, %eax
|
||||
@@ -25,7 +32,14 @@ clear_fixed_var_mtrr:
|
||||
jmp clear_fixed_var_mtrr
|
||||
clear_fixed_var_mtrr_out:
|
||||
|
||||
/* enable memory access for 0 - 1MB using top_mem */
|
||||
disable_fixed_mtrr_dram_modify:
|
||||
/* Disable the access to AMD RdDram and WrDram extension bits */
|
||||
movl $SYSCFG_MSR, %ecx
|
||||
rdmsr
|
||||
andl $(~SYSCFG_MSR_MtrrFixDramModEn), %eax
|
||||
wrmsr
|
||||
|
||||
/* enable memory access for 0 - 1MB using top_mem */
|
||||
movl $TOP_MEM, %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
|
||||
@@ -72,9 +86,10 @@ enable_mtrr:
|
||||
movl $0x00000800, %eax
|
||||
wrmsr
|
||||
|
||||
/* Enable the MTRRs in SYSCFG */
|
||||
/* Enable the MTRRs and IORRs in SYSCFG */
|
||||
movl $SYSCFG_MSR, %ecx
|
||||
rdmsr
|
||||
/* Don't enable SYSCFG_MSR_MtrrFixDramEn) untill we have done with VGA BIOS */
|
||||
orl $(SYSCFG_MSR_MtrrVarDramEn), %eax
|
||||
wrmsr
|
||||
|
||||
|
@@ -99,7 +99,7 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned l
|
||||
base.hi = basek >> 22;
|
||||
base.lo = basek << 10;
|
||||
|
||||
//printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
|
||||
//printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
|
||||
|
||||
if (sizek < 4*1024*1024) {
|
||||
mask.hi = ADDRESS_MASK_HIGH;
|
||||
@@ -219,7 +219,7 @@ static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char
|
||||
unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
|
||||
msr_t msr;
|
||||
msr.lo = msr.hi = 0; /* Shut up gcc */
|
||||
for(i = first; i < last; i++) {
|
||||
for (i = first; i < last; i++) {
|
||||
/* When I switch to a new msr read it in */
|
||||
if (fixed_msr != i >> 3) {
|
||||
/* But first write out the old msr */
|
||||
@@ -304,12 +304,12 @@ void setup_mtrrs(struct mem_range *mem)
|
||||
printk_debug("\n");
|
||||
/* Initialized the fixed_mtrrs to uncached */
|
||||
printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
|
||||
0, NUM_FIXED_RANGES);
|
||||
0, NUM_FIXED_RANGES);
|
||||
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
|
||||
|
||||
/* Now see which of the fixed mtrrs cover ram.
|
||||
*/
|
||||
for(memp = mem; memp->sizek; memp++) {
|
||||
for (memp = mem; memp->sizek; memp++) {
|
||||
unsigned int start_mtrr;
|
||||
unsigned int last_mtrr;
|
||||
start_mtrr = fixed_mtrr_index(memp->basek);
|
||||
@@ -317,11 +317,17 @@ void setup_mtrrs(struct mem_range *mem)
|
||||
if (start_mtrr >= NUM_FIXED_RANGES) {
|
||||
break;
|
||||
}
|
||||
|
||||
#if defined(k7) || defined(k8)
|
||||
#warning "FIXME: dealing with RdMEM/WrMEM for Athlon/Opteron"
|
||||
#endif
|
||||
|
||||
printk_debug("Setting fixed MTRRs(%d-%d) type: WB\n",
|
||||
start_mtrr, last_mtrr);
|
||||
start_mtrr, last_mtrr);
|
||||
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
|
||||
}
|
||||
printk_debug("DONE fixed MTRRs\n");
|
||||
|
||||
/* Cache as many memory areas as possible */
|
||||
/* FIXME is there an algorithm for computing the optimal set of mtrrs?
|
||||
* In some cases it is definitely possible to do better.
|
||||
|
Reference in New Issue
Block a user