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AGESA binaryPI boards: Fix some whitespace

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Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki
2017-09-21 12:32:43 +03:00
parent e1dced4561
commit e52738b428
34 changed files with 622 additions and 622 deletions
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42
src/mainboard/amd/db-ft3b-lc/OemCustomize.c
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@@ -18,12 +18,12 @@
#include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = {
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -32,8 +32,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -42,8 +42,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -52,8 +52,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -62,8 +62,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -71,12 +71,12 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
}
};
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
},
};
@@ -190,14 +190,14 @@ HW_RXEN_SEED(
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_6),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END
};