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AGESA binaryPI boards: Fix some whitespace

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Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki
2017-09-21 12:32:43 +03:00
parent e1dced4561
commit e52738b428
34 changed files with 622 additions and 622 deletions
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54
src/mainboard/amd/bettong/OemCustomize.c
View File

@@ -18,12 +18,12 @@
#include <boardid.h> #include <boardid.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 3, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 3, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -33,8 +33,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -43,8 +43,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -53,8 +53,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -63,8 +63,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -73,8 +73,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -83,24 +83,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 */ /* DP0 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 */ /* DP1 */
{ {
0, /*DESCRIPTOR_TERMINATE_LIST, */ 0, /*DESCRIPTOR_TERMINATE_LIST, */
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
}, },
/* DP2 */ /* DP2 */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
}, },
}; };
@@ -136,13 +136,13 @@ VOID OemCustomizeInitEarly (
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MOTHER_BOARD_LAYERS (LAYERS_6), MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

42
src/mainboard/amd/db-ft3b-lc/OemCustomize.c
View File

@@ -18,12 +18,12 @@
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -32,8 +32,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -42,8 +42,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -52,8 +52,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -62,8 +62,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -71,12 +71,12 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
}; };
@@ -190,14 +190,14 @@ HW_RXEN_SEED(
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_6), MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

2
src/mainboard/amd/dinar/OemCustomize.c
View File

@@ -34,7 +34,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
// CS2 M[B,A]_CLK_H/L[1] // CS2 M[B,A]_CLK_H/L[1]
// CS3 M[B,A]_CLK_H/L[3] // CS3 M[B,A]_CLK_H/L[3]
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
PSO_END PSO_END
}; };

32
src/mainboard/amd/inagua/OemCustomize.c
View File

@@ -46,45 +46,45 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
} }
}; };
@@ -139,8 +139,8 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

32
src/mainboard/amd/lamar/OemCustomize.c
View File

@@ -17,7 +17,7 @@
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* /*
* Lanes to pins to PCI device mapping can be found in section 2.12 of the * Lanes to pins to PCI device mapping can be found in section 2.12 of the
@@ -26,8 +26,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
{ /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */ { /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 31), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 31),
PCIE_PORT_DATA_INITIALIZER_V2 ( PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, PortEnabled,
ChannelTypeExt6db, 0, 0, ChannelTypeExt6db, 0, 0,
HotplugDisabled, HotplugDisabled,
@@ -41,8 +41,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
{ /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */ { /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 11),
PCIE_PORT_DATA_INITIALIZER_V2 ( PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, PortEnabled,
ChannelTypeExt6db, 0, 0, ChannelTypeExt6db, 0, 0,
HotplugDisabled, HotplugDisabled,
@@ -56,11 +56,11 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
{ /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */ { /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER ( PCIE_ENGINE_DATA_INITIALIZER(
IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
12, 15 12, 15
), ),
PCIE_PORT_DATA_INITIALIZER_V2 ( PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, PortEnabled,
ChannelTypeExt6db, 0, 0, ChannelTypeExt6db, 0, 0,
HotplugDisabled, HotplugDisabled,
@@ -73,32 +73,32 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
{ /* DP3 */ { /* DP3 */
0, 0,
PCIE_ENGINE_DATA_INITIALIZER ( PCIE_ENGINE_DATA_INITIALIZER(
IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
12, 15 12, 15
), ),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux4, Hdp4) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux4, Hdp4)
}, },
{ /* DP2 */ { /* DP2 */
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 36, 39), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 36, 39),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
}, },
{ /* DP1 */ { /* DP1 */
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
}, },
{ /* DP0 */ { /* DP0 */
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 4, 7),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
}; };

50
src/mainboard/amd/olivehill/OemCustomize.c
View File

@@ -21,11 +21,11 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -34,8 +34,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -44,8 +44,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -54,8 +54,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -64,8 +64,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -73,24 +73,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
}, },
}; };
@@ -167,14 +167,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_4), MOTHER_BOARD_LAYERS(LAYERS_4),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

36
src/mainboard/amd/olivehillplus/OemCustomize.c
View File

@@ -16,12 +16,12 @@
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -30,8 +30,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -40,8 +40,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -50,8 +50,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -60,8 +60,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -69,24 +69,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
}, },
}; };

58
src/mainboard/amd/parmer/OemCustomize.c
View File

@@ -66,75 +66,75 @@
* 38 DP2_TX[P,N]6 * 38 DP2_TX[P,N]6
*/ */
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */ /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */ /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
}, },
}; };
@@ -207,12 +207,12 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

36
src/mainboard/amd/persimmon/OemCustomize.c
View File

@@ -44,52 +44,52 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeLvds, Aux1, Hdp1} {ConnectorTypeLvds, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeDP, Aux2, Hdp2} {ConnectorTypeDP, Aux2, Hdp2}
} }
}; };
@@ -145,8 +145,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

36
src/mainboard/amd/south_station/OemCustomize.c
View File

@@ -46,53 +46,53 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
#if 1 #if 1
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
#endif #endif
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
/* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */ /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
}, },
/* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */ /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
} }
}; };
@@ -147,8 +147,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

56
src/mainboard/amd/thatcher/OemCustomize.c
View File

@@ -66,74 +66,74 @@
* 38 DP2_TX[P,N]6 * 38 DP2_TX[P,N]6
*/ */
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */ /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 4, PCI Device Number 4, LAN */ /* PCIe port, Lanes 4, PCI Device Number 4, LAN */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 7, PCI Device Number 7, Disabled */ /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// DP0 to HDMI0/DP0 // DP0 to HDMI0/DP0
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
// DP1 to HDMI1/DP1 // DP1 to HDMI1/DP1
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
}, },
// DP2 to MINI-DDI Card // DP2 to MINI-DDI Card
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
}, },
}; };
@@ -233,12 +233,12 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

40
src/mainboard/amd/torpedo/OemCustomize.c
View File

@@ -21,57 +21,57 @@
#include "amdlib.h" #include "amdlib.h"
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
}, },
// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
}, },
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
}, },
// Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
} }
}; };
@@ -166,8 +166,8 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
PSO_END PSO_END
}; };

36
src/mainboard/amd/union_station/OemCustomize.c
View File

@@ -48,54 +48,54 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
#if 1 #if 1
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
#endif #endif
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeHDMI, Aux1, Hdp1} {ConnectorTypeHDMI, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeHDMI, Aux2, Hdp2} {ConnectorTypeHDMI, Aux2, Hdp2}
} }
}; };
@@ -151,8 +151,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

24
src/mainboard/asrock/e350m1/OemCustomize.c
View File

@@ -48,34 +48,34 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeDP, Aux1, Hdp1} {ConnectorTypeDP, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeDP, Aux2, Hdp2} {ConnectorTypeDP, Aux2, Hdp2}
} }
}; };
@@ -131,8 +131,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

50
src/mainboard/asrock/imb-a180/OemCustomize.c
View File

@@ -21,11 +21,11 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -34,8 +34,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -44,8 +44,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -54,8 +54,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -64,8 +64,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -73,24 +73,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
}, },
}; };
@@ -167,14 +167,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_4), MOTHER_BOARD_LAYERS(LAYERS_4),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

44
src/mainboard/asus/f2a85-m/OemCustomize.c
View File

@@ -67,24 +67,24 @@
* 38 DP2_TX[P,N]6 * 38 DP2_TX[P,N]6
*/ */
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
}; };
@@ -94,24 +94,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
* Tested and works: VGA/DVI * Tested and works: VGA/DVI
* Untested: HDMI * Untested: HDMI
*/ */
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// DP0 to HDMI0/DP // DP0 to HDMI0/DP
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
// DP1 to FCH // DP1 to FCH
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
}, },
// DP2 to HDMI1/DP // DP2 to HDMI1/DP
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
}, },
}; };
@@ -211,22 +211,22 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
*/ */
static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = { static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
/* /*
TODO: is this OK for DDR3 socket FM2? TODO: is this OK for DDR3 socket FM2?
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/ */
PSO_END PSO_END
}; };
static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = { static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
PSO_END PSO_END
}; };

42
src/mainboard/bap/ode_e20XX/OemCustomize.c
View File

@@ -21,12 +21,12 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */ /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugBasic, HotplugBasic,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -35,8 +35,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device Number 2, Function 3) */ /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device Number 2, Function 3) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -45,8 +45,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device Number 2, Function 2) */ /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device Number 2, Function 2) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -55,8 +55,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, Function 1) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, Function 1) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugBasic, HotplugBasic,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -64,18 +64,18 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* eDP0 to LVDS connector*/ /* eDP0 to LVDS connector*/
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to HDMI */ /* DP1 to HDMI */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
}, },
}; };
@@ -158,14 +158,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_6), MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

28
src/mainboard/bap/ode_e21XX/OemCustomize.c
View File

@@ -16,12 +16,12 @@
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */ /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -30,8 +30,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -40,8 +40,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -50,8 +50,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -59,18 +59,18 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* eDP0 to LVDS connector */ /* eDP0 to LVDS connector */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to HDMI */ /* DP1 to HDMI */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
}, },
}; };

50
src/mainboard/biostar/am1ml/OemCustomize.c
View File

@@ -21,11 +21,11 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -34,8 +34,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -44,8 +44,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -54,8 +54,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -64,8 +64,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -73,24 +73,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
}, },
}; };
@@ -171,14 +171,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_4), MOTHER_BOARD_LAYERS(LAYERS_4),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

36
src/mainboard/elmex/pcm205400/OemCustomize.c
View File

@@ -44,52 +44,52 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeLvds, Aux1, Hdp1} {ConnectorTypeLvds, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeDP, Aux2, Hdp2} {ConnectorTypeDP, Aux2, Hdp2}
} }
}; };
@@ -145,8 +145,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* use its default conservative settings. * use its default conservative settings.
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

36
src/mainboard/gizmosphere/gizmo/OemCustomize.c
View File

@@ -49,52 +49,52 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeDP, Aux1, Hdp1} {ConnectorTypeDP, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeDP, Aux2, Hdp2} {ConnectorTypeDP, Aux2, Hdp2}
} }
}; };
@@ -151,8 +151,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
// Gizmos soldered down memory uses memory CLK0 and CLK1 on CS0 // Gizmos soldered down memory uses memory CLK0 and CLK1 on CS0
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),

46
src/mainboard/gizmosphere/gizmo2/OemCustomize.c
View File

@@ -21,11 +21,11 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -34,8 +34,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -44,8 +44,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -54,8 +54,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -64,8 +64,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -73,18 +73,18 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
/* DP1 to high-speed edge connector */ /* DP1 to high-speed edge connector */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
}, },
}; };
@@ -167,14 +167,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
MOTHER_BOARD_LAYERS (LAYERS_6), MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

46
src/mainboard/hp/abm/OemCustomize.c
View File

@@ -22,11 +22,11 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -35,8 +35,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -45,8 +45,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -55,8 +55,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -65,8 +65,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -74,18 +74,18 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
}, },
}; };
@@ -162,14 +162,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A), SEED_A),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
MOTHER_BOARD_LAYERS (LAYERS_6), MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

58
src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
View File

@@ -67,75 +67,75 @@
* 38 DP2_TX[P,N]6 * 38 DP2_TX[P,N]6
*/ */
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */ /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */ /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
}, },
}; };
@@ -210,12 +210,12 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

36
src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
View File

@@ -46,12 +46,12 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
/** /**
* @brief Initialize Port descriptors * @brief Initialize Port descriptors
*/ */
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
GNB_GPP_PORT4_CHANNEL_TYPE, GNB_GPP_PORT4_CHANNEL_TYPE,
4, 4,
GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_HOTPLUG_SUPPORT,
@@ -63,8 +63,8 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
GNB_GPP_PORT5_CHANNEL_TYPE, GNB_GPP_PORT5_CHANNEL_TYPE,
5, 5,
GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_HOTPLUG_SUPPORT,
@@ -76,8 +76,8 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
GNB_GPP_PORT6_CHANNEL_TYPE, GNB_GPP_PORT6_CHANNEL_TYPE,
6, 6,
GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_HOTPLUG_SUPPORT,
@@ -89,8 +89,8 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
GNB_GPP_PORT7_CHANNEL_TYPE, GNB_GPP_PORT7_CHANNEL_TYPE,
7, 7,
GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_HOTPLUG_SUPPORT,
@@ -102,8 +102,8 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
GNB_GPP_PORT8_CHANNEL_TYPE, GNB_GPP_PORT8_CHANNEL_TYPE,
8, 8,
GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_HOTPLUG_SUPPORT,
@@ -117,19 +117,19 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
/** /**
* @brief Initialize Ddi descriptors * @brief Initialize Ddi descriptors
*/ */
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
/* (DDI interface Lanes 8:11, DdA, ...) */ /* (DDI interface Lanes 8:11, DdA, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
{ConnectorTypeLvds, Aux1, Hdp1} {ConnectorTypeLvds, Aux1, Hdp1}
}, },
/* (DDI interface Lanes 12:15, DdB, ...) */ /* (DDI interface Lanes 12:15, DdB, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
{ConnectorTypeDP, Aux2, Hdp2} {ConnectorTypeDP, Aux2, Hdp2}
} }
}; };
@@ -187,8 +187,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* data from the table. Otherwise, it will use its default conservative settings. * data from the table. Otherwise, it will use its default conservative settings.
*/ */
static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

58
src/mainboard/lenovo/g505s/OemCustomize.c
View File

@@ -67,75 +67,75 @@
* 38 DP2_TX[P,N]6 * 38 DP2_TX[P,N]6
*/ */
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */ /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 to HDMI0/DP */ /* DP0 to HDMI0/DP */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
}, },
/* DP1 to FCH */ /* DP1 to FCH */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
}, },
/* DP2 to HDMI1/DP */ /* DP2 to HDMI1/DP */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */ /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
}, },
}; };
@@ -210,12 +210,12 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };

36
src/mainboard/lippert/frontrunner-af/OemCustomize.c
View File

@@ -48,52 +48,52 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeTravisDpToLvds, Aux1, Hdp1} {ConnectorTypeTravisDpToLvds, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeDP, Aux2, Hdp2} {ConnectorTypeDP, Aux2, Hdp2}
} }
}; };
@@ -150,8 +150,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

36
src/mainboard/lippert/toucan-af/OemCustomize.c
View File

@@ -48,52 +48,52 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeAutoDetect, Aux1, Hdp1} {ConnectorTypeAutoDetect, Aux1, Hdp1}
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeAutoDetect, Aux2, Hdp2} {ConnectorTypeAutoDetect, Aux2, Hdp2}
} }
}; };
@@ -150,8 +150,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END PSO_END
}; };

48
src/mainboard/msi/ms7721/OemCustomize.c
View File

@@ -68,57 +68,57 @@
* 38 DP2_TX[P,N]6 * 38 DP2_TX[P,N]6
*/ */
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */ /* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */ /* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */ /* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */ /* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
}, },
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
}, },
}; };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// DP0 to HDMI0/DP // DP0 to HDMI0/DP
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
}, },
// DP1 to FCH // DP1 to FCH
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
}, },
// DP2 to HDMI1/DP // DP2 to HDMI1/DP
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
}, },
}; };
@@ -218,14 +218,14 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
/* /*
TODO: is this OK for DDR3 socket FM2? TODO: is this OK for DDR3 socket FM2?
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/ */
PSO_END PSO_END
}; };

32
src/mainboard/pcengines/apu1/OemCustomize.c
View File

@@ -44,45 +44,45 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeDP, Aux1, Hdp1} {ConnectorTypeDP, Aux1, Hdp1}
}, },
}; };
@@ -139,8 +139,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
// APU soldered down memory uses memory CLK0 and CLK1 on CS0 // APU soldered down memory uses memory CLK0 and CLK1 on CS0
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),

22
src/mainboard/pcengines/apu2/OemCustomize.c
View File

@@ -16,11 +16,11 @@
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -29,8 +29,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -39,8 +39,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -49,8 +49,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
@@ -59,8 +59,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,

2
src/mainboard/supermicro/h8qgi/OemCustomize.c
View File

@@ -61,7 +61,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
SEED_D), SEED_D),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), //max 3
PSO_END PSO_END
}; };

2
src/mainboard/supermicro/h8scm/OemCustomize.c
View File

@@ -62,7 +62,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
SEED_D), SEED_D),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), //max 3
PSO_END PSO_END
}; };

2
src/mainboard/tyan/s8226/OemCustomize.c
View File

@@ -62,7 +62,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
SEED_D), SEED_D),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 3), //max 3 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 3), //max 3
PSO_END PSO_END
}; };