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soc/amd/stoneyridge/southbridge.c: Create a GPIO programming function

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Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.

Add dummy table to kahlee, grunt and gardenia to be able to test a build.

BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.

Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Richard Spiegel
2017-12-25 18:25:58 -07:00
committed by Martin Roth
parent 19a5ed1f3b
commit e539c85386
8 changed files with 151 additions and 2 deletions
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26
src/soc/amd/stoneyridge/southbridge.c
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@@ -155,6 +155,32 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
return irq_association;
}
void sb_program_gpio(void)
{
void *tmp_ptr;
const struct soc_amd_stoneyridge_gpio *gpio_ptr;
size_t size;
uint8_t control, mux, index;
printk(BIOS_SPEW, "GPIO programming stage %s\n", STR_GPIO_STAGE);
gpio_ptr = board_get_gpio(&size);
for (index = 0; index < size; index++) {
mux = gpio_ptr[index].function;
control = gpio_ptr[index].control;
tmp_ptr = (void *)(gpio_ptr[index].gpio + AMD_GPIO_MUX);
write8(tmp_ptr, mux & AMD_GPIO_MUX_MASK);
/*
* Get the address of AMD_GPIO_CONTROL (dword) relative
* to the desired pin and program bits 16-23.
*/
tmp_ptr = (void *)(gpio_ptr[index].gpio * sizeof(uint32_t) +
AMD_GPIO_CONTROL + 2);
write8(tmp_ptr, control);
}
printk(BIOS_SPEW, "End GPIO programming\n");
}
/**
* @brief Find the size of a particular wide IO
*