vc/amd/pi/00660F01: Remove unused code and directory
This is some leftover omitted during 00660F01 removal, since corresponding CPU and northbridge code is not present in the tree already. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib7ccbc088766b5a4f59c47bd48790c6a2af8ca61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Michał Żygowski
committed by
Felix Held
Felix Held
parent
d44ca19b83
commit
e570845f6d
File diff suppressed because it is too large
Load Diff
@ -1,481 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* Agesa structures and definitions
|
|
||||||
*
|
|
||||||
* Contains AMD AGESA core interface
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Include
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef _AMD_H_
|
|
||||||
#define _AMD_H_
|
|
||||||
|
|
||||||
#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
|
|
||||||
#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
|
|
||||||
#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
|
|
||||||
|
|
||||||
#define AGESA_REVISION "Arch2008"
|
|
||||||
#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
|
|
||||||
|
|
||||||
//
|
|
||||||
//
|
|
||||||
// AGESA Types and Definitions
|
|
||||||
//
|
|
||||||
//
|
|
||||||
#define LAST_ENTRY 0xFFFFFFFFul
|
|
||||||
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
|
|
||||||
#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
|
|
||||||
#define IOCF8 0xCF8
|
|
||||||
#define IOCFC 0xCFC
|
|
||||||
|
|
||||||
/// The return status for all AGESA public services.
|
|
||||||
///
|
|
||||||
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
|
|
||||||
/// will have log entries with more detail.
|
|
||||||
///
|
|
||||||
typedef enum {
|
|
||||||
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
|
|
||||||
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
|
|
||||||
///< Not logged.
|
|
||||||
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
|
|
||||||
///< Example, memory address not installed, heap buffer handle not found.
|
|
||||||
///< Not Logged.
|
|
||||||
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
|
|
||||||
AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
|
|
||||||
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
|
|
||||||
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
|
|
||||||
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
|
|
||||||
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
|
|
||||||
///< may not be able to reliably produce log events.
|
|
||||||
AgesaStatusMax ///< Not a status, for limit checking.
|
|
||||||
} AGESA_STATUS;
|
|
||||||
|
|
||||||
/// For checking whether a status is at or above the mandatory log level.
|
|
||||||
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Callout method to the host environment.
|
|
||||||
*
|
|
||||||
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
|
|
||||||
*
|
|
||||||
* @param[in] Function The specific callout function being invoked.
|
|
||||||
* @param[in] FcnData Function specific data item.
|
|
||||||
* @param[in,out] ConfigPtr Reference to Callout params.
|
|
||||||
*/
|
|
||||||
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
|
|
||||||
IN UINT32 Function,
|
|
||||||
IN UINTN FcnData,
|
|
||||||
IN OUT VOID *ConfigPtr
|
|
||||||
);
|
|
||||||
|
|
||||||
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
|
|
||||||
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
|
|
||||||
|
|
||||||
///This allocation type is used by the AmdCreateStruct entry point
|
|
||||||
typedef enum {
|
|
||||||
PreMemHeap = 0, ///< Create heap in cache.
|
|
||||||
PostMemDram, ///< Create heap in memory.
|
|
||||||
ByHost ///< Create heap by Host.
|
|
||||||
} ALLOCATION_METHOD;
|
|
||||||
|
|
||||||
/// These width descriptors are used by the library function, and others, to specify the data size
|
|
||||||
typedef enum ACCESS_WIDTH {
|
|
||||||
AccessWidthNone = 0, ///< dummy access width
|
|
||||||
AccessWidth8 = 1, ///< Access width is 8 bits.
|
|
||||||
AccessWidth16, ///< Access width is 16 bits.
|
|
||||||
AccessWidth32, ///< Access width is 32 bits.
|
|
||||||
AccessWidth64, ///< Access width is 64 bits.
|
|
||||||
|
|
||||||
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
|
|
||||||
AccessS3SaveWidth16, ///< Save 16 bits data.
|
|
||||||
AccessS3SaveWidth32, ///< Save 32 bits data.
|
|
||||||
AccessS3SaveWidth64, ///< Save 64 bits data.
|
|
||||||
} ACCESS_WIDTH;
|
|
||||||
|
|
||||||
/* When AMD rolled out CarrizoPI, they made a bad choice of removing
|
|
||||||
* an entry from the middle of the enumeration list.
|
|
||||||
*/
|
|
||||||
#define AMD_S3_SAVE_REMOVED
|
|
||||||
|
|
||||||
/// AGESA struct name
|
|
||||||
typedef enum {
|
|
||||||
// AGESA BASIC FUNCTIONS
|
|
||||||
AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
|
|
||||||
AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
|
|
||||||
AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
|
|
||||||
AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
|
|
||||||
AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
|
|
||||||
AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
|
|
||||||
AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
|
|
||||||
AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
|
|
||||||
AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
|
|
||||||
AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
|
|
||||||
AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
|
|
||||||
AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle
|
|
||||||
AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle
|
|
||||||
AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle
|
|
||||||
AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle
|
|
||||||
AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle
|
|
||||||
AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle
|
|
||||||
AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle
|
|
||||||
AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle
|
|
||||||
AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle
|
|
||||||
AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle
|
|
||||||
// Add
|
|
||||||
AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
|
|
||||||
AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
|
|
||||||
FCH_INIT_RESET = 0x00040000,
|
|
||||||
FCH_INIT_ENV = 0x00041000,
|
|
||||||
FCH_INIT_MID = 0x00042000,
|
|
||||||
FCH_INIT_LATE = 0x00043000,
|
|
||||||
FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
|
|
||||||
FCH_INIT_S3_LATE_RESTORE = 0x00045000,
|
|
||||||
AMD_SET_VALUE_invalid = 0x00081000,
|
|
||||||
AMD_GET_VALUE_invalid = 0x00082000
|
|
||||||
} AGESA_STRUCT_NAME;
|
|
||||||
|
|
||||||
/* ResetType constant values */
|
|
||||||
#define WARM_RESET_WHENEVER 1
|
|
||||||
#define COLD_RESET_WHENEVER 2
|
|
||||||
#define WARM_RESET_IMMEDIATELY 3
|
|
||||||
#define COLD_RESET_IMMEDIATELY 4
|
|
||||||
|
|
||||||
|
|
||||||
// AGESA Structures
|
|
||||||
|
|
||||||
/// The standard header for all AGESA services.
|
|
||||||
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
|
|
||||||
typedef struct {
|
|
||||||
IN VOID * ImageBasePtr; ///< The AGESA Image base address.
|
|
||||||
IN UINT32 Func; ///< The service desired
|
|
||||||
IN VOID * AltImageBasePtr; ///< Alternate Image location
|
|
||||||
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
|
|
||||||
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
|
|
||||||
IN UINT64 HeapBasePtr; ///< Location of the heap
|
|
||||||
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
|
|
||||||
} AMD_CONFIG_PARAMS;
|
|
||||||
|
|
||||||
|
|
||||||
/// Create Struct Interface.
|
|
||||||
typedef struct {
|
|
||||||
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
|
|
||||||
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
|
|
||||||
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
|
|
||||||
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
|
|
||||||
IN OUT VOID *NewStructPtr; ///< The struct for the service.
|
|
||||||
///< The struct to init for ByHost allocation,
|
|
||||||
///< the initialized struct on return.
|
|
||||||
} AMD_INTERFACE_PARAMS;
|
|
||||||
|
|
||||||
#define FUNC_0 0 // bit-placed for PCI address creation
|
|
||||||
#define FUNC_1 1
|
|
||||||
#define FUNC_2 2
|
|
||||||
#define FUNC_3 3
|
|
||||||
#define FUNC_4 4
|
|
||||||
#define FUNC_5 5
|
|
||||||
#define FUNC_6 6
|
|
||||||
#define FUNC_7 7
|
|
||||||
|
|
||||||
/// AGESA Binary module header structure
|
|
||||||
typedef struct {
|
|
||||||
IN UINT32 Signature; ///< Binary Signature
|
|
||||||
IN CHAR8 CreatorID[8]; ///< 8 characters ID
|
|
||||||
IN CHAR8 Version[12]; ///< 12 characters version
|
|
||||||
IN UINT32 ModuleInfoOffset; ///< Offset of module
|
|
||||||
IN UINT32 EntryPointAddress; ///< Entry address
|
|
||||||
IN UINT32 ImageBase; ///< Image base
|
|
||||||
IN UINT32 RelocTableOffset; ///< Relocate Table offset
|
|
||||||
IN UINT32 ImageSize; ///< Size
|
|
||||||
IN UINT16 Checksum; ///< Checksum
|
|
||||||
IN UINT8 ImageType; ///< Type
|
|
||||||
IN UINT8 V_Reserved; ///< Reserved
|
|
||||||
} AMD_IMAGE_HEADER;
|
|
||||||
/// AGESA Binary module header structure
|
|
||||||
typedef struct _AMD_MODULE_HEADER {
|
|
||||||
IN UINT32 ModuleHeaderSignature; ///< Module signature
|
|
||||||
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
|
|
||||||
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
|
|
||||||
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
|
|
||||||
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
|
|
||||||
} AMD_MODULE_HEADER;
|
|
||||||
|
|
||||||
// AMD_CODE_HEADER Signatures.
|
|
||||||
#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
|
|
||||||
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
|
|
||||||
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
|
|
||||||
|
|
||||||
/// AGESA_CODE_SIGNATURE
|
|
||||||
typedef struct {
|
|
||||||
IN CHAR8 Signature[8]; ///< code header Signature
|
|
||||||
IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
|
|
||||||
IN CHAR8 Version[12]; ///< 12 character version string
|
|
||||||
IN CHAR8 TerminatorNull; ///< null terminated string
|
|
||||||
IN CHAR8 VerReserved[7]; ///< reserved space
|
|
||||||
} AMD_CODE_HEADER;
|
|
||||||
|
|
||||||
/// Extended PCI address format
|
|
||||||
typedef struct {
|
|
||||||
IN OUT UINT32 Register:12; ///< Register offset
|
|
||||||
IN OUT UINT32 Function:3; ///< Function number
|
|
||||||
IN OUT UINT32 Device:5; ///< Device number
|
|
||||||
IN OUT UINT32 Bus:8; ///< Bus number
|
|
||||||
IN OUT UINT32 Segment:4; ///< Segment
|
|
||||||
} EXT_PCI_ADDR;
|
|
||||||
|
|
||||||
/// Union type for PCI address
|
|
||||||
typedef union _PCI_ADDR {
|
|
||||||
IN UINT32 AddressValue; ///< Formal address
|
|
||||||
IN EXT_PCI_ADDR Address; ///< Extended address
|
|
||||||
} PCI_ADDR;
|
|
||||||
|
|
||||||
// SBDFO - Segment Bus Device Function Offset
|
|
||||||
// 31:28 Segment (4-bits)
|
|
||||||
// 27:20 Bus (8-bits)
|
|
||||||
// 19:15 Device (5-bits)
|
|
||||||
// 14:12 Function(3-bits)
|
|
||||||
// 11:00 Offset (12-bits)
|
|
||||||
|
|
||||||
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
|
|
||||||
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
|
|
||||||
#define ILLEGAL_SBDFO 0xFFFFFFFFul
|
|
||||||
|
|
||||||
/// CPUID data received registers format
|
|
||||||
typedef struct {
|
|
||||||
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
|
|
||||||
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
|
|
||||||
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
|
|
||||||
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
|
|
||||||
} CPUID_DATA;
|
|
||||||
|
|
||||||
// Topology Services definitions and macros
|
|
||||||
#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef BIT0
|
|
||||||
#define BIT0 0x0000000000000001ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT1
|
|
||||||
#define BIT1 0x0000000000000002ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT2
|
|
||||||
#define BIT2 0x0000000000000004ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT3
|
|
||||||
#define BIT3 0x0000000000000008ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT4
|
|
||||||
#define BIT4 0x0000000000000010ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT5
|
|
||||||
#define BIT5 0x0000000000000020ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT6
|
|
||||||
#define BIT6 0x0000000000000040ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT7
|
|
||||||
#define BIT7 0x0000000000000080ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT8
|
|
||||||
#define BIT8 0x0000000000000100ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT9
|
|
||||||
#define BIT9 0x0000000000000200ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT10
|
|
||||||
#define BIT10 0x0000000000000400ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT11
|
|
||||||
#define BIT11 0x0000000000000800ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT12
|
|
||||||
#define BIT12 0x0000000000001000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT13
|
|
||||||
#define BIT13 0x0000000000002000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT14
|
|
||||||
#define BIT14 0x0000000000004000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT15
|
|
||||||
#define BIT15 0x0000000000008000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT16
|
|
||||||
#define BIT16 0x0000000000010000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT17
|
|
||||||
#define BIT17 0x0000000000020000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT18
|
|
||||||
#define BIT18 0x0000000000040000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT19
|
|
||||||
#define BIT19 0x0000000000080000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT20
|
|
||||||
#define BIT20 0x0000000000100000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT21
|
|
||||||
#define BIT21 0x0000000000200000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT22
|
|
||||||
#define BIT22 0x0000000000400000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT23
|
|
||||||
#define BIT23 0x0000000000800000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT24
|
|
||||||
#define BIT24 0x0000000001000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT25
|
|
||||||
#define BIT25 0x0000000002000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT26
|
|
||||||
#define BIT26 0x0000000004000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT27
|
|
||||||
#define BIT27 0x0000000008000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT28
|
|
||||||
#define BIT28 0x0000000010000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT29
|
|
||||||
#define BIT29 0x0000000020000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT30
|
|
||||||
#define BIT30 0x0000000040000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT31
|
|
||||||
#define BIT31 0x0000000080000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT32
|
|
||||||
#define BIT32 0x0000000100000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT33
|
|
||||||
#define BIT33 0x0000000200000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT34
|
|
||||||
#define BIT34 0x0000000400000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT35
|
|
||||||
#define BIT35 0x0000000800000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT36
|
|
||||||
#define BIT36 0x0000001000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT37
|
|
||||||
#define BIT37 0x0000002000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT38
|
|
||||||
#define BIT38 0x0000004000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT39
|
|
||||||
#define BIT39 0x0000008000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT40
|
|
||||||
#define BIT40 0x0000010000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT41
|
|
||||||
#define BIT41 0x0000020000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT42
|
|
||||||
#define BIT42 0x0000040000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT43
|
|
||||||
#define BIT43 0x0000080000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT44
|
|
||||||
#define BIT44 0x0000100000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT45
|
|
||||||
#define BIT45 0x0000200000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT46
|
|
||||||
#define BIT46 0x0000400000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT47
|
|
||||||
#define BIT47 0x0000800000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT48
|
|
||||||
#define BIT48 0x0001000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT49
|
|
||||||
#define BIT49 0x0002000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT50
|
|
||||||
#define BIT50 0x0004000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT51
|
|
||||||
#define BIT51 0x0008000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT52
|
|
||||||
#define BIT52 0x0010000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT53
|
|
||||||
#define BIT53 0x0020000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT54
|
|
||||||
#define BIT54 0x0040000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT55
|
|
||||||
#define BIT55 0x0080000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT56
|
|
||||||
#define BIT56 0x0100000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT57
|
|
||||||
#define BIT57 0x0200000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT58
|
|
||||||
#define BIT58 0x0400000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT59
|
|
||||||
#define BIT59 0x0800000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT60
|
|
||||||
#define BIT60 0x1000000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT61
|
|
||||||
#define BIT61 0x2000000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT62
|
|
||||||
#define BIT62 0x4000000000000000ull
|
|
||||||
#endif
|
|
||||||
#ifndef BIT63
|
|
||||||
#define BIT63 0x8000000000000000ull
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif // _AMD_H_
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD Pushhigh Interface
|
|
||||||
*
|
|
||||||
* Contains interface to Pushhigh entry
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Legacy
|
|
||||||
* @e \$Revision: 281175 $ @e \$Date: 2013-12-18 15:53:00 +0800 (Wed, 18 Dec 2013) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _DISPATCHER_H_
|
|
||||||
#define _DISPATCHER_H_
|
|
||||||
|
|
||||||
// AGESA function prototypes
|
|
||||||
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
|
|
||||||
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
|
|
||||||
|
|
||||||
#endif // _DISPATCHER_H_
|
|
||||||
@ -1,648 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* Collectively assign unique filecodes for assert and debug to each source file.
|
|
||||||
*
|
|
||||||
* Publish values for decorated filenames, which can be used for
|
|
||||||
* ASSERT and debug support using a preprocessor define like:
|
|
||||||
* @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
|
|
||||||
* This file serves as a reference for debugging to associate the code and filename.
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Include
|
|
||||||
* @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _FILECODE_H_
|
|
||||||
#define _FILECODE_H_
|
|
||||||
|
|
||||||
#define UNASSIGNED_FILE_FILECODE (0xFFFF)
|
|
||||||
|
|
||||||
/// For debug use in any Platform's options C file.
|
|
||||||
/// Can be reused for platforms and image builds, since only one options file can be built.
|
|
||||||
#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
|
|
||||||
|
|
||||||
|
|
||||||
#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
|
|
||||||
#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
|
|
||||||
#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
|
|
||||||
#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
|
|
||||||
#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
|
|
||||||
#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
|
|
||||||
#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA033)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECOMMCLKCFG_PCIECOMMCLKCFG_FILECODE (0xA04C)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
|
|
||||||
#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
|
|
||||||
#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7)
|
|
||||||
#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8)
|
|
||||||
#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9)
|
|
||||||
#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA)
|
|
||||||
#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB)
|
|
||||||
#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC)
|
|
||||||
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD)
|
|
||||||
#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEASPMEXITLATENCYV5_FILECODE (0xA0C5)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
|
|
||||||
#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101)
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZ_FILECODE (0xA202)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GFXENVINITCZ_FILECODE (0xA203)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GFXGMCINITCZ_FILECODE (0xA204)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GFXINTEGRATEDINFOTABLECZ_FILECODE (0xA205)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GFXLIBCZ_FILECODE (0xA206)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GFXMIDINITCZ_FILECODE (0xA207)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GFXPOSTINITCZ_FILECODE (0xA208)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBEARLYINITCZ_FILECODE (0xA209)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBENVINITCZ_FILECODE (0xA20A)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBFUSETABLECZ_FILECODE (0xA20B)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBIOMMUIVRSCZ_FILECODE (0xA20C)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBMIDINITCZ_FILECODE (0xA20D)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBPOSTINITCZ_FILECODE (0xA20E)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBREGISTERACCCZ_FILECODE (0xA20F)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBURATOKENMAPCZ_FILECODE (0xA211)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIECOMPLEXDATACZ_FILECODE (0xA212)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIECONFIGCZ_FILECODE (0xA213)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIEEARLYINITCZ_FILECODE (0xA214)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIEENVINITCZ_FILECODE (0xA215)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIELIBCZ_FILECODE (0xA216)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIEMIDINITCZ_FILECODE (0xA217)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIEPOSTINITCZ_FILECODE (0xA218)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIEPOWERGATECZ_FILECODE (0xA219)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBURACZ_FILECODE (0xA21A)
|
|
||||||
#define PROC_GNB_MODULES_GNBSMULIBV8_GNBSMUINITLIBV8_FILECODE (0xA21B)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_PCIEARIINITCZ_FILECODE (0xA21C)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBBOOTTIMECALCZ_FILECODE (0xA21D)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBPSPCZ_FILECODE (0xA21E)
|
|
||||||
#define PROC_GNB_MODULES_GNBINITCZ_GNBSMUINITCZ_FILECODE (0xA21F)
|
|
||||||
|
|
||||||
#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
|
|
||||||
#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
|
|
||||||
#define PROC_GNB_GNBINITATRTB_FILECODE (0xAE03)
|
|
||||||
#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18)
|
|
||||||
|
|
||||||
#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33)
|
|
||||||
#define PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE (0xAE3A)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXLIBV5_FILECODE (0xAE41)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXINTEGRATEDINFOTABLEV5_FILECODE (0xAE42)
|
|
||||||
#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXPWRPLAYTABLEV5_FILECODE (0xAE43)
|
|
||||||
#define PROC_GNB_MODULES_GNBAZALIALIB_GNBAZALIALIB_FILECODE (0xAE44)
|
|
||||||
|
|
||||||
// FCH
|
|
||||||
#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
|
|
||||||
#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011)
|
|
||||||
#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
|
|
||||||
#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
|
|
||||||
#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
|
|
||||||
#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
|
|
||||||
#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016)
|
|
||||||
|
|
||||||
#define UEFI_SMM_MEMSMMLIB_MEMSMMLIB_FILECODE (0xB2C1)
|
|
||||||
#define UEFI_SMM_MEMSMMLIB_CZ_DRAMMAPCZ_FILECODE (0xB2C3)
|
|
||||||
#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIARESET_FILECODE (0xB400)
|
|
||||||
#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAENV_FILECODE (0xB401)
|
|
||||||
#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAMID_FILECODE (0xB402)
|
|
||||||
#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIALATE_FILECODE (0xB403)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIRESET_FILECODE (0xB410)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENV_FILECODE (0xB411)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMID_FILECODE (0xB412)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATE_FILECODE (0xB413)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNSSSERVICE_FILECODE (0xB414)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENVSERVICE_FILECODE (0xB415)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMIDSERVICE_FILECODE (0xB416)
|
|
||||||
#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATESERVICE_FILECODE (0xB417)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMRESET_FILECODE (0xB420)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMENV_FILECODE (0xB421)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMMID_FILECODE (0xB422)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMLATE_FILECODE (0xB423)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMENVSERVICE_FILECODE (0xB424)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMMIDSERVICE_FILECODE (0xB425)
|
|
||||||
#define PROC_FCH_KERN_KERNHWM_KERNHWMLATESERVICE_FILECODE (0xB426)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITRESET_FILECODE (0xB427)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITENV_FILECODE (0xB428)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITMID_FILECODE (0xB429)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITLATE_FILECODE (0xB42A)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITS3_FILECODE (0xB42B)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNINITRESETDEF_FILECODE (0xB42C)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNINITENVDEF_FILECODE (0xB42D)
|
|
||||||
#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHTASKLAUNCHER_FILECODE (0xB42E)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNIMCRESET_FILECODE (0xB430)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNIMCENV_FILECODE (0xB431)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNIMCMID_FILECODE (0xB432)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNIMCLATE_FILECODE (0xB433)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNFCHECRESET_FILECODE (0xB434)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNFCHECENV_FILECODE (0xB435)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNFCHECMID_FILECODE (0xB436)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNFCHECLATE_FILECODE (0xB437)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNIMCLIB_FILECODE (0xB438)
|
|
||||||
#define PROC_FCH_KERN_KERNIMC_KERNIMCSERVICE_FILECODE (0xB439)
|
|
||||||
#define PROC_FCH_KERN_KERNIR_KERNIRENV_FILECODE (0xB43A)
|
|
||||||
#define PROC_FCH_KERN_KERNIR_KERNIRMID_FILECODE (0xB43B)
|
|
||||||
#define PROC_FCH_KERN_KERNIR_KERNIRLATE_FILECODE (0xB43C)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABRESET_FILECODE (0xB440)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABENV_FILECODE (0xB441)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABMID_FILECODE (0xB442)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABLATE_FILECODE (0xB443)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABENVSERVICE_FILECODE (0xB44C)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABRESETSERVICE_FILECODE (0xB44D)
|
|
||||||
#define PROC_FCH_KERN_KERNPCIE_KERNABSERVICE_FILECODE (0xB44E)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATARESET_FILECODE (0xB460)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAENV_FILECODE (0xB461)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAMID_FILECODE (0xB462)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATALATE_FILECODE (0xB463)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATARESETSERVICE_FILECODE (0xB464)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAENVSERVICE_FILECODE (0xB465)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATASERVICE_FILECODE (0xB466)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATALIB_FILECODE (0xB467)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAENVLIB_FILECODE (0xB468)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNAHCILIB_FILECODE (0xB469)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNAHCIENV_FILECODE (0xB46A)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNAHCIMID_FILECODE (0xB46B)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNAHCILATE_FILECODE (0xB46C)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNRAIDLIB_FILECODE (0xB46D)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNRAIDENV_FILECODE (0xB46E)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNRAIDMID_FILECODE (0xB46F)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNRAIDLATE_FILECODE (0xB470)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILIB_FILECODE (0xB471)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIENV_FILECODE (0xB472)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIMID_FILECODE (0xB473)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILATE_FILECODE (0xB474)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELIB_FILECODE (0xB475)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEENV_FILECODE (0xB476)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEMID_FILECODE (0xB477)
|
|
||||||
#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELATE_FILECODE (0xB478)
|
|
||||||
#define PROC_FCH_KERN_KERNSD_KERNSDENV_FILECODE (0xB481)
|
|
||||||
#define PROC_FCH_KERN_KERNSD_KERNSDMID_FILECODE (0xB482)
|
|
||||||
#define PROC_FCH_KERN_KERNSD_KERNSDLATE_FILECODE (0xB483)
|
|
||||||
#define PROC_FCH_KERN_KERNSD_KERNSDRESETSERVICE_FILECODE (0xB484)
|
|
||||||
#define PROC_FCH_KERN_KERNSD_KERNSDENVSERVICE_FILECODE (0xB485)
|
|
||||||
#define PROC_FCH_KERN_KERNSD_KERNSDSERVICE_FILECODE (0xB486)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNSPIRESET_FILECODE (0xB490)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNSPIENV_FILECODE (0xB491)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNSPIMID_FILECODE (0xB492)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNSPILATE_FILECODE (0xB493)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNLPCRESET_FILECODE (0xB494)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNLPCENV_FILECODE (0xB495)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNLPCMID_FILECODE (0xB496)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNLPCLATE_FILECODE (0xB497)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNLPCRESETSERVICE_FILECODE (0xB498)
|
|
||||||
#define PROC_FCH_KERN_KERNSPI_KERNLPCENVSERVICE_FILECODE (0xB499)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNUSBRESET_FILECODE (0xB4A0)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNUSBENV_FILECODE (0xB4A1)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNUSBMID_FILECODE (0xB4A2)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNUSBLATE_FILECODE (0xB4A3)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCIRESET_FILECODE (0xB4A4)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCIENV_FILECODE (0xB4A5)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCIMID_FILECODE (0xB4A6)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCILATE_FILECODE (0xB4A7)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCIMIDSERVICE_FILECODE (0xB4A8)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCIENVSERVICE_FILECODE (0xB4A9)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNEHCILATESERVICE_FILECODE (0xB4AA)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESET_FILECODE (0xB4B2)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIENV_FILECODE (0xB4B3)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIMID_FILECODE (0xB4B4)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCILATE_FILECODE (0xB4B5)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESETSERVICE_FILECODE (0xB4B6)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIENVSERVICE_FILECODE (0xB4B7)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIMIDSERVICE_FILECODE (0xB4B8)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCILATESERVICE_FILECODE (0xB4B9)
|
|
||||||
#define PROC_FCH_KERN_KERNUSB_KERNXHCIRECOVERY_FILECODE (0xB4BA)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB408)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB409)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB40A)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHACPICS_FUNCTIONS_FCHD3COLD_FCHD3COLD_FILECODE (0xB40B)
|
|
||||||
#define UEFI_FCH_KERN_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB4C1)
|
|
||||||
#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB4C2)
|
|
||||||
#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB4C3)
|
|
||||||
#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB4C4)
|
|
||||||
#define UEFI_FCH_KERN_DXE_CF9RESET_CF9RESET_FILECODE (0xB4C5)
|
|
||||||
#define UEFI_FCH_KERN_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB4C6)
|
|
||||||
#define UEFI_FCH_KERN_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB4C7)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXE_FCHDXE_FILECODE (0xB4C8)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXE_USBOC_FILECODE (0xB4C9)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB4CA)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB4CB)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB4CC)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB4CD)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB4CE)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB4CF)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB4D0)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB4D1)
|
|
||||||
#define UEFI_FCH_KERN_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB4D2)
|
|
||||||
#define UEFI_FCH_KERN_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB4D3)
|
|
||||||
#define UEFI_FCH_KERN_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB4D4)
|
|
||||||
#define UEFI_FCH_KERN_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB4D5)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB4D6)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEI_FCHPEI_FILECODE (0xB4D8)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEI_FCHRESET_FILECODE (0xB4D9)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB4DA)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSTALL_FILECODE (0xB4DB)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB4DC)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB4DD)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB4DE)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB4DF)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB4E0)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB4E1)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB4E2)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB4E3)
|
|
||||||
#define UEFI_FCH_KERN_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB4E4)
|
|
||||||
#define UEFI_FCH_KERN_PEI_SMBUS_SMBUS_FILECODE (0xB4E5)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_FCHSMM_FILECODE (0xB4E6)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_GPESMI_FILECODE (0xB4E7)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB4E8)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_MISCSMI_FILECODE (0xB4E9)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB4EA)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB4EB)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_SWSMI_FILECODE (0xB4EC)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMM_SXSMI_FILECODE (0xB4ED)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB4F0)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB4F1)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB4F5)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB4F6)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB4F7)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB4F8)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB4F9)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB4FA)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB4FB)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB4FC)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB4FE)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB4FF)
|
|
||||||
#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB4F2)
|
|
||||||
|
|
||||||
|
|
||||||
#define LIB_AMDLIB_FILECODE (0xC001)
|
|
||||||
#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
|
|
||||||
#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
|
|
||||||
#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
|
|
||||||
|
|
||||||
#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
|
|
||||||
|
|
||||||
#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
|
|
||||||
#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
|
|
||||||
#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
|
|
||||||
#define UEFI_PROC_COMMON_HOBTRANSFERUEFI_FILECODE (0xC160)
|
|
||||||
#define UEFI_PROC_DXE_HOBTRANSFERUEFIDXE_FILECODE (0xC161)
|
|
||||||
#define UEFI_PROC_PEI_HOBTRANSFERUEFIPEI_FILECODE (0xC162)
|
|
||||||
|
|
||||||
#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
|
|
||||||
#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
|
|
||||||
#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
|
|
||||||
#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
|
|
||||||
#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
|
|
||||||
#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
|
|
||||||
#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
|
|
||||||
#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
|
|
||||||
#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
|
|
||||||
#define PROC_COMMON_AMDINITRTB_FILECODE (0xC029)
|
|
||||||
#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
|
|
||||||
#define PROC_COMMON_AMDS3FINALRESTORE_FILECODE (0xC02B)
|
|
||||||
|
|
||||||
#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
|
|
||||||
#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
|
|
||||||
#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
|
|
||||||
#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
|
|
||||||
#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
|
|
||||||
#define PROC_COMMON_S3INIT_FILECODE (0xC0FA)
|
|
||||||
|
|
||||||
#define PROC_CPU_CPUAPCOMM_FILECODE (0xC401)
|
|
||||||
#define PROC_CPU_CPUAPCOMMAPIC_FILECODE (0xC402)
|
|
||||||
#define PROC_CPU_CPUAPCOMMPCI_FILECODE (0xC403)
|
|
||||||
#define PROC_CPU_TABLE_FILECODE (0xC404)
|
|
||||||
#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
|
|
||||||
#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
|
|
||||||
#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
|
|
||||||
#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
|
|
||||||
#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
|
|
||||||
#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
|
|
||||||
#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
|
|
||||||
#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
|
|
||||||
#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
|
|
||||||
#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F)
|
|
||||||
#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC410)
|
|
||||||
#define PROC_CPU_CPURESETINIT_FILECODE (0xC411)
|
|
||||||
#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
|
|
||||||
#define PROC_CPU_CPUMIDINIT_FILECODE (0xC421)
|
|
||||||
#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
|
|
||||||
#define PROC_CPU_S3_FILECODE (0xC460)
|
|
||||||
|
|
||||||
// Family 15h
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0A)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE (0xCB0B)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE (0xCB0C)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CPUF15PREFETCHMODE_FILECODE (0xCB0D)
|
|
||||||
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCOREAFTERRESET_FILECODE (0xCB70)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZDMI_FILECODE (0xCB71)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZNBAFTERRESET_FILECODE (0xCB72)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPSTATE_FILECODE (0xCB73)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZLOGICALIDTABLES_FILECODE (0xCB74)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZMICROCODEPATCHTABLES_FILECODE (0xCB75)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZALLCORETABLES_FILECODE (0xCB76)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCOMPUTEUNITTABLES_FILECODE (0xCB77)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZEQUIVALENCETABLE_FILECODE (0xCB78)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPRIMARYCORETABLES_FILECODE (0xCB79)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPOWERMGMTSYSTEMTABLES_FILECODE (0xCB7A)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZUTILITIES_FILECODE (0xCB7C)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZC6STATE_FILECODE (0xCB7D)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCPB_FILECODE (0xCB7E)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZIOCSTATE_FILECODE (0xCB7F)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCACHEFLUSHONHALT_FILECODE (0xCB80)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZHTC_FILECODE (0xCB81)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZINITEARLYTABLE_FILECODE (0xCB82)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZEARLYSAMPLES_FILECODE (0xCB83)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPSI_FILECODE (0xCB85)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZWORKAROUNDTABLE_FILECODE (0xCB87)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCC6EXITCONTROL_FILECODE (0xCB88)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCONNECTEDSTANDBY_FILECODE (0xCB89)
|
|
||||||
#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZBTC_FILECODE (0xCB8A)
|
|
||||||
|
|
||||||
#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
|
|
||||||
#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
|
|
||||||
#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
|
|
||||||
#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
|
|
||||||
#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
|
|
||||||
#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
|
|
||||||
#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC86)
|
|
||||||
#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
|
|
||||||
#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC0)
|
|
||||||
#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC1)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1)
|
|
||||||
#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE (0xDCD3)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCONNECTEDSTANDBY_FILECODE (0xDCD5)
|
|
||||||
#define PROC_CPU_FEATURE_CPUCC6EXITCONTROL_FILECODE (0xDCD6)
|
|
||||||
|
|
||||||
#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
|
|
||||||
|
|
||||||
#define PROC_TOPOLOGY_TOPOMAIN_FILECODE (0xE001)
|
|
||||||
#define PROC_TOPOLOGY_TOPONB_FILECODE (0xE002)
|
|
||||||
#define PROC_TOPOLOGY_FAM15_TOPONBFAM15_FILECODE (0xE087)
|
|
||||||
#define PROC_TOPOLOGY_FAM15_TOPONBUTILITIESFAM15_FILECODE (0xE088)
|
|
||||||
|
|
||||||
#define PROC_RECOVERY_TOPOLOGY_TOPOINITRECOVERY_FILECODE (0xE0FF)
|
|
||||||
|
|
||||||
#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
|
|
||||||
#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802)
|
|
||||||
#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
|
|
||||||
#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
|
|
||||||
#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
|
|
||||||
|
|
||||||
#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810)
|
|
||||||
#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811)
|
|
||||||
#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812)
|
|
||||||
#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813)
|
|
||||||
#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814)
|
|
||||||
#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815)
|
|
||||||
|
|
||||||
#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E)
|
|
||||||
#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F)
|
|
||||||
#define PROC_IDS_FAMILY_0X15_CZ_IDSF15CZALLSERVICE_FILECODE (0xE821)
|
|
||||||
|
|
||||||
|
|
||||||
///0xE820 ~ 0xE840 is reserved for ids extend module
|
|
||||||
|
|
||||||
#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
|
|
||||||
|
|
||||||
#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
|
|
||||||
#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
|
|
||||||
#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
|
|
||||||
#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
|
|
||||||
#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
|
|
||||||
#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
|
|
||||||
#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
|
|
||||||
#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
|
|
||||||
#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
|
|
||||||
#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
|
|
||||||
#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
|
|
||||||
#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
|
|
||||||
#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
|
|
||||||
#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
|
|
||||||
#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
|
|
||||||
#define PROC_MEM_FEAT_CHINTLV_MFMCHI_FILECODE (0xF094)
|
|
||||||
#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095)
|
|
||||||
#define PROC_MEM_FEAT_AMP_MFAMP_FILECODE (0xF096)
|
|
||||||
#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097)
|
|
||||||
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098)
|
|
||||||
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099)
|
|
||||||
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A)
|
|
||||||
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B)
|
|
||||||
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
|
|
||||||
#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F)
|
|
||||||
#define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0)
|
|
||||||
|
|
||||||
#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
|
|
||||||
#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
|
|
||||||
#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
|
|
||||||
#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
|
|
||||||
#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
|
|
||||||
#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
|
|
||||||
#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
|
|
||||||
#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
|
|
||||||
#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
|
|
||||||
#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
|
|
||||||
#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
|
|
||||||
#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
|
|
||||||
#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
|
|
||||||
#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
|
|
||||||
#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
|
|
||||||
#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
|
|
||||||
#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
|
|
||||||
#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
|
|
||||||
#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119)
|
|
||||||
#define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127)
|
|
||||||
|
|
||||||
#define PROC_MEM_NB_MN_FILECODE (0xF27C)
|
|
||||||
#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D)
|
|
||||||
#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E)
|
|
||||||
#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F)
|
|
||||||
#define PROC_MEM_NB_MNS3_FILECODE (0xF280)
|
|
||||||
#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281)
|
|
||||||
#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282)
|
|
||||||
#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284)
|
|
||||||
#define PROC_MEM_NB_MNREG_FILECODE (0xF285)
|
|
||||||
#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7)
|
|
||||||
#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8)
|
|
||||||
#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9)
|
|
||||||
#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF2DA)
|
|
||||||
#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF2DB)
|
|
||||||
#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF2DC)
|
|
||||||
#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF2DD)
|
|
||||||
#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF2DE)
|
|
||||||
#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF)
|
|
||||||
#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0)
|
|
||||||
#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1)
|
|
||||||
#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0xF2E3)
|
|
||||||
|
|
||||||
|
|
||||||
#define PROC_MEM_PS_MP_FILECODE (0xF401)
|
|
||||||
#define PROC_MEM_PS_MPRTT_FILECODE (0xF422)
|
|
||||||
#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423)
|
|
||||||
#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424)
|
|
||||||
#define PROC_MEM_PS_MPSAO_FILECODE (0xF425)
|
|
||||||
#define PROC_MEM_PS_MPMR0_FILECODE (0xF426)
|
|
||||||
#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427)
|
|
||||||
#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428)
|
|
||||||
#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429)
|
|
||||||
#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A)
|
|
||||||
#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B)
|
|
||||||
#define PROC_MEM_PS_MPS2D_FILECODE (0xF436)
|
|
||||||
#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437)
|
|
||||||
#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C)
|
|
||||||
#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D)
|
|
||||||
#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0xF445)
|
|
||||||
#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0xF446)
|
|
||||||
#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0xF447)
|
|
||||||
#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0xF44A)
|
|
||||||
#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0xF44B)
|
|
||||||
|
|
||||||
|
|
||||||
#define PROC_MEM_TECH_MT_FILECODE (0xF501)
|
|
||||||
#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502)
|
|
||||||
#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504)
|
|
||||||
#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505)
|
|
||||||
#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506)
|
|
||||||
#define PROC_MEM_TECH_MTTML_FILECODE (0xF507)
|
|
||||||
#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509)
|
|
||||||
#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B)
|
|
||||||
#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588)
|
|
||||||
#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589)
|
|
||||||
#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A)
|
|
||||||
#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B)
|
|
||||||
#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C)
|
|
||||||
|
|
||||||
#define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590)
|
|
||||||
#define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591)
|
|
||||||
|
|
||||||
#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801)
|
|
||||||
#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802)
|
|
||||||
#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803)
|
|
||||||
#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7)
|
|
||||||
#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8)
|
|
||||||
#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9)
|
|
||||||
#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA)
|
|
||||||
#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8)
|
|
||||||
#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9)
|
|
||||||
#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA)
|
|
||||||
|
|
||||||
//Psp
|
|
||||||
#define PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE (0xFA20)
|
|
||||||
|
|
||||||
#endif // _FILECODE_H_
|
|
||||||
@ -1,222 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* General Services
|
|
||||||
*
|
|
||||||
* Provides Services similar to the external General Services API, except
|
|
||||||
* suited to use within AGESA components. Socket, Core and PCI identification.
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Common
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _GENERAL_SERVICES_H_
|
|
||||||
#define _GENERAL_SERVICES_H_
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* D E F I N I T I O N S A N D M A C R O S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define NUMBER_OF_EVENT_DATA_PARAMS 4
|
|
||||||
|
|
||||||
/**
|
|
||||||
* AMD Device id for MMIO check.
|
|
||||||
*/
|
|
||||||
#define AMD_DEV_VEN_ID 0x1022
|
|
||||||
#define AMD_DEV_VEN_ID_ADDRESS 0
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* An AGESA Event Log entry.
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
|
|
||||||
UINT32 EventInfo; ///< Uniquely identifies the event.
|
|
||||||
UINT32 DataParam1; ///< Event specific additional data
|
|
||||||
UINT32 DataParam2; ///< Event specific additional data
|
|
||||||
UINT32 DataParam3; ///< Event specific additional data
|
|
||||||
UINT32 DataParam4; ///< Event specific additional data
|
|
||||||
} AGESA_EVENT;
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* F U N C T I O N P R O T O T Y P E
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get a specified Core's APIC ID.
|
|
||||||
*
|
|
||||||
* @param[in] StdHeader Header for library and services.
|
|
||||||
* @param[in] Socket The Core's Socket.
|
|
||||||
* @param[in] Core The Core id.
|
|
||||||
* @param[out] ApicAddress The Core's APIC ID.
|
|
||||||
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
|
|
||||||
*
|
|
||||||
* @retval TRUE The core is present, APIC Id valid
|
|
||||||
* @retval FALSE The core is not present, APIC Id not valid.
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
GetApicId (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
|
||||||
IN UINT32 Socket,
|
|
||||||
IN UINT32 Core,
|
|
||||||
OUT UINT8 *ApicAddress,
|
|
||||||
OUT AGESA_STATUS *AgesaStatus
|
|
||||||
);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get Processor Module's PCI Config Space address.
|
|
||||||
*
|
|
||||||
* @param[in] StdHeader Header for library and services.
|
|
||||||
* @param[in] Socket The Core's Socket.
|
|
||||||
* @param[in] Module The Module in that Processor
|
|
||||||
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
|
|
||||||
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
|
|
||||||
*
|
|
||||||
* @retval TRUE The core is present, PCI Address valid
|
|
||||||
* @retval FALSE The core is not present, PCI Address not valid.
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
GetPciAddress (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
|
||||||
IN UINT32 Socket,
|
|
||||||
IN UINT32 Module,
|
|
||||||
OUT PCI_ADDR *PciAddress,
|
|
||||||
OUT AGESA_STATUS *AgesaStatus
|
|
||||||
);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* "Who am I" for the current running core.
|
|
||||||
*
|
|
||||||
* @param[in] StdHeader Header for library and services.
|
|
||||||
* @param[out] Socket The current Core's Socket
|
|
||||||
* @param[out] Module The current Core's Processor Module
|
|
||||||
* @param[out] Core The current Core's core id.
|
|
||||||
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
IdentifyCore (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
|
||||||
OUT UINT32 *Socket,
|
|
||||||
OUT UINT32 *Module,
|
|
||||||
OUT UINT32 *Core,
|
|
||||||
OUT AGESA_STATUS *AgesaStatus
|
|
||||||
);
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Is this the BSP core?
|
|
||||||
*
|
|
||||||
* @param[in,out] StdHeader Header for library and services
|
|
||||||
*
|
|
||||||
* @retval TRUE Is BSP core
|
|
||||||
* @retval FALSE Is not BSP Core
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
IsBsp (
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* This function logs AGESA events into the event log.
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
PutEventLog (
|
|
||||||
IN AGESA_STATUS EventClass,
|
|
||||||
IN UINT32 EventInfo,
|
|
||||||
IN UINT32 DataParam1,
|
|
||||||
IN UINT32 DataParam2,
|
|
||||||
IN UINT32 DataParam3,
|
|
||||||
IN UINT32 DataParam4,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* This function gets event logs from the circular buffer.
|
|
||||||
*/
|
|
||||||
AGESA_STATUS
|
|
||||||
GetEventLog (
|
|
||||||
OUT AGESA_EVENT *EventRecord,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* This function gets event logs from the circular buffer without flushing the entry.
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
PeekEventLog (
|
|
||||||
OUT AGESA_EVENT *EventRecord,
|
|
||||||
IN UINT16 Index,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* This routine programs the registers necessary to get the PCI MMIO mechanism
|
|
||||||
* up and functioning.
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
InitializePciMmio (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Is it SecureS3
|
|
||||||
*
|
|
||||||
* @param[in] StdHeader Header for library and services
|
|
||||||
*
|
|
||||||
* @retval TRUE It's SecureS3
|
|
||||||
* @retval FALSE It's NOT SecureS3
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
IsSecureS3 (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif // _GENERAL_SERVICES_H_
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,145 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD Integrated Debug Routines for performance analysis
|
|
||||||
*
|
|
||||||
* Contains AMD AGESA debug macros and functions for performance analysis
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: IDS
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#ifndef _IDS_PERFORMANCE_DATA_POINT
|
|
||||||
|
|
||||||
#define _IDS_PERFORMANCE_DATA_POINT
|
|
||||||
#define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1
|
|
||||||
/// Time points performance function used
|
|
||||||
/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum
|
|
||||||
typedef enum {
|
|
||||||
TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly
|
|
||||||
TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly
|
|
||||||
TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize
|
|
||||||
TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize
|
|
||||||
TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier
|
|
||||||
TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier
|
|
||||||
TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly
|
|
||||||
TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly
|
|
||||||
TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly
|
|
||||||
TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly
|
|
||||||
TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv
|
|
||||||
TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv
|
|
||||||
TP_BEGININITENV = 0x10C, ///< BeginInitEnv
|
|
||||||
TP_ENDINITENV = 0x10D, ///< EndInitEnv
|
|
||||||
TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv
|
|
||||||
TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv
|
|
||||||
TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate
|
|
||||||
TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate
|
|
||||||
TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable
|
|
||||||
TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable
|
|
||||||
TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate
|
|
||||||
TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate
|
|
||||||
TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate
|
|
||||||
TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate
|
|
||||||
TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate
|
|
||||||
TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate
|
|
||||||
TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid
|
|
||||||
TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid
|
|
||||||
TP_BEGININITMID = 0x11E, ///< BeginInitMid
|
|
||||||
TP_ENDINITMID = 0x11F, ///< EndInitMid
|
|
||||||
TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid
|
|
||||||
TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid
|
|
||||||
TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost
|
|
||||||
TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost
|
|
||||||
TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost
|
|
||||||
TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost
|
|
||||||
TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto
|
|
||||||
TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto
|
|
||||||
TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost
|
|
||||||
TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost
|
|
||||||
TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram
|
|
||||||
TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram
|
|
||||||
TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset
|
|
||||||
TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset
|
|
||||||
TP_BEGININITRESET = 0x12E, ///< BeginInitReset
|
|
||||||
TP_ENDINITRESET = 0x12F, ///< EndInitReset
|
|
||||||
TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset
|
|
||||||
TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset
|
|
||||||
TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume
|
|
||||||
TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume
|
|
||||||
TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume
|
|
||||||
TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume
|
|
||||||
TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume
|
|
||||||
TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume
|
|
||||||
TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel
|
|
||||||
TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel
|
|
||||||
TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init
|
|
||||||
TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init
|
|
||||||
TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit
|
|
||||||
TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit
|
|
||||||
TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto
|
|
||||||
TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto
|
|
||||||
TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32
|
|
||||||
TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32
|
|
||||||
TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT
|
|
||||||
TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT
|
|
||||||
TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping
|
|
||||||
TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping
|
|
||||||
TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining
|
|
||||||
TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining
|
|
||||||
TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming
|
|
||||||
TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming
|
|
||||||
TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping
|
|
||||||
TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping
|
|
||||||
TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr
|
|
||||||
TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr
|
|
||||||
TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN
|
|
||||||
TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN
|
|
||||||
TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit
|
|
||||||
TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit
|
|
||||||
TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining
|
|
||||||
TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining
|
|
||||||
TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb
|
|
||||||
TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb
|
|
||||||
TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData
|
|
||||||
TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData
|
|
||||||
TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining
|
|
||||||
TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining
|
|
||||||
TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb
|
|
||||||
TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb
|
|
||||||
TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly
|
|
||||||
TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly
|
|
||||||
TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate
|
|
||||||
TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate
|
|
||||||
IDS_TP_END ///< End of IDS TP list
|
|
||||||
} IDS_PERF_DATA;
|
|
||||||
#endif
|
|
||||||
@ -1,68 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AGESA options structures
|
|
||||||
*
|
|
||||||
* Contains options control structures for the AGESA build options
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Core
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef _OPTIONS_H_
|
|
||||||
#define _OPTIONS_H_
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Provide topology limits for loops and runtime, based on supported families.
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
|
|
||||||
///< supported families and other build options.
|
|
||||||
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
|
|
||||||
///< on supported families.
|
|
||||||
} OPTIONS_CONFIG_TOPOLOGY;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Dispatch Table.
|
|
||||||
*
|
|
||||||
* The push high dispatcher uses this table to find what entries are currently in the build image.
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
UINT32 FunctionId; ///< The function id specified.
|
|
||||||
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
|
|
||||||
} DISPATCH_TABLE;
|
|
||||||
|
|
||||||
|
|
||||||
#endif // _OPTIONS_H_
|
|
||||||
@ -1,530 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD Platform Specific Memory Configuration
|
|
||||||
*
|
|
||||||
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: OPTION
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
|
|
||||||
#define _PLATFORM_MEMORY_CONFIGURATION_H_
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#ifndef PSO_ENTRY
|
|
||||||
#define PSO_ENTRY UINT8
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* D E F I N I T I O N S A N D M A C R O S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* PLATFORM SPECIFIC MEMORY DEFINITIONS
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
///
|
|
||||||
/// Memory Speed and DIMM Population Masks
|
|
||||||
///
|
|
||||||
///< DDR Speed Masks
|
|
||||||
///< Specifies the DDR Speed on a memory channel
|
|
||||||
///
|
|
||||||
#define ANY_SPEED 0xFFFFFFFFul
|
|
||||||
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
|
|
||||||
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
|
|
||||||
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
|
|
||||||
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
|
|
||||||
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
|
|
||||||
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
|
|
||||||
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
|
|
||||||
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
|
|
||||||
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
|
|
||||||
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
|
|
||||||
///
|
|
||||||
///< DIMM POPULATION MASKS
|
|
||||||
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
|
|
||||||
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
|
|
||||||
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
|
|
||||||
///
|
|
||||||
#define ANY_ 0xFF ///< Any dimm configuration the current channel
|
|
||||||
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
|
|
||||||
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
|
|
||||||
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
|
|
||||||
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
|
|
||||||
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
|
|
||||||
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
|
|
||||||
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
|
|
||||||
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
|
|
||||||
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
|
|
||||||
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
|
|
||||||
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
|
|
||||||
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
|
|
||||||
#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
|
|
||||||
#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
|
|
||||||
#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
|
|
||||||
#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
|
|
||||||
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
|
|
||||||
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
|
|
||||||
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
|
|
||||||
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
|
|
||||||
///
|
|
||||||
///< CS POPULATION MASKS
|
|
||||||
///< Specifies the CS Population on a channel (can be added together to specify configuration).
|
|
||||||
///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
|
|
||||||
///
|
|
||||||
#define CS_ANY_ 0xFF ///< Any CS configuration
|
|
||||||
#define CS0_ 0x01 ///< CS0 bit map mask
|
|
||||||
#define CS1_ 0x02 ///< CS1 bit map mask
|
|
||||||
#define CS2_ 0x04 ///< CS2 bit map mask
|
|
||||||
#define CS3_ 0x08 ///< CS3 bit map mask
|
|
||||||
#define CS4_ 0x10 ///< CS4 bit map mask
|
|
||||||
#define CS5_ 0x20 ///< CS5 bit map mask
|
|
||||||
#define CS6_ 0x40 ///< CS6 bit map mask
|
|
||||||
#define CS7_ 0x80 ///< CS7 bit map mask
|
|
||||||
///
|
|
||||||
///< Number of Dimms on the current channel
|
|
||||||
///< This is a mask used to indicate the number of dimms in a channel
|
|
||||||
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
|
|
||||||
///
|
|
||||||
#define ANY_NUM 0xFF ///< Any number of Dimms
|
|
||||||
#define NO_DIMM 0x00 ///< No Dimms present
|
|
||||||
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
|
|
||||||
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
|
|
||||||
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
|
|
||||||
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
|
|
||||||
|
|
||||||
///
|
|
||||||
///< DIMM VOLTAGE MASKS
|
|
||||||
///
|
|
||||||
#define VOLT_ANY_ 0xFF ///< Any voltage configuration
|
|
||||||
#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
|
|
||||||
#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
|
|
||||||
#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
|
|
||||||
|
|
||||||
//
|
|
||||||
// < Not applicable
|
|
||||||
//
|
|
||||||
#define NA_ 0 ///< Not applicable
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* Platform Specific Override Definitions for Socket, Channel and Dimm
|
|
||||||
* This indicates where a platform override will be applied.
|
|
||||||
*
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
///
|
|
||||||
///< SOCKET MASKS
|
|
||||||
///< Indicates associated processor sockets to apply override settings
|
|
||||||
///
|
|
||||||
#define ANY_SOCKET 0xFF ///< Apply to all sockets
|
|
||||||
#define SOCKET0 0x01 ///< Apply to socket 0
|
|
||||||
#define SOCKET1 0x02 ///< Apply to socket 1
|
|
||||||
#define SOCKET2 0x04 ///< Apply to socket 2
|
|
||||||
#define SOCKET3 0x08 ///< Apply to socket 3
|
|
||||||
#define SOCKET4 0x10 ///< Apply to socket 4
|
|
||||||
#define SOCKET5 0x20 ///< Apply to socket 5
|
|
||||||
#define SOCKET6 0x40 ///< Apply to socket 6
|
|
||||||
#define SOCKET7 0x80 ///< Apply to socket 7
|
|
||||||
///
|
|
||||||
///< CHANNEL MASKS
|
|
||||||
///< Indicates Memory channels where override should be applied
|
|
||||||
///
|
|
||||||
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
|
|
||||||
#define CHANNEL_A 0x01 ///< Apply to Channel A
|
|
||||||
#define CHANNEL_B 0x02 ///< Apply to Channel B
|
|
||||||
#define CHANNEL_C 0x04 ///< Apply to Channel C
|
|
||||||
#define CHANNEL_D 0x08 ///< Apply to Channel D
|
|
||||||
///
|
|
||||||
/// DIMM MASKS
|
|
||||||
/// Indicates Dimm Slots where override should be applied
|
|
||||||
///
|
|
||||||
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
|
|
||||||
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
|
|
||||||
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
|
|
||||||
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
|
|
||||||
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
|
|
||||||
///
|
|
||||||
/// REGISTER ACCESS MASKS
|
|
||||||
/// Not supported as an at this time
|
|
||||||
///
|
|
||||||
#define ACCESS_NB0 0x0
|
|
||||||
#define ACCESS_NB1 0x1
|
|
||||||
#define ACCESS_NB2 0x2
|
|
||||||
#define ACCESS_NB3 0x3
|
|
||||||
#define ACCESS_NB4 0x4
|
|
||||||
#define ACCESS_PHY 0x5
|
|
||||||
#define ACCESS_DCT_XT 0x6
|
|
||||||
///
|
|
||||||
/// MOTHER BOARD DESIGN LAYERS MASKS
|
|
||||||
/// Indicates the layer design of mother board
|
|
||||||
///
|
|
||||||
#define LAYERS_4 0x0
|
|
||||||
#define LAYERS_6 0x1
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* Platform Specific Overriding Table Definitions
|
|
||||||
*
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define PSO_END 0 ///< Table End
|
|
||||||
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
|
|
||||||
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
|
|
||||||
#define PSO_CS_TRI 3 ///< CS Tristate Map
|
|
||||||
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
|
|
||||||
#define PSO_CLK_SPEED 5 ///< Clock Speed
|
|
||||||
#define PSO_DIMM_TYPE 6 ///< Dimm Type
|
|
||||||
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
|
|
||||||
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
|
|
||||||
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
|
|
||||||
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
|
|
||||||
#define PSO_MEM_TECH 11 ///< Channel Memory Type
|
|
||||||
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
|
|
||||||
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
|
|
||||||
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
|
|
||||||
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
|
|
||||||
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
|
|
||||||
#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
|
|
||||||
#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
|
|
||||||
#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
|
|
||||||
#define PSO_MOTHER_BOARD_LAYERS 20 ///< Mother board layer design
|
|
||||||
|
|
||||||
/*----------------------------------
|
|
||||||
* CONDITIONAL PSO SPECIFIC ENTRIES
|
|
||||||
*---------------------------------*/
|
|
||||||
// Condition Types
|
|
||||||
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
|
|
||||||
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
|
|
||||||
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
|
|
||||||
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
|
|
||||||
#define PSO_CONDITION_REG 103 // Reserved
|
|
||||||
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
|
|
||||||
// Action Types
|
|
||||||
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
|
|
||||||
#define PSO_ACTION_ODT 120 ///< ODT values to override
|
|
||||||
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
|
|
||||||
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
|
|
||||||
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
|
|
||||||
#define PSO_ACTION_REG 124 // Reserved
|
|
||||||
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
|
|
||||||
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
|
|
||||||
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
|
|
||||||
|
|
||||||
/*----------------------------------
|
|
||||||
* TABLE DRIVEN PSO SPECIFIC ENTRIES
|
|
||||||
*---------------------------------*/
|
|
||||||
// Condition descriptor
|
|
||||||
#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
|
|
||||||
|
|
||||||
// Overriding entry types
|
|
||||||
#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
|
|
||||||
#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
|
|
||||||
#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
|
|
||||||
#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
|
|
||||||
#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
|
|
||||||
#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
|
|
||||||
#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
|
|
||||||
#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
|
|
||||||
#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
|
|
||||||
#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
|
|
||||||
#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
|
|
||||||
#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
|
|
||||||
#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
|
|
||||||
#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
|
|
||||||
#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
|
|
||||||
#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* CONDITIONAL OVERRIDE TABLE MACROS
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
|
|
||||||
PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
|
|
||||||
((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
|
|
||||||
PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
|
|
||||||
, Bit7Map
|
|
||||||
|
|
||||||
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
|
|
||||||
PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
|
|
||||||
|
|
||||||
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
|
|
||||||
PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
|
|
||||||
|
|
||||||
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
|
|
||||||
PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
|
|
||||||
|
|
||||||
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
|
|
||||||
PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
|
|
||||||
|
|
||||||
#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
|
|
||||||
PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
|
|
||||||
|
|
||||||
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
|
|
||||||
PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
|
|
||||||
|
|
||||||
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
|
|
||||||
PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
|
|
||||||
|
|
||||||
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
|
|
||||||
PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
|
|
||||||
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
|
|
||||||
|
|
||||||
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
|
|
||||||
PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
|
|
||||||
|
|
||||||
#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
|
|
||||||
Byte6Seed, Byte7Seed, ByteEccSeed) \
|
|
||||||
PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
|
|
||||||
Byte6Seed, Byte7Seed, ByteEccSeed
|
|
||||||
|
|
||||||
#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
|
|
||||||
Byte6Seed, Byte7Seed, ByteEccSeed) \
|
|
||||||
PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
|
|
||||||
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
|
|
||||||
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
|
|
||||||
|
|
||||||
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
|
|
||||||
PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
|
|
||||||
|
|
||||||
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
|
|
||||||
PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
|
|
||||||
|
|
||||||
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
|
|
||||||
PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
|
|
||||||
|
|
||||||
#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
|
|
||||||
PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
|
|
||||||
|
|
||||||
#define MOTHER_BOARD_LAYERS(Layers) \
|
|
||||||
PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
|
|
||||||
|
|
||||||
#define MAX_NUMBER_PSO_TABLES 13
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* CONDITIONAL OVERRIDE TABLE MACROS
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONDITION_AND \
|
|
||||||
PSO_CONDITION_AND, 0
|
|
||||||
|
|
||||||
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
|
|
||||||
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
|
|
||||||
|
|
||||||
#define COND_SPD(Byte, Mask, Value) \
|
|
||||||
PSO_CONDITION_SPD, 3, Byte, Mask, Value
|
|
||||||
|
|
||||||
#define COND_REG(Access, Offset, Mask, Value) \
|
|
||||||
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
|
|
||||||
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
|
|
||||||
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
|
|
||||||
|
|
||||||
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
|
|
||||||
PSO_ACTION_ODT, 9, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
|
|
||||||
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
|
|
||||||
|
|
||||||
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
|
|
||||||
PSO_ACTION_ADDRTMG, 10, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
|
||||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
|
||||||
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
|
|
||||||
PSO_ACTION_ODCCONTROL, 10, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
|
||||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
|
||||||
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
|
|
||||||
PSO_ACTION_SLEWRATE, 10, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
|
||||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
|
||||||
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
|
|
||||||
PSO_ACTION_SPEEDLIMIT, 9, \
|
|
||||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
|
|
||||||
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
|
|
||||||
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
|
|
||||||
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
|
|
||||||
|
|
||||||
|
|
||||||
#define MEMCLK_DIS_MAP_SIZE 13
|
|
||||||
#define CKE_TRI_MAP_SIZE 9
|
|
||||||
#define ODT_TRI_MAP_SIZE 9
|
|
||||||
#define CS_TRI_MAP_SIZE 13
|
|
||||||
#define NUMBER_OF_DIMMS_SUPPORTED_SIZE 6
|
|
||||||
#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED_SIZE 6
|
|
||||||
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED_SIZE 6
|
|
||||||
#define NUMBER_OF_CHANNELS_SUPPORTED_SIZE 6
|
|
||||||
#define OVERRIDE_DDR_BUS_SPEED_SIZE 13
|
|
||||||
#define DRAM_TECHNOLOGY_SIZE 9
|
|
||||||
#define SOLDERED_DOWN_SODIMM_TYPE_SIZE 6
|
|
||||||
#define MEMORY_POWER_POLICY_OVERRIDE_SIZE 6
|
|
||||||
#define MOTHER_BOARD_LAYERS_SIZE 6
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* END OF CONDITIONAL OVERRIDE TABLE MACROS
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* TABLE DRIVEN OVERRIDE MACROS
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
/// Configuration sub-descriptors
|
|
||||||
typedef enum {
|
|
||||||
CONFIG_GENERAL, ///< CONFIG_GENERAL
|
|
||||||
CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
|
|
||||||
CONFIG_RC2IBT, ///< CONFIG_RC2IBT
|
|
||||||
CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
|
|
||||||
} Config_Type;
|
|
||||||
|
|
||||||
// ====================
|
|
||||||
// Configuration Macros
|
|
||||||
// ====================
|
|
||||||
#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
|
|
||||||
PSO_TBLDRV_CONFIG, 9, \
|
|
||||||
CONFIG_GENERAL, \
|
|
||||||
DimmPerCH, DimmVolt, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
|
||||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
|
|
||||||
|
|
||||||
#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
|
|
||||||
PSO_TBLDRV_CONFIG, 7, \
|
|
||||||
CONFIG_SPEEDLIMIT, \
|
|
||||||
DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
|
|
||||||
|
|
||||||
#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
|
|
||||||
PSO_TBLDRV_CONFIG, 10, \
|
|
||||||
CONFIG_RC2IBT, \
|
|
||||||
DimmPerCH, DimmVolt, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
|
||||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
|
||||||
NumOfReg
|
|
||||||
|
|
||||||
//==================
|
|
||||||
// Overriding Macros
|
|
||||||
//==================
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
|
|
||||||
PSO_TBLDRV_SPEEDLIMIT, 6, \
|
|
||||||
(SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
|
|
||||||
(SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
|
|
||||||
(SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
|
|
||||||
PSO_TBLDRV_ODT_RTTNOM, 2, \
|
|
||||||
TgtCS, RttNom
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
|
|
||||||
PSO_TBLDRV_ODT_RTTWR, 2, \
|
|
||||||
TgtCS, RttWr
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
|
|
||||||
PSO_TBLDRV_ODTPATTERN, 16, \
|
|
||||||
((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
|
|
||||||
((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
|
|
||||||
((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
|
|
||||||
((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
|
|
||||||
PSO_TBLDRV_ADDRTMG, 4, \
|
|
||||||
((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
|
|
||||||
PSO_TBLDRV_ODCCTRL, 4, \
|
|
||||||
((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
|
|
||||||
PSO_TBLDRV_SLOWACCMODE, 1, \
|
|
||||||
SlowAccMode
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
|
|
||||||
PSO_TBLDRV_RC2_IBT, 2, \
|
|
||||||
TgtDimm, IBT
|
|
||||||
|
|
||||||
#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
|
|
||||||
PSO_TBLDRV_CONFIG, 1, \
|
|
||||||
CONFIG_DONT_CARE, \
|
|
||||||
PSO_TBLDRV_MR0_CL, 3, \
|
|
||||||
RegValOfTcl, MR0CL13, MR0CL0
|
|
||||||
|
|
||||||
#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
|
|
||||||
PSO_TBLDRV_CONFIG, 1, \
|
|
||||||
CONFIG_DONT_CARE, \
|
|
||||||
PSO_TBLDRV_MR0_WR, 2, \
|
|
||||||
RegValOfTwr, MR0WR
|
|
||||||
|
|
||||||
#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
|
|
||||||
PSO_TBLDRV_CONFIG, 1, \
|
|
||||||
CONFIG_DONT_CARE, \
|
|
||||||
PSO_TBLDRV_RC10_OPSPEED, 5, \
|
|
||||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
|
||||||
MR10OPSPEED
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
|
|
||||||
PSO_TBLDRV_LRDIMM_IBT, 4, \
|
|
||||||
F0RC8, F1RC0, F1RC1, F1RC2
|
|
||||||
|
|
||||||
#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
|
|
||||||
PSO_TBLDRV_2D_TRAINING, 1, \
|
|
||||||
Training2dMode
|
|
||||||
|
|
||||||
//============================
|
|
||||||
// Macros for removing entries
|
|
||||||
//============================
|
|
||||||
#define INVALID_CONFIG_FLAG 0x8000
|
|
||||||
|
|
||||||
#define TBLDRV_INVALID_CONFIG \
|
|
||||||
PSO_TBLDRV_INVALID_TYPE, 0
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* END OF TABLE DRIVEN OVERRIDE MACROS
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_
|
|
||||||
@ -1,86 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* Topology interface definitions.
|
|
||||||
*
|
|
||||||
* Contains AMD AGESA internal interface for topology related data which
|
|
||||||
* is consumed by code other than Topology Services init.
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Core
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _TOPOLOGY_H_
|
|
||||||
#define _TOPOLOGY_H_
|
|
||||||
|
|
||||||
// Defines for limiting data structure maximum allocation and limit checking.
|
|
||||||
#define MAX_NODES 1
|
|
||||||
#define MAX_SOCKETS MAX_NODES
|
|
||||||
#define MAX_DIES 1
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Socket and Module to Node Map Item.
|
|
||||||
* Provide the Node Id and core id range for each module in each processor.
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
UINT8 Node; ///< The module's Node id.
|
|
||||||
UINT8 LowCore; ///< The lowest processor core id for this module.
|
|
||||||
UINT8 HighCore; ///< The highest processor core id for this module.
|
|
||||||
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
|
|
||||||
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
|
|
||||||
UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module.
|
|
||||||
UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module.
|
|
||||||
} SOCKET_DIE_TO_NODE_ITEM;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Socket and Module to Node Map.
|
|
||||||
* This type is a pointer to the actual map, it can be used for a struct item or
|
|
||||||
* for typecasting a heap buffer pointer.
|
|
||||||
*/
|
|
||||||
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Node id to Socket Die Map Item.
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
UINT8 Socket; ///< socket of the processor containing the Node.
|
|
||||||
UINT8 Die; ///< the module in the processor which is Node.
|
|
||||||
} NODE_TO_SOCKET_DIE_ITEM;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Node id to Socket Die Map.
|
|
||||||
*/
|
|
||||||
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
|
|
||||||
|
|
||||||
#endif // _TOPOLOGY_H_
|
|
||||||
@ -1,107 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD CPU Register Table Related Functions
|
|
||||||
*
|
|
||||||
* Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: CPU
|
|
||||||
* @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CPU_FAM_REGISTERS_H_
|
|
||||||
#define _CPU_FAM_REGISTERS_H_
|
|
||||||
|
|
||||||
/*
|
|
||||||
*--------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* M O D U L E S U S E D
|
|
||||||
*
|
|
||||||
*---------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
*--------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* D E F I N I T I O N S / M A C R O S
|
|
||||||
*
|
|
||||||
*---------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
// This define should be equal to the total number of families
|
|
||||||
// in the cpuFamily enum.
|
|
||||||
#define MAX_CPU_FAMILIES 15
|
|
||||||
#define MAX_CPU_REVISIONS 15 // Max Cpu Revisions Per Family
|
|
||||||
|
|
||||||
// CPU_LOGICAL_ID.Family equates
|
|
||||||
// Family 15h equates
|
|
||||||
#define AMD_FAMILY_15_CZ 0x0004u
|
|
||||||
#define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ)
|
|
||||||
|
|
||||||
#define AMD_FAMILY_15_ST 0x0008u
|
|
||||||
#define AMD_FAMILY_ST (AMD_FAMILY_15_ST)
|
|
||||||
|
|
||||||
#define AMD_FAMILY_15 (AMD_FAMILY_15_CZ | AMD_FAMILY_ST)
|
|
||||||
|
|
||||||
// Family Unknown
|
|
||||||
#define AMD_FAMILY_UNKNOWN 0x8000u
|
|
||||||
|
|
||||||
|
|
||||||
// Family 15h CPU_LOGICAL_ID.Revision equates
|
|
||||||
// -------------------------------------
|
|
||||||
|
|
||||||
// Family 15h CZ steppings
|
|
||||||
#define AMD_F15_CZ_A0 0x0001u
|
|
||||||
#define AMD_F15_CZ_A1 0x0002u
|
|
||||||
#define AMD_F15_BR_A1 0x0004u
|
|
||||||
// Family 15h ST steppings
|
|
||||||
#define AMD_F15_ST_A0 0x0010u
|
|
||||||
// Family 15h Unknown stepping
|
|
||||||
#define AMD_F15_UNKNOWN 0x8000u
|
|
||||||
// CZ and BR
|
|
||||||
#define AMD_F15_BR_Ax (AMD_F15_BR_A1)
|
|
||||||
#define AMD_F15_BR_ALL (AMD_F15_BR_Ax)
|
|
||||||
|
|
||||||
#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1 | AMD_F15_BR_Ax)
|
|
||||||
#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax | AMD_F15_BR_ALL)
|
|
||||||
|
|
||||||
// ST
|
|
||||||
#define AMD_F15_ST_Ax (AMD_F15_ST_A0)
|
|
||||||
#define AMD_F15_ST_ALL (AMD_F15_ST_Ax)
|
|
||||||
|
|
||||||
#define AMD_F15_ALL (AMD_F15_CZ_ALL | AMD_F15_ST_ALL)
|
|
||||||
|
|
||||||
#endif // _CPU_FAM_REGISTERS_H_
|
|
||||||
|
|
||||||
@ -1,137 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD CPU Execution Cache Allocation functions.
|
|
||||||
*
|
|
||||||
* Contains code for doing Execution Cache Allocation for ROM space
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: CPU
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CPU_CACHE_INIT_H_
|
|
||||||
#define _CPU_CACHE_INIT_H_
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
|
||||||
*
|
|
||||||
*----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------
|
|
||||||
* DEFINITIONS AND MACROS
|
|
||||||
*
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define BSP_STACK_SIZE_64K 65536
|
|
||||||
#define BSP_STACK_SIZE_32K 32768
|
|
||||||
|
|
||||||
#define CORE0_STACK_SIZE 16384
|
|
||||||
#define CORE1_STACK_SIZE 4096
|
|
||||||
|
|
||||||
#define AMD_MTRR_FIX4K_BASE 0x268
|
|
||||||
#define AMD_MTRR_VARIABLE_BASE6 0x20C
|
|
||||||
#define AMD_MTRR_VARIABLE_BASE7 0x20E
|
|
||||||
|
|
||||||
#define WP_IO 0x0505050505050505ull
|
|
||||||
|
|
||||||
#define AGESA_CACHE_SIZE_REDUCED 1
|
|
||||||
#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
|
|
||||||
#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
|
|
||||||
#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
|
|
||||||
#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
|
|
||||||
#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
|
|
||||||
#define AGESA_DEALLOCATE_CACHE_REGIONS 7
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
* TYPEDEFS, STRUCTURES, ENUMS
|
|
||||||
*
|
|
||||||
*----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
/// Cache-As-Ram Executable region allocation modes
|
|
||||||
typedef enum {
|
|
||||||
LimitedByL2Size, ///< Execution space must be allocated from L2
|
|
||||||
InfiniteExe, ///< Family can support unlimited Execution space
|
|
||||||
MaxCarExeMode ///< Used as limit or bounds check
|
|
||||||
} CAR_EXE_MODE;
|
|
||||||
|
|
||||||
/// Cache Information
|
|
||||||
typedef struct {
|
|
||||||
IN UINT32 BspStackSize; ///< Stack size of BSP
|
|
||||||
IN UINT32 Core0StackSize; ///< Stack size of primary cores
|
|
||||||
IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
|
|
||||||
IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
|
|
||||||
IN UINT32 SharedMemSize; ///< Shared memory size
|
|
||||||
IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
|
|
||||||
IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
|
|
||||||
IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
|
|
||||||
IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
|
|
||||||
} CACHE_INFO;
|
|
||||||
|
|
||||||
/// Merged memory region overlap type
|
|
||||||
typedef enum {
|
|
||||||
EmptySet, ///< One of the regions is zero length
|
|
||||||
Disjoint, ///< The two regions do not touch
|
|
||||||
Adjacent, ///< one region is next to the other, no gap
|
|
||||||
CommonEnd, ///< regions overlap with a common end point
|
|
||||||
Extending, ///< the 2nd region is extending the size of the 1st
|
|
||||||
Contained, ///< the 2nd region is wholely contained inside the 1st
|
|
||||||
CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
|
|
||||||
Identity, ///< the two regions are the same
|
|
||||||
CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
|
|
||||||
NotCombinable ///< the combined regions do not follow the cache block rules
|
|
||||||
} OVERLAP_TYPE;
|
|
||||||
|
|
||||||
/// Result of merging two memory regions for cache coverage
|
|
||||||
typedef struct {
|
|
||||||
IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
|
|
||||||
IN OUT UINT32 MergedSize; ///< Size of the merged regions
|
|
||||||
OUT UINT32 OverlapAmount; ///< the size of the overlapping section
|
|
||||||
OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
|
|
||||||
} MERGED_CACHE_REGION;
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
* FUNCTIONS PROTOTYPE
|
|
||||||
*
|
|
||||||
*----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
AGESA_STATUS
|
|
||||||
AllocateExecutionCache (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
|
||||||
IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif // _CPU_CACHE_INIT_H_
|
|
||||||
|
|
||||||
@ -1,213 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD CPU Reset API, and related functions and structures.
|
|
||||||
*
|
|
||||||
* Contains code that initialized the CPU after early reset.
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: CPU
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CPU_EARLY_INIT_H_
|
|
||||||
#define _CPU_EARLY_INIT_H_
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* D E F I N I T I O N S A N D M A C R O S
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
|
|
||||||
#define LOW_NODE_DEVICEID 24
|
|
||||||
#define NB_CAPABILITIES 0xE8 //Function 3 Registers
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
/* All lengths are in bytes */
|
|
||||||
#define MICROCODE_TRIADE_SIZE 28
|
|
||||||
#define MICROCODE_HEADER_LENGTH 64
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @page ucodeflag Microcode Patches Signature Guide
|
|
||||||
*
|
|
||||||
* We mark patches in the ROM with a signature so that they can be easily found
|
|
||||||
*
|
|
||||||
* @anchor Microcode Patch Signature
|
|
||||||
* @li @e Microcode Patch Signature @n
|
|
||||||
* Microcode patches are marked by adding a signature before patches in the ROM image to
|
|
||||||
* help identify where they are located.
|
|
||||||
* There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
|
|
||||||
* The other is '$UCODE4K', it indicates there's a following patch with 4K size.
|
|
||||||
* If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/// Microcode patch flag for replacement
|
|
||||||
typedef struct {
|
|
||||||
IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
|
|
||||||
} MICROCODE_PATCHES_FLAG;
|
|
||||||
|
|
||||||
#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
|
|
||||||
#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
|
|
||||||
#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
|
|
||||||
|
|
||||||
/* Offsets in UCODE PATCH Header */
|
|
||||||
/* Note: Header is 64 bytes */
|
|
||||||
#define DATE_CODE_OFFSET 0 // 4 bytes
|
|
||||||
#define PATCH_ID 4 // 4 bytes
|
|
||||||
#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
|
|
||||||
#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
|
|
||||||
#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
|
|
||||||
#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
|
|
||||||
#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
|
|
||||||
#define PROCESSOR_REV_ID 24 // 2 bytes
|
|
||||||
#define CHIPSET_1_REV_ID 26 // 1 byte
|
|
||||||
#define CHIPSET_2_REV_ID 27 // 1 byte
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
/// A structure representing BrandId[15:0] from
|
|
||||||
/// CPUID Fn8000_0001_EBX
|
|
||||||
typedef struct {
|
|
||||||
UINT8 String1:4; ///< An index to a string value used to create the name string
|
|
||||||
UINT8 String2:4; ///< An index to a string value used to create the name string
|
|
||||||
UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
|
|
||||||
UINT8 Model:7; ///< A field used to create the model number in the name string
|
|
||||||
UINT8 Socket:4; ///< Specifies the package type
|
|
||||||
UINT8 Cores:4; ///< Identifies how many physical cores are present
|
|
||||||
} AMD_CPU_BRAND_DATA;
|
|
||||||
|
|
||||||
/// A structure containing string1 and string2 values
|
|
||||||
/// as well as information pertaining to their usage
|
|
||||||
typedef struct {
|
|
||||||
IN UINT8 Cores; ///< Appropriate number of physical cores
|
|
||||||
IN UINT8 Page; ///< This string's page number
|
|
||||||
IN UINT8 Index; ///< String index
|
|
||||||
IN UINT8 Socket; ///< Package type information
|
|
||||||
IN CONST CHAR8 *Stringstart; ///< The literal string
|
|
||||||
IN UINT8 Stringlength; ///< Number of characters in the string
|
|
||||||
} AMD_CPU_BRAND;
|
|
||||||
|
|
||||||
/// An entire CPU brand table.
|
|
||||||
typedef struct {
|
|
||||||
UINT8 NumberOfEntries; ///< The number of entries in the table.
|
|
||||||
CONST AMD_CPU_BRAND *Table; ///< The table entries.
|
|
||||||
} CPU_BRAND_TABLE;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Set down core register
|
|
||||||
*
|
|
||||||
* @CpuServiceInstances
|
|
||||||
*
|
|
||||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
|
||||||
* @param[in] Socket Socket ID.
|
|
||||||
* @param[in] Module Module ID in socket.
|
|
||||||
* @param[in] LeveledCores Number of core.
|
|
||||||
* @param[in] CoreLevelMode Core level mode.
|
|
||||||
* @param[in] StdHeader Header for library and services.
|
|
||||||
*
|
|
||||||
* @retval TRUE Down Core register is updated.
|
|
||||||
* @retval FALSE Down Core register is not updated.
|
|
||||||
*/
|
|
||||||
typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
|
|
||||||
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
|
|
||||||
IN UINT32 *Socket,
|
|
||||||
IN UINT32 *Module,
|
|
||||||
IN UINT32 *LeveledCores,
|
|
||||||
IN CORE_LEVELING_TYPE CoreLevelMode,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
/// Reference to a method
|
|
||||||
typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Provide the interface to the Core Leveling Family Specific Services.
|
|
||||||
*
|
|
||||||
* Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
|
|
||||||
* Each supported Family must provide an implementation for all methods in this interface, even if the
|
|
||||||
* implementation is a CommonReturn().
|
|
||||||
*/
|
|
||||||
struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
|
|
||||||
UINT16 Revision; ///< Interface version
|
|
||||||
// Public Methods.
|
|
||||||
PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
|
|
||||||
};
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* F U N C T I O N P R O T O T Y P E
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
// These are P U B L I C functions, used by IBVs
|
|
||||||
AGESA_STATUS
|
|
||||||
AmdCpuEarly (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
|
||||||
IN PLATFORM_CONFIGURATION *PlatformConfig
|
|
||||||
);
|
|
||||||
|
|
||||||
// These are P U B L I C functions, used by AGESA
|
|
||||||
AGESA_STATUS
|
|
||||||
PmInitializationAtEarly (
|
|
||||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
AmdCpuEarlyInitializer (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
|
||||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
|
||||||
IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif // _CPU_EARLY_INIT_H_
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,502 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD CPU Register Table Related Functions
|
|
||||||
*
|
|
||||||
* Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: CPU
|
|
||||||
* @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CPU_REGISTERS_H_
|
|
||||||
#define _CPU_REGISTERS_H_
|
|
||||||
|
|
||||||
#include "cpuFamRegisters.h"
|
|
||||||
/*
|
|
||||||
*--------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* M O D U L E S U S E D
|
|
||||||
*
|
|
||||||
*---------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
*--------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* D E F I N I T I O N S / M A C R O S
|
|
||||||
*
|
|
||||||
*---------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
#undef BIT0
|
|
||||||
#undef BIT1
|
|
||||||
#undef BIT2
|
|
||||||
#undef BIT3
|
|
||||||
#undef BIT4
|
|
||||||
#undef BIT5
|
|
||||||
#undef BIT6
|
|
||||||
#undef BIT7
|
|
||||||
#undef BIT8
|
|
||||||
#undef BIT9
|
|
||||||
#undef BIT10
|
|
||||||
#undef BIT10
|
|
||||||
#undef BIT11
|
|
||||||
#undef BIT12
|
|
||||||
#undef BIT13
|
|
||||||
#undef BIT14
|
|
||||||
#undef BIT15
|
|
||||||
#undef BIT16
|
|
||||||
#undef BIT17
|
|
||||||
#undef BIT18
|
|
||||||
#undef BIT19
|
|
||||||
#undef BIT20
|
|
||||||
#undef BIT21
|
|
||||||
#undef BIT22
|
|
||||||
#undef BIT23
|
|
||||||
#undef BIT24
|
|
||||||
#undef BIT25
|
|
||||||
#undef BIT26
|
|
||||||
#undef BIT27
|
|
||||||
#undef BIT28
|
|
||||||
#undef BIT29
|
|
||||||
#undef BIT30
|
|
||||||
#undef BIT31
|
|
||||||
#undef BIT32
|
|
||||||
#undef BIT33
|
|
||||||
#undef BIT34
|
|
||||||
#undef BIT35
|
|
||||||
#undef BIT36
|
|
||||||
#undef BIT37
|
|
||||||
#undef BIT38
|
|
||||||
#undef BIT39
|
|
||||||
#undef BIT40
|
|
||||||
#undef BIT41
|
|
||||||
#undef BIT42
|
|
||||||
#undef BIT43
|
|
||||||
#undef BIT44
|
|
||||||
#undef BIT45
|
|
||||||
#undef BIT46
|
|
||||||
#undef BIT47
|
|
||||||
#undef BIT48
|
|
||||||
#undef BIT49
|
|
||||||
#undef BIT40
|
|
||||||
#undef BIT41
|
|
||||||
#undef BIT42
|
|
||||||
#undef BIT43
|
|
||||||
#undef BIT44
|
|
||||||
#undef BIT45
|
|
||||||
#undef BIT46
|
|
||||||
#undef BIT47
|
|
||||||
#undef BIT48
|
|
||||||
#undef BIT49
|
|
||||||
#undef BIT50
|
|
||||||
#undef BIT51
|
|
||||||
#undef BIT52
|
|
||||||
#undef BIT53
|
|
||||||
#undef BIT54
|
|
||||||
#undef BIT55
|
|
||||||
#undef BIT56
|
|
||||||
#undef BIT57
|
|
||||||
#undef BIT58
|
|
||||||
#undef BIT59
|
|
||||||
#undef BIT60
|
|
||||||
#undef BIT61
|
|
||||||
#undef BIT62
|
|
||||||
#undef BIT63
|
|
||||||
|
|
||||||
#define BIT0 0x0000000000000001ull
|
|
||||||
#define BIT1 0x0000000000000002ull
|
|
||||||
#define BIT2 0x0000000000000004ull
|
|
||||||
#define BIT3 0x0000000000000008ull
|
|
||||||
#define BIT4 0x0000000000000010ull
|
|
||||||
#define BIT5 0x0000000000000020ull
|
|
||||||
#define BIT6 0x0000000000000040ull
|
|
||||||
#define BIT7 0x0000000000000080ull
|
|
||||||
#define BIT8 0x0000000000000100ull
|
|
||||||
#define BIT9 0x0000000000000200ull
|
|
||||||
#define BIT10 0x0000000000000400ull
|
|
||||||
#define BIT11 0x0000000000000800ull
|
|
||||||
#define BIT12 0x0000000000001000ull
|
|
||||||
#define BIT13 0x0000000000002000ull
|
|
||||||
#define BIT14 0x0000000000004000ull
|
|
||||||
#define BIT15 0x0000000000008000ull
|
|
||||||
#define BIT16 0x0000000000010000ull
|
|
||||||
#define BIT17 0x0000000000020000ull
|
|
||||||
#define BIT18 0x0000000000040000ull
|
|
||||||
#define BIT19 0x0000000000080000ull
|
|
||||||
#define BIT20 0x0000000000100000ull
|
|
||||||
#define BIT21 0x0000000000200000ull
|
|
||||||
#define BIT22 0x0000000000400000ull
|
|
||||||
#define BIT23 0x0000000000800000ull
|
|
||||||
#define BIT24 0x0000000001000000ull
|
|
||||||
#define BIT25 0x0000000002000000ull
|
|
||||||
#define BIT26 0x0000000004000000ull
|
|
||||||
#define BIT27 0x0000000008000000ull
|
|
||||||
#define BIT28 0x0000000010000000ull
|
|
||||||
#define BIT29 0x0000000020000000ull
|
|
||||||
#define BIT30 0x0000000040000000ull
|
|
||||||
#define BIT31 0x0000000080000000ull
|
|
||||||
#define BIT32 0x0000000100000000ull
|
|
||||||
#define BIT33 0x0000000200000000ull
|
|
||||||
#define BIT34 0x0000000400000000ull
|
|
||||||
#define BIT35 0x0000000800000000ull
|
|
||||||
#define BIT36 0x0000001000000000ull
|
|
||||||
#define BIT37 0x0000002000000000ull
|
|
||||||
#define BIT38 0x0000004000000000ull
|
|
||||||
#define BIT39 0x0000008000000000ull
|
|
||||||
#define BIT40 0x0000010000000000ull
|
|
||||||
#define BIT41 0x0000020000000000ull
|
|
||||||
#define BIT42 0x0000040000000000ull
|
|
||||||
#define BIT43 0x0000080000000000ull
|
|
||||||
#define BIT44 0x0000100000000000ull
|
|
||||||
#define BIT45 0x0000200000000000ull
|
|
||||||
#define BIT46 0x0000400000000000ull
|
|
||||||
#define BIT47 0x0000800000000000ull
|
|
||||||
#define BIT48 0x0001000000000000ull
|
|
||||||
#define BIT49 0x0002000000000000ull
|
|
||||||
#define BIT50 0x0004000000000000ull
|
|
||||||
#define BIT51 0x0008000000000000ull
|
|
||||||
#define BIT52 0x0010000000000000ull
|
|
||||||
#define BIT53 0x0020000000000000ull
|
|
||||||
#define BIT54 0x0040000000000000ull
|
|
||||||
#define BIT55 0x0080000000000000ull
|
|
||||||
#define BIT56 0x0100000000000000ull
|
|
||||||
#define BIT57 0x0200000000000000ull
|
|
||||||
#define BIT58 0x0400000000000000ull
|
|
||||||
#define BIT59 0x0800000000000000ull
|
|
||||||
#define BIT60 0x1000000000000000ull
|
|
||||||
#define BIT61 0x2000000000000000ull
|
|
||||||
#define BIT62 0x4000000000000000ull
|
|
||||||
#define BIT63 0x8000000000000000ull
|
|
||||||
|
|
||||||
/// CPUID related registers
|
|
||||||
#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
|
|
||||||
#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
|
|
||||||
#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
|
|
||||||
#define CPUID_ASSOCIATIVITY_DISABLED 0x00
|
|
||||||
#define CPUID_ASSOCIATIVITY_1_WAY 0x01
|
|
||||||
#define CPUID_ASSOCIATIVITY_2_WAY 0x02
|
|
||||||
#define CPUID_ASSOCIATIVITY_4_WAY 0x04
|
|
||||||
#define CPUID_ASSOCIATIVITY_8_WAY 0x06
|
|
||||||
#define CPUID_ASSOCIATIVITY_16_WAY 0x08
|
|
||||||
#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
|
|
||||||
#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
|
|
||||||
#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
|
|
||||||
#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
|
|
||||||
#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
|
|
||||||
#define CPUID_ASSOCIATIVITY_FULLY 0x0F
|
|
||||||
#define AMD_CPUID_TLB_L1Cache 0x80000005ul
|
|
||||||
#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
|
|
||||||
#define AMD_CPUID_APM 0x80000007ul
|
|
||||||
#define LOCAL_APIC_ID 24
|
|
||||||
#define LOGICAL_PROCESSOR_COUNT 16
|
|
||||||
#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
|
|
||||||
|
|
||||||
/// CPU Logical ID Transfer
|
|
||||||
typedef struct {
|
|
||||||
UINT32 RawId; ///< RawID
|
|
||||||
UINT16 LogicalId; ///< LogicalID
|
|
||||||
} CPU_LOGICAL_ID_XLAT;
|
|
||||||
|
|
||||||
/// Logical CPU ID Table
|
|
||||||
typedef struct {
|
|
||||||
IN UINT32 Elements; ///< Number of Elements
|
|
||||||
IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
|
|
||||||
} LOGICAL_ID_TABLE;
|
|
||||||
|
|
||||||
// MSRs
|
|
||||||
// ------------------------
|
|
||||||
#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR
|
|
||||||
#define MSR_MCG_CAP 0x00000179ul
|
|
||||||
#define DBG_CTL_MSR 0x000001D9ul
|
|
||||||
#define MSR_MC0_CTL 0x00000400ul
|
|
||||||
#define MSR_MC0_STATUS 0x00000401ul
|
|
||||||
#define MSR_MC0_MISC 0x00000403ul
|
|
||||||
#define MSR_MC1_MISC 0x00000407ul
|
|
||||||
#define MSR_MC2_MISC 0x0000040Bul
|
|
||||||
#define MSR_MC4_MISC0 0x00000413ul
|
|
||||||
#define MSR_MC5_MISC 0x00000417ul
|
|
||||||
#define MSR_MC4_MISC1 0xC0000408ul
|
|
||||||
#define MSR_MC5_STATUS 0x00000415ul
|
|
||||||
#define MSR_MC6_STATUS 0x00000419ul
|
|
||||||
|
|
||||||
#define MSR_APIC_BAR 0x0000001Bul
|
|
||||||
#define MSR_PATCH_LEVEL 0x0000008Bul
|
|
||||||
|
|
||||||
#define CPUID_LONG_MODE_ADDR 0x80000008ul
|
|
||||||
|
|
||||||
#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul
|
|
||||||
#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul
|
|
||||||
#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul
|
|
||||||
#define MSR_PATCH_LOADER 0xC0010020ul
|
|
||||||
|
|
||||||
/// Patch Loader Register
|
|
||||||
typedef struct {
|
|
||||||
UINT64 PatchBase:32; ///< Linear address of patch header address block
|
|
||||||
UINT64 SBZ:32; ///< Should be zero
|
|
||||||
} PATCH_LOADER_MSR;
|
|
||||||
|
|
||||||
#define AMD_MTRR_VARIABLE_BASE0 0x200
|
|
||||||
#define AMD_MTRR_VARIABLE_BASE6 0x20C
|
|
||||||
#define AMD_MTRR_FIX64k_00000 0x250
|
|
||||||
#define AMD_MTRR_FIX16k_80000 0x258
|
|
||||||
#define AMD_MTRR_FIX16k_A0000 0x259
|
|
||||||
#define AMD_MTRR_FIX4k_C0000 0x268
|
|
||||||
#define AMD_MTRR_FIX4k_C8000 0x269
|
|
||||||
#define AMD_MTRR_FIX4k_D0000 0x26A
|
|
||||||
#define AMD_MTRR_FIX4k_D8000 0x26B
|
|
||||||
#define AMD_MTRR_FIX4k_E0000 0x26C
|
|
||||||
#define AMD_MTRR_FIX4k_E8000 0x26D
|
|
||||||
#define AMD_MTRR_FIX4k_F0000 0x26E
|
|
||||||
#define AMD_MTRR_FIX4k_F8000 0x26F
|
|
||||||
|
|
||||||
#define AMD_MTRR_FIX64K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
|
|
||||||
#define AMD_MTRR_FIX64K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
|
|
||||||
#define AMD_MTRR_FIX64K_UC_DRAM 0x1818181818181818ull
|
|
||||||
#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
|
|
||||||
#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
|
|
||||||
#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
|
|
||||||
#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
|
|
||||||
#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
|
|
||||||
#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
|
|
||||||
|
|
||||||
|
|
||||||
#define MSR_SYS_CFG 0xC0010010ul // SYSCFG
|
|
||||||
#define MSR_TOM 0xC001001Aul // TOP_MEM
|
|
||||||
#define MSR_TOM2 0xC001001Dul // TOP_MEM2
|
|
||||||
#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask
|
|
||||||
#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask
|
|
||||||
#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask
|
|
||||||
#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask
|
|
||||||
|
|
||||||
#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features
|
|
||||||
#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features
|
|
||||||
#define MSR_HDT_CFG 0xC001100Aul
|
|
||||||
#define MSR_HWCR 0xC0010015ul
|
|
||||||
#define MSR_NB_CFG 0xC001001Ful // NB Config
|
|
||||||
#define MSR_HTC 0xC001003Eul
|
|
||||||
#define CPU_WDT_CFG 0xC0010074ul
|
|
||||||
#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
|
|
||||||
#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
|
|
||||||
#define MSR_CU_SPMCTL 0xC0010281ul
|
|
||||||
#define MSR_LS_CFG 0xC0011020ul
|
|
||||||
#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared
|
|
||||||
#define MSR_DC_CFG 0xC0011022ul
|
|
||||||
#define MSR_ME_CFG 0xC0011029ul
|
|
||||||
#define MSR_BU_CFG 0xC0011023ul
|
|
||||||
#define MSR_CU_CFG 0xC0011023ul // F15 Shared
|
|
||||||
#define MSR_DE_CFG 0xC0011029ul // F15 Shared
|
|
||||||
#define MSR_BU_CFG2 0xC001102Aul
|
|
||||||
#define MSR_CU_CFG2 0xC001102Aul // F15 Shared
|
|
||||||
#define MSR_BU_CFG3 0xC001102Bul
|
|
||||||
#define MSR_CU_CFG3 0xC001102Bul // F15 Shared
|
|
||||||
#define MSR_LS_CFG2 0xC001102Dul
|
|
||||||
#define MSR_CU_PFTCFG 0xC001102Ful
|
|
||||||
#define MSR_IBS_OP_DATA3 0xC0011037ul
|
|
||||||
#define MSR_C001_1070 0xC0011070ul // F15 Shared
|
|
||||||
#define MSR_CU_CBBCFG 0xC00110A1ul // F15 CZ
|
|
||||||
|
|
||||||
|
|
||||||
#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
|
|
||||||
#define MSR_CPUID_NAME_STRING1 0xC0010031ul
|
|
||||||
#define MSR_CPUID_NAME_STRING2 0xC0010032ul
|
|
||||||
#define MSR_CPUID_NAME_STRING3 0xC0010033ul
|
|
||||||
#define MSR_CPUID_NAME_STRING4 0xC0010034ul
|
|
||||||
#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
|
|
||||||
#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register
|
|
||||||
#define MSR_BIST 0xC0010060ul // BIST Results register
|
|
||||||
#define MSR_OSVW_ID_Length 0xC0010140ul
|
|
||||||
#define MSR_OSVW_Status 0xC0010141ul
|
|
||||||
#define MSR_NB_PERF_CTL0 0xC0010240ul
|
|
||||||
#define MSR_NB_PERF_CTR0 0xC0010241ul
|
|
||||||
#define MSR_NB_PERF_CTL1 0xC0010242ul
|
|
||||||
#define MSR_NB_PERF_CTR1 0xC0010243ul
|
|
||||||
#define MSR_NB_PERF_CTL2 0xC0010244ul
|
|
||||||
#define MSR_NB_PERF_CTR2 0xC0010245ul
|
|
||||||
#define MSR_NB_PERF_CTL3 0xC0010246ul
|
|
||||||
#define MSR_NB_PERF_CTR3 0xC0010247ul
|
|
||||||
#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control
|
|
||||||
#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3
|
|
||||||
#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3
|
|
||||||
#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
|
|
||||||
#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
|
|
||||||
// CAR Corruption
|
|
||||||
// FUNC_0 registers
|
|
||||||
// ----------------
|
|
||||||
#define LINK_INIT_CTRL 0x6C
|
|
||||||
#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
|
|
||||||
#define LINK_INIT_COLD_RST_DET BIT4
|
|
||||||
#define LINK_INIT_BIOS_RST_DET_0 BIT5
|
|
||||||
#define LINK_INIT_BIOS_RST_DET_1 BIT9
|
|
||||||
#define LINK_INIT_BIOS_RST_DET_2 BIT10
|
|
||||||
#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
|
|
||||||
#define EXTENDED_NODE_ID 0x160
|
|
||||||
|
|
||||||
#define CORE_CTRL 0x1DC
|
|
||||||
#define CORE_CTRL_CORE1_EN 0x00000002ul
|
|
||||||
#define CORE_CTRL_CORE2_EN 0x00000004ul
|
|
||||||
#define CORE_CTRL_CORE3_EN 0x00000008ul
|
|
||||||
#define CORE_CTRL_CORE4_EN 0x00000010ul
|
|
||||||
#define CORE_CTRL_CORE5_EN 0x00000020ul
|
|
||||||
#define CORE_CTRL_CORE6_EN 0x00000040ul
|
|
||||||
#define CORE_CTRL_CORE7_EN 0x00000080ul
|
|
||||||
#define CORE_CTRL_CORE8_EN 0x00000100ul
|
|
||||||
#define CORE_CTRL_CORE9_EN 0x00000200ul
|
|
||||||
|
|
||||||
// FUNC_3 registers
|
|
||||||
// ----------------
|
|
||||||
#define HARDWARE_THERMAL_CTRL_REG 0x64
|
|
||||||
#define SOFTWARE_THERMAL_CTRL_REG 0x68
|
|
||||||
|
|
||||||
#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
|
|
||||||
#define ACPI_PSC_4_REG 0x84
|
|
||||||
|
|
||||||
#define NB_CFG_HIGH_REG 0x8C
|
|
||||||
#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
|
|
||||||
#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
|
|
||||||
#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
|
|
||||||
#define MULTI_NODE_CPU 29
|
|
||||||
#define CPUID_FMR 0xFC // Family / Model registers
|
|
||||||
#define DOWNCORE_CTRL 0x190 // Downcore Control Register
|
|
||||||
|
|
||||||
#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
|
|
||||||
#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
|
|
||||||
#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
|
|
||||||
|
|
||||||
// FUNC_4 registers
|
|
||||||
// ----------------
|
|
||||||
/* Native Die CPUID Register F4x160 */
|
|
||||||
#define NATIVE_DIE_CPUID_REG 0x160
|
|
||||||
#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG))
|
|
||||||
|
|
||||||
/// Native Die CPUID PCI Register
|
|
||||||
typedef struct {
|
|
||||||
UINT32 Stepping:4; ///< Stepping
|
|
||||||
UINT32 BaseModel:4; ///< Base Model
|
|
||||||
UINT32 BaseFamily:4; ///< Base Family
|
|
||||||
UINT32 :4; ///< Reserved
|
|
||||||
UINT32 ExtModel:4; ///< Extended Model
|
|
||||||
UINT32 ExtFamily:8; ///< Extended Family
|
|
||||||
UINT32 :4; ///< Reserved
|
|
||||||
} NATIVE_DIE_CPUID_REGISTER;
|
|
||||||
|
|
||||||
// FUNC_5 registers
|
|
||||||
// ----------------
|
|
||||||
#define COMPUTE_UNIT_STATUS 0x80
|
|
||||||
#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
|
|
||||||
|
|
||||||
|
|
||||||
// Misc. defines.
|
|
||||||
#define PCI_DEV_BASE 24
|
|
||||||
|
|
||||||
#define CPUID_STEPPING_MASK 0x0000000Ful
|
|
||||||
#define CPUID_BASE_MODEL_MASK 0x000000F0ul
|
|
||||||
#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
|
|
||||||
#define CPUID_EXT_MODEL_MASK 0x000F0000ul
|
|
||||||
#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
|
|
||||||
|
|
||||||
#define CZ_SOCKET_FP4 0
|
|
||||||
#define ST_SOCKET_FP4 0
|
|
||||||
#define ST_SOCKET_FT4 3
|
|
||||||
#define SOCKET_IGNORE 0xF
|
|
||||||
|
|
||||||
#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
|
|
||||||
#define APIC_EXT_BRDCST_MASK 0x000E0000ul
|
|
||||||
#define APIC_ENABLE_BIT 0x00000800ul
|
|
||||||
#define LOCAL_APIC_ADDR 0xFEE00000ul
|
|
||||||
#define INT_CMD_REG_LO 0x300
|
|
||||||
#define INT_CMD_REG_HI 0x310
|
|
||||||
#define REMOTE_MSG_REG 0x380
|
|
||||||
#define REMOTE_READ_REG 0xC0
|
|
||||||
#define APIC_ID_REG 0x20
|
|
||||||
#define APIC20_ApicId 24
|
|
||||||
#define CMD_REG_TO_READ_DATA 0x338
|
|
||||||
|
|
||||||
#define MAX_CORE_ID_SIZE 8
|
|
||||||
#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
|
|
||||||
|
|
||||||
/*-------------------------
|
|
||||||
* Default definitions
|
|
||||||
*-------------------------
|
|
||||||
*/
|
|
||||||
#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul
|
|
||||||
#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul
|
|
||||||
#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul
|
|
||||||
#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul
|
|
||||||
#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul
|
|
||||||
#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul
|
|
||||||
#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul
|
|
||||||
#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul
|
|
||||||
#define DOWNCORE_MASK_TEN 0xFFFFFC00ul
|
|
||||||
#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul
|
|
||||||
#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul
|
|
||||||
#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul
|
|
||||||
#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul
|
|
||||||
#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul
|
|
||||||
#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul
|
|
||||||
#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul
|
|
||||||
#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul
|
|
||||||
#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul
|
|
||||||
|
|
||||||
#define DELIVERY_STATUS BIT13
|
|
||||||
#define REMOTE_READ_STAT_MASK 0x00030000ul
|
|
||||||
#define REMOTE_DELIVERY_PENDING 0x00010000ul
|
|
||||||
#define REMOTE_DELIVERY_DONE 0x00020000ul
|
|
||||||
|
|
||||||
/*
|
|
||||||
* --------------------------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* D E F I N E S / T Y P E D E F S / S T R U C T U R E S
|
|
||||||
*
|
|
||||||
* --------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/// CpuEarly param type
|
|
||||||
typedef struct {
|
|
||||||
IN UINT8 MemInitPState; ///< Pstate value during memory initial
|
|
||||||
IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
|
|
||||||
} AMD_CPU_EARLY_PARAMS;
|
|
||||||
|
|
||||||
/// CPUID
|
|
||||||
typedef enum {
|
|
||||||
REG_EAX, ///< EAX
|
|
||||||
REG_EBX, ///< EBX
|
|
||||||
REG_ECX, ///< ECX
|
|
||||||
REG_EDX ///< EDX
|
|
||||||
} CPUID_REG;
|
|
||||||
|
|
||||||
#endif // _CPU_REGISTERS_H_
|
|
||||||
|
|
||||||
@ -1,241 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD Heap Manager and Heap Allocation APIs, and related functions.
|
|
||||||
*
|
|
||||||
* Contains code that initialize, maintain, and allocate the heap space.
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: CPU
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _HEAP_MANAGER_H_
|
|
||||||
#define _HEAP_MANAGER_H_
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* D E F I N I T I O N S A N D M A C R O S
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define AMD_MTRR_VARIABLE_BASE0 0x200
|
|
||||||
#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
|
|
||||||
#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
|
|
||||||
|
|
||||||
#define AMD_HEAP_START_ADDRESS 0x400000ul
|
|
||||||
#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
|
|
||||||
#define AMD_HEAP_SIZE_PER_CORE 0x010000ul
|
|
||||||
#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
|
|
||||||
#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
|
|
||||||
#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
|
|
||||||
|
|
||||||
#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value)
|
|
||||||
#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20
|
|
||||||
|
|
||||||
#define AMD_HEAP_RAM_ADDRESS 0xB0000ul
|
|
||||||
|
|
||||||
#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP'
|
|
||||||
#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared
|
|
||||||
|
|
||||||
///Heap Manager Life cycle
|
|
||||||
#define HEAP_DO_NOT_EXIST_YET 1
|
|
||||||
#define HEAP_LOCAL_CACHE 2
|
|
||||||
#define HEAP_TEMP_MEM 3
|
|
||||||
#define HEAP_SYSTEM_MEM 4
|
|
||||||
#define HEAP_DO_NOT_EXIST_ANYMORE 5
|
|
||||||
#define HEAP_S3_RESUME 6
|
|
||||||
#define HEAP_RUNTIME_SYSTEM_MEM 7
|
|
||||||
|
|
||||||
///Heap callout
|
|
||||||
#define HEAP_CALLOUT_BOOTTIME 0
|
|
||||||
#define HEAP_CALLOUT_RUNTIME 1
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
/// Allocate Heap Parameters
|
|
||||||
typedef struct _ALLOCATE_HEAP_PARAMS {
|
|
||||||
UINT32 RequestedBufferSize; ///< Size of buffer.
|
|
||||||
UINT32 BufferHandle; ///< An unique ID of buffer.
|
|
||||||
UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
|
|
||||||
UINT8 *BufferPtr; ///< Pointer to buffer.
|
|
||||||
} ALLOCATE_HEAP_PARAMS;
|
|
||||||
|
|
||||||
/// Locate Heap Parameters
|
|
||||||
typedef struct _LOCATE_HEAP_PTR {
|
|
||||||
UINT32 BufferHandle; ///< An unique ID of buffer.
|
|
||||||
UINT32 BufferSize; ///< Data buffer size.
|
|
||||||
UINT8 *BufferPtr; ///< Pointer to buffer.
|
|
||||||
} LOCATE_HEAP_PTR;
|
|
||||||
|
|
||||||
/// Heap Node Header
|
|
||||||
typedef struct _BUFFER_NODE {
|
|
||||||
UINT32 BufferHandle; ///< An unique ID of buffer.
|
|
||||||
UINT32 BufferSize; ///< Size of buffer.
|
|
||||||
UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
|
|
||||||
UINT8 PadSize; ///< Size of pad.
|
|
||||||
UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
|
|
||||||
} BUFFER_NODE;
|
|
||||||
|
|
||||||
/// Heap Manager
|
|
||||||
typedef struct _HEAP_MANAGER {
|
|
||||||
UINT32 Signature; ///< a signature to indicate if the heap is valid.
|
|
||||||
UINT32 UsedSize; ///< Used size of heap.
|
|
||||||
UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
|
|
||||||
UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
|
|
||||||
} HEAP_MANAGER;
|
|
||||||
|
|
||||||
/// AGESA Buffer Handles (These are reserved)
|
|
||||||
typedef enum {
|
|
||||||
AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
|
|
||||||
AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
|
|
||||||
AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
|
|
||||||
AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
|
|
||||||
AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
|
|
||||||
AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
|
|
||||||
AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
|
|
||||||
AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
|
|
||||||
AMD_INIT_RTB_HANDLE, ///< Assign 0x000A008 buffer handle to AmdInitRtb routine.
|
|
||||||
AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
|
|
||||||
AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
|
|
||||||
AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
|
|
||||||
AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
|
|
||||||
AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
|
|
||||||
AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
|
|
||||||
AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
|
|
||||||
AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
|
|
||||||
AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
|
|
||||||
AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
|
|
||||||
AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
|
|
||||||
AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3
|
|
||||||
AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information
|
|
||||||
AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
|
|
||||||
EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log
|
|
||||||
IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine.
|
|
||||||
IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support.
|
|
||||||
IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis
|
|
||||||
AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support
|
|
||||||
AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure
|
|
||||||
AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration
|
|
||||||
AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table
|
|
||||||
AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration
|
|
||||||
AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block
|
|
||||||
AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training
|
|
||||||
AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training
|
|
||||||
AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory
|
|
||||||
AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init
|
|
||||||
AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search
|
|
||||||
AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search
|
|
||||||
AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround
|
|
||||||
AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure
|
|
||||||
AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save
|
|
||||||
AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02A buffer handle for keeping the result of IsFeatureEnabled
|
|
||||||
AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02B buffer handle for Composite Data Eye Compression Work Area
|
|
||||||
AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02C buffer handle for Samu patch buffer
|
|
||||||
AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02D buffer handle for Samu boot control buffer
|
|
||||||
AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A02E buffer handle for GNB ACP engine buffer
|
|
||||||
AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A02F buffer handle for PMU SRAM Message Block buffer
|
|
||||||
AMD_MEM_DRAM_CAD_BUS_CONFIG_HANDLE, ///< Assign 0x000A030 buffer handle for DRAM CAD Bus Configuration
|
|
||||||
AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A031 buffer handle for GNB SMU table buffer
|
|
||||||
AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A032 buffer handle for GNB CRAT HSA unit table
|
|
||||||
AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A033 buffer handle for GNB build options
|
|
||||||
AMD_S3_FINAL_RESTORE_HANDLE, ///< Assign 0x000A034 buffer handle to AmdS3FinalRestore routine.
|
|
||||||
AMD_GNB_PCIE_AER_CONFIG_HANDLE, ///< Assign 0x000A035 buffer handle for GNB PCIE AER configuration.
|
|
||||||
AMD_BTC_SCRATCH_HANDLE, ///< Assign 0x000A036 buffer handle for boot time calibration workloads
|
|
||||||
AMD_BTC_XMM_SAVE_HANDLE, ///< Assign 0x000A037 buffer handle for boot time calibration xmm register save
|
|
||||||
AMD_S3_SAVE_HANDLE, ///< Assign 0x000A038 buffer handle to memory context data
|
|
||||||
AMD_MEM_DDR_MAX_RATE_HANDLE, ///< Assign 0x000A039 buffer handle to memory DDR max rate
|
|
||||||
AMD_GNB_TDP_HANDLE, ///< Assign 0x000A03A buffer handle to GNB TDP
|
|
||||||
AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
|
|
||||||
AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
|
|
||||||
AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
|
|
||||||
SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
|
|
||||||
NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
|
|
||||||
HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
|
|
||||||
AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset
|
|
||||||
AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
|
|
||||||
IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table
|
|
||||||
IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR'
|
|
||||||
IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table
|
|
||||||
IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save
|
|
||||||
IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save
|
|
||||||
IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module
|
|
||||||
IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data
|
|
||||||
} AGESA_BUFFER_HANDLE;
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------
|
|
||||||
* F U N C T I O N P R O T O T Y P E
|
|
||||||
*---------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
HeapManagerInit (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
HeapAllocateBuffer (
|
|
||||||
IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
HeapDeallocateBuffer (
|
|
||||||
IN UINT32 BufferHandle,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
HeapLocateBuffer (
|
|
||||||
IN OUT LOCATE_HEAP_PTR *LocateHeap,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT64
|
|
||||||
HeapGetBaseAddress (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
EventLogInitialization (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
#endif // _HEAP_MANAGER_H_
|
|
||||||
@ -1,63 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD FCH Component
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _AMD_FCH_H_
|
|
||||||
#define _AMD_FCH_H_
|
|
||||||
|
|
||||||
typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr);
|
|
||||||
typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg);
|
|
||||||
|
|
||||||
|
|
||||||
/// FCH API build options
|
|
||||||
typedef struct {
|
|
||||||
FCH_INIT *InitReset; ///< InitReset
|
|
||||||
FCH_INIT *InitResetConstructor; ///< InitResetConstructor
|
|
||||||
FCH_INIT *InitEnv; ///< InitEnv
|
|
||||||
FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor
|
|
||||||
FCH_INIT *InitMid; ///< InitMid
|
|
||||||
FCH_INIT *InitMidConstructor; ///< InitMidConstructor
|
|
||||||
FCH_INIT *InitLate; ///< InitLate
|
|
||||||
FCH_INIT *InitLateConstructor; ///< InitLateConstructor
|
|
||||||
} BLDOPT_FCH_FUNCTION;
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,90 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH ACPI lib
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#ifndef _FCH_ACPILIB_H_
|
|
||||||
#define _FCH_ACPILIB_H_
|
|
||||||
///
|
|
||||||
/// RSDP - ACPI 2.0 table RSDP
|
|
||||||
///
|
|
||||||
typedef struct _RSDP_HEADER {
|
|
||||||
UINT64 Signature; ///< RSDP signature "RSD PTR"
|
|
||||||
UINT8 CheckSum; ///< checksum of the first 20 bytes
|
|
||||||
UINT8 OEMID[6]; ///< OEM ID
|
|
||||||
UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
|
|
||||||
UINT32 RsdtAddress; ///< physical address of RSDT
|
|
||||||
UINT32 Length; ///< total length of RSDP (including extended part)
|
|
||||||
UINT64 XsdtAddress; ///< physical address of XSDT
|
|
||||||
UINT8 ExtendedCheckSum; ///< chechsum of whole table
|
|
||||||
UINT8 Reserved[3]; ///< Reserved
|
|
||||||
} RSDP_HEADER;
|
|
||||||
|
|
||||||
///
|
|
||||||
/// DESCRIPTION_HEADER - ACPI common table header
|
|
||||||
///
|
|
||||||
typedef struct _DESCRIPTION_HEADER {
|
|
||||||
UINT32 Signature; ///< ACPI signature (4 ASCII characters)
|
|
||||||
UINT32 Length; ///< Length of table, in bytes, including header
|
|
||||||
UINT8 Revision; ///< ACPI Specification minor version #
|
|
||||||
UINT8 CheckSum; ///< To make sum of entire table == 0
|
|
||||||
UINT8 OemId[6]; ///< OEM identification
|
|
||||||
UINT8 OemTableId[8]; ///< OEM table identification
|
|
||||||
UINT32 OemRevision; ///< OEM revision number
|
|
||||||
UINT32 CreatorId; ///< ASL compiler vendor ID
|
|
||||||
UINT32 CreatorRevision; ///< ASL compiler revision number
|
|
||||||
} DESCRIPTION_HEADER;
|
|
||||||
|
|
||||||
///
|
|
||||||
/// _AcpiRegWrite - ACPI MMIO register R/W structure
|
|
||||||
///
|
|
||||||
typedef struct _ACPI_REG_WRITE {
|
|
||||||
UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
|
|
||||||
UINT8 MmioReg; /// MmioReg : Register index
|
|
||||||
UINT8 DataAndMask; /// DataANDMask : AND Register Data
|
|
||||||
UINT8 DataOrMask; /// DataOrMask : Or Register Data
|
|
||||||
} ACPI_REG_WRITE;
|
|
||||||
|
|
||||||
VOID* AcpiLocateTable (IN UINT32 Signature);
|
|
||||||
VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
|
|
||||||
UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
|
|
||||||
UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,66 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH BIOS Ram usage
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#ifndef _FCH_BIOS_RAM_USAGE_H_
|
|
||||||
#define _FCH_BIOS_RAM_USAGE_H_
|
|
||||||
|
|
||||||
#define RESTORE_MEMORY_CONTROLLER_START 0
|
|
||||||
#define XHCI_REGISTER_BAR00 0xD0
|
|
||||||
#define XHCI_REGISTER_BAR01 0xD1
|
|
||||||
#define XHCI_REGISTER_BAR02 0xD2
|
|
||||||
#define XHCI_REGISTER_BAR03 0xD3
|
|
||||||
#define XHCI_REGISTER_04H 0xD4
|
|
||||||
#define XHCI_REGISTER_0CH 0xD5
|
|
||||||
#define XHCI_REGISTER_3CH 0xD6
|
|
||||||
#define XHCI1_REGISTER_BAR00 0xE0
|
|
||||||
#define XHCI1_REGISTER_BAR01 0xE1
|
|
||||||
#define XHCI1_REGISTER_BAR02 0xE2
|
|
||||||
#define XHCI1_REGISTER_BAR03 0xE3
|
|
||||||
#define XHCI1_REGISTER_04H 0xE4
|
|
||||||
#define XHCI1_REGISTER_0CH 0xE5
|
|
||||||
#define XHCI1_REGISTER_3CH 0xE6
|
|
||||||
#define RTC_WORKAROUND_DATA_START 0xF0
|
|
||||||
#define BOOT_TIME_FLAG_SEC 0xF8
|
|
||||||
#define BOOT_TIME_FLAG_INT19 0xFC
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,423 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH routine definition
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#ifndef _FCH_DEF_H_
|
|
||||||
#define _FCH_DEF_H_
|
|
||||||
|
|
||||||
|
|
||||||
UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
|
|
||||||
VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
|
|
||||||
VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
|
|
||||||
VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
|
|
||||||
VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
|
|
||||||
VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
|
|
||||||
VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Ab Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetAb (IN VOID* FchDataPtr);
|
|
||||||
VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvAb (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitMidAb (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitLateAb (IN VOID* FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
|
|
||||||
BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID FchAbLateProgram (IN VOID* FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Pcie Routines
|
|
||||||
///
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Gpp Routines
|
|
||||||
///
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Common Gpp Routines
|
|
||||||
///
|
|
||||||
VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Azalia Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetAzalia (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidAzalia (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateAzalia (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch HwAcpi Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
|
|
||||||
VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
|
|
||||||
VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
|
|
||||||
VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
|
|
||||||
VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
|
|
||||||
VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID HpetInit (IN VOID *FchDataPtr);
|
|
||||||
VOID MtC1eEnable (IN VOID *FchDataPtr);
|
|
||||||
VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
|
|
||||||
VOID StressResetModeLate (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Hwm Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetHwm (IN VOID* FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvHwm (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitMidHwm (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitLateHwm (IN VOID* FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID HwmInitRegister (IN VOID* FchDataPtr);
|
|
||||||
VOID FchECfancontrolservice (IN VOID* FchDataPtr);
|
|
||||||
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Imc Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetImc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetEc (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvImc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidImc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateImc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvEc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidEc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateEc (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
|
|
||||||
VOID ImcSleep (IN VOID *FchDataPtr);
|
|
||||||
VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
|
|
||||||
VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
|
|
||||||
VOID ImcWakeup (IN VOID *FchDataPtr);
|
|
||||||
VOID ImcIdle (IN VOID *FchDataPtr);
|
|
||||||
BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
|
|
||||||
VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
|
|
||||||
VOID ImcCrashReset (IN VOID *FchDataPtr);
|
|
||||||
VOID SoftwareDisableImc (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Ir Routines
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvIr (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitMidIr (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitLateIr (IN VOID* FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch SATA Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitMidSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
VOID FchInitLateSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataIde (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataIde (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
|
|
||||||
VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
|
|
||||||
VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
|
|
||||||
VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
|
|
||||||
VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
|
|
||||||
VOID SataBar5RegSet (IN VOID *FchDataPtr);
|
|
||||||
VOID SataSetPortGenMode (IN VOID *FchDataPtr);
|
|
||||||
VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
|
|
||||||
VOID FchProgramSataPhy (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// FCH USB Controller Public Function
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchEhciDebugPortService (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
|
|
||||||
VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
|
|
||||||
VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Sd Routines
|
|
||||||
///
|
|
||||||
VOID FchInitEnvSd (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSd (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSd (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
|
|
||||||
VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Spi Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID FchSpiUnlock (IN VOID *FchDataPtr);
|
|
||||||
VOID FchSpiLock (IN VOID *FchDataPtr);
|
|
||||||
VOID FchUsb3D3ColdCallback (IN VOID *FchDataPtr);
|
|
||||||
VOID FchUsb3D0Callback (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
/*--------------------------- Documentation Pages ---------------------------*/
|
|
||||||
VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID TurnOffCG2 (OUT VOID);
|
|
||||||
VOID BackUpCG2 (OUT VOID);
|
|
||||||
VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
|
|
||||||
VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID AcLossControl (IN UINT8 AcLossControlValue);
|
|
||||||
VOID FchVgaInit (OUT VOID);
|
|
||||||
VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
|
|
||||||
VOID ValidateFchVariant (IN VOID *FchDataPtr);
|
|
||||||
VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
|
|
||||||
VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
FchSpiTransfer (
|
|
||||||
IN UINT8 PrefixCode,
|
|
||||||
IN UINT8 Opcode,
|
|
||||||
IN OUT UINT8 *DataPtr,
|
|
||||||
IN UINT8 *AddressPtr,
|
|
||||||
IN UINT8 Length,
|
|
||||||
IN BOOLEAN WriteFlag,
|
|
||||||
IN BOOLEAN AddressFlag,
|
|
||||||
IN BOOLEAN DataFlag,
|
|
||||||
IN BOOLEAN FinishedFlag
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
FchConfigureSpiDeviceDummyCycle (
|
|
||||||
IN UINT32 DeviceID,
|
|
||||||
IN UINT8 SpiMode
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
FchReadSpiId (
|
|
||||||
IN BOOLEAN Flag
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
FchPlatformSpiQe (
|
|
||||||
IN VOID *FchDataPtr
|
|
||||||
);
|
|
||||||
|
|
||||||
FCH_DATA_BLOCK*
|
|
||||||
FchInitLoadDataBlock (
|
|
||||||
IN FCH_INTERFACE *FchInterface,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
FCH_DATA_BLOCK*
|
|
||||||
FchInitEnvCreatePrivateData (
|
|
||||||
IN AMD_ENV_PARAMS *EnvParams
|
|
||||||
);
|
|
||||||
|
|
||||||
FCH_RESET_DATA_BLOCK*
|
|
||||||
FchInitResetLoadPrivateDefault (
|
|
||||||
IN AMD_RESET_PARAMS *ResetParams
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
RetrieveDataBlockFromInitReset (
|
|
||||||
IN FCH_DATA_BLOCK *FchParams
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
@ -1,672 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH IO access common routine
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#include "FchPlatform.h"
|
|
||||||
#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE
|
|
||||||
|
|
||||||
/**< FchStall - Reserved */
|
|
||||||
VOID
|
|
||||||
FchStall (
|
|
||||||
IN UINT32 uSec,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT16 timerAddr;
|
|
||||||
UINT32 startTime;
|
|
||||||
UINT32 elapsedTime;
|
|
||||||
|
|
||||||
LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
|
|
||||||
if ( timerAddr == 0 ) {
|
|
||||||
uSec = uSec / 2;
|
|
||||||
while ( uSec != 0 ) {
|
|
||||||
LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader);
|
|
||||||
uSec--;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
|
|
||||||
for ( ;; ) {
|
|
||||||
LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
|
|
||||||
if ( elapsedTime < startTime ) {
|
|
||||||
elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
|
|
||||||
} else {
|
|
||||||
elapsedTime = elapsedTime - startTime;
|
|
||||||
}
|
|
||||||
if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**< cimFchStall - Reserved */
|
|
||||||
VOID
|
|
||||||
CimFchStall (
|
|
||||||
IN UINT32 uSec,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT16 timerAddr;
|
|
||||||
UINT32 startTime;
|
|
||||||
UINT32 elapsedTime;
|
|
||||||
|
|
||||||
LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
|
|
||||||
if ( timerAddr == 0 ) {
|
|
||||||
uSec = uSec / 2;
|
|
||||||
while ( uSec != 0 ) {
|
|
||||||
LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
|
|
||||||
uSec--;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
|
|
||||||
for ( ;; ) {
|
|
||||||
LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
|
|
||||||
if ( elapsedTime < startTime ) {
|
|
||||||
elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
|
|
||||||
} else {
|
|
||||||
elapsedTime = elapsedTime - startTime;
|
|
||||||
}
|
|
||||||
if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**< FchReset - Reserved */
|
|
||||||
VOID
|
|
||||||
FchPciReset (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 PciRstValue;
|
|
||||||
|
|
||||||
PciRstValue = 0x06;
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**< outPort80 - Reserved */
|
|
||||||
VOID
|
|
||||||
OutPort80 (
|
|
||||||
IN UINT32 pcode,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**< outPort1080 - Reserved */
|
|
||||||
VOID
|
|
||||||
OutPort1080 (
|
|
||||||
IN UINT32 pcode,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**< FchCopyMem - Reserved */
|
|
||||||
VOID
|
|
||||||
FchCopyMem (
|
|
||||||
IN VOID* pDest,
|
|
||||||
IN VOID* pSource,
|
|
||||||
IN UINTN Length
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINTN i;
|
|
||||||
UINT8 *Ptr;
|
|
||||||
UINT8 *Source;
|
|
||||||
Ptr = (UINT8*)pDest;
|
|
||||||
Source = (UINT8*)pSource;
|
|
||||||
for (i = 0; i < Length; i++) {
|
|
||||||
*Ptr = *Source;
|
|
||||||
Source++;
|
|
||||||
Ptr++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/** GetRomSigPtr - Reserved **/
|
|
||||||
VOID*
|
|
||||||
GetRomSigPtr (
|
|
||||||
IN UINTN *RomSigPtr,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 RomPtr;
|
|
||||||
UINT32 RomSig;
|
|
||||||
UINT16 MswAddr;
|
|
||||||
|
|
||||||
*RomSigPtr = 0;
|
|
||||||
MswAddr = 0xFF00;
|
|
||||||
do {
|
|
||||||
RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO;
|
|
||||||
LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader);
|
|
||||||
if (RomSig == FCH_ROMSIG_SIGNATURE) {
|
|
||||||
*RomSigPtr = RomPtr;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
MswAddr >>= 1;
|
|
||||||
MswAddr |= BIT15;
|
|
||||||
} while (MswAddr != 0xFFF8);
|
|
||||||
return RomSigPtr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** RwXhciIndReg - Reserved **/
|
|
||||||
VOID
|
|
||||||
RwXhciIndReg (
|
|
||||||
IN UINT32 Index,
|
|
||||||
IN UINT32 AndMask,
|
|
||||||
IN UINT32 OrMask,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 RevReg;
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
|
|
||||||
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
|
|
||||||
RevReg = ~AndMask;
|
|
||||||
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
|
|
||||||
|
|
||||||
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
|
|
||||||
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
|
|
||||||
RevReg = ~AndMask;
|
|
||||||
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** RwXhci0IndReg - Reserved **/
|
|
||||||
VOID
|
|
||||||
RwXhci0IndReg (
|
|
||||||
IN UINT32 Index,
|
|
||||||
IN UINT32 AndMask,
|
|
||||||
IN UINT32 OrMask,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 RevReg;
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
|
|
||||||
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
|
|
||||||
RevReg = ~AndMask;
|
|
||||||
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** RwXhci1IndReg - Reserved **/
|
|
||||||
VOID
|
|
||||||
RwXhci1IndReg (
|
|
||||||
IN UINT32 Index,
|
|
||||||
IN UINT32 AndMask,
|
|
||||||
IN UINT32 OrMask,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 RevReg;
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
|
|
||||||
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
|
|
||||||
RevReg = ~AndMask;
|
|
||||||
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** ReadXhci0Phy - Reserved **/
|
|
||||||
VOID
|
|
||||||
ReadXhci0Phy (
|
|
||||||
IN UINT32 Port,
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT32 *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 RegIndex;
|
|
||||||
UINT32 RegValue;
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader);
|
|
||||||
|
|
||||||
RegIndex = FCH_XHCI_IND60_REG04;
|
|
||||||
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader);
|
|
||||||
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
|
|
||||||
LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
|
|
||||||
|
|
||||||
(*Value) = ( RegValue >> (Port * 8)) & 0x000000FF;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** ReadXhci1Phy - Reserved **/
|
|
||||||
VOID
|
|
||||||
ReadXhci1Phy (
|
|
||||||
IN UINT32 Port,
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT32 *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 RegIndex;
|
|
||||||
UINT32 RegValue;
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader);
|
|
||||||
|
|
||||||
RegIndex = FCH_XHCI_IND60_REG04;
|
|
||||||
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader);
|
|
||||||
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
|
|
||||||
LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
|
|
||||||
|
|
||||||
(*Value) = ( RegValue >> (Port * 8)) & 0x000000FF;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** AcLossControl - Reserved **/
|
|
||||||
VOID
|
|
||||||
AcLossControl (
|
|
||||||
IN UINT8 AcLossControlValue
|
|
||||||
)
|
|
||||||
{
|
|
||||||
AcLossControlValue &= 0x03;
|
|
||||||
AcLossControlValue |= BIT2;
|
|
||||||
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** RecordFchConfigPtr - Reserved **/
|
|
||||||
VOID
|
|
||||||
RecordFchConfigPtr (
|
|
||||||
IN UINT32 FchConfigPtr
|
|
||||||
)
|
|
||||||
{
|
|
||||||
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) );
|
|
||||||
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) );
|
|
||||||
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) );
|
|
||||||
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) );
|
|
||||||
}
|
|
||||||
|
|
||||||
/** ReadAlink - Reserved **/
|
|
||||||
UINT32
|
|
||||||
ReadAlink (
|
|
||||||
IN UINT32 Index,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Data;
|
|
||||||
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
|
|
||||||
LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
|
|
||||||
//Clear Index
|
|
||||||
Index = 0;
|
|
||||||
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
|
|
||||||
return Data;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** WriteAlink - Reserved **/
|
|
||||||
VOID
|
|
||||||
WriteAlink (
|
|
||||||
IN UINT32 Index,
|
|
||||||
IN UINT32 Data,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
|
|
||||||
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
|
|
||||||
//Clear Index
|
|
||||||
Index = 0;
|
|
||||||
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** RwAlink - Reserved **/
|
|
||||||
VOID
|
|
||||||
RwAlink (
|
|
||||||
IN UINT32 Index,
|
|
||||||
IN UINT32 AndMask,
|
|
||||||
IN UINT32 OrMask,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 AccessType;
|
|
||||||
|
|
||||||
AccessType = Index & 0xE0000000;
|
|
||||||
if (AccessType == (AXINDC << 29)) {
|
|
||||||
WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader);
|
|
||||||
Index = FCH_AX_DATAC_REG34 | AccessType;
|
|
||||||
} else if (AccessType == (AXINDP << 29)) {
|
|
||||||
WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
|
|
||||||
Index = FCH_AX_DATAP_REG3C | AccessType;
|
|
||||||
}
|
|
||||||
WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Read PMIO
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - PMIO Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] Value - Read Data Buffer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ReadPmio (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
OpFlag = 1 << (OpFlag - 1);
|
|
||||||
for (i = 0; i < OpFlag; i++) {
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
|
|
||||||
Address++;
|
|
||||||
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Write PMIO
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - PMIO Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] Value - Write Data Buffer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
WritePmio (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
OpFlag = 1 << (OpFlag - 1);
|
|
||||||
for (i = 0; i < OpFlag; i++) {
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
|
|
||||||
Address++;
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* RwPmio - Read/Write PMIO
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - PMIO Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] AndMask - Data And Mask 32 bits
|
|
||||||
* @param[in] OrMask - Data OR Mask 32 bits
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
RwPmio (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN UINT32 AndMask,
|
|
||||||
IN UINT32 OrMask,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Result;
|
|
||||||
|
|
||||||
ReadPmio (Address, OpFlag, &Result, StdHeader);
|
|
||||||
Result = (Result & AndMask) | OrMask;
|
|
||||||
WritePmio (Address, OpFlag, &Result, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Read PMIO2
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - PMIO2 Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] Value - Read Data Buffer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ReadPmio2 (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
OpFlag = 1 << (OpFlag - 1);
|
|
||||||
for ( i = 0; i < OpFlag; i++ ) {
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
|
|
||||||
Address++;
|
|
||||||
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Write PMIO 2
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - PMIO2 Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] Value - Write Data Buffer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
WritePmio2 (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
OpFlag = 1 << (OpFlag - 1);
|
|
||||||
|
|
||||||
for ( i = 0; i < OpFlag; i++ ) {
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
|
|
||||||
Address++;
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* RwPmio2 - Read/Write PMIO2
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - PMIO2 Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] AndMask - Data And Mask 32 bits
|
|
||||||
* @param[in] OrMask - Data OR Mask 32 bits
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
RwPmio2 (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN UINT32 AndMask,
|
|
||||||
IN UINT32 OrMask,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Result;
|
|
||||||
|
|
||||||
ReadPmio2 (Address, OpFlag, &Result, StdHeader);
|
|
||||||
Result = (Result & AndMask) | OrMask;
|
|
||||||
WritePmio2 (Address, OpFlag, &Result, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Read BIOSRAM
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - BIOSRAM Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] Value - Read Data Buffer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ReadBiosram (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
OpFlag = 1 << (OpFlag - 1);
|
|
||||||
for (i = 0; i < OpFlag; i++) {
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
|
|
||||||
Address++;
|
|
||||||
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Write BIOSRAM
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address - BIOSRAM Offset value
|
|
||||||
* @param[in] OpFlag - Access sizes
|
|
||||||
* @param[in] Value - Write Data Buffer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
WriteBiosram (
|
|
||||||
IN UINT8 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
OpFlag = 1 << (OpFlag - 1);
|
|
||||||
for (i = 0; i < OpFlag; i++) {
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
|
|
||||||
Address++;
|
|
||||||
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Record SMI Status
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
RecordSmiStatus (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINTN Index;
|
|
||||||
UINT8 SwSmiValue;
|
|
||||||
|
|
||||||
ACPIMMIO8 (0xfed80320) |= 0x01;
|
|
||||||
for ( Index = 0; Index < 20; Index++ ) {
|
|
||||||
ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index);
|
|
||||||
}
|
|
||||||
LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader);
|
|
||||||
ACPIMMIO8 (0xfed10040) = SwSmiValue;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Clear All SMI Status
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ClearAllSmiStatus (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINTN Index;
|
|
||||||
|
|
||||||
for ( Index = 0; Index < 20; Index++ ) {
|
|
||||||
ACPIMMIO8 (0xfed80280 + Index) |= 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@ -1,310 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH IO access common routine
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#include "FchPlatform.h"
|
|
||||||
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* ProgramPciByteTable - Program PCI register by table (8 bits data)
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] pPciByteTable - Table data pointer
|
|
||||||
* @param[in] dwTableSize - Table length
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ProgramPciByteTable (
|
|
||||||
IN REG8_MASK *pPciByteTable,
|
|
||||||
IN UINT16 dwTableSize,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
UINT8 dbBusNo;
|
|
||||||
UINT8 dbDevFnNo;
|
|
||||||
UINT8 Or8;
|
|
||||||
UINT8 Mask8;
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
dbBusNo = pPciByteTable->RegIndex;
|
|
||||||
dbDevFnNo = pPciByteTable->AndMask;
|
|
||||||
pPciByteTable++;
|
|
||||||
|
|
||||||
for ( i = 1; i < dwTableSize; i++ ) {
|
|
||||||
if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {
|
|
||||||
pPciByteTable++;
|
|
||||||
dbBusNo = pPciByteTable->RegIndex;
|
|
||||||
dbDevFnNo = pPciByteTable->AndMask;
|
|
||||||
pPciByteTable++;
|
|
||||||
i++;
|
|
||||||
} else {
|
|
||||||
PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;
|
|
||||||
Or8 = pPciByteTable->OrMask;
|
|
||||||
Mask8 = ~pPciByteTable->AndMask;
|
|
||||||
LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);
|
|
||||||
pPciByteTable++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] pAcpiTbl - Table data pointer
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ProgramFchAcpiMmioTbl (
|
|
||||||
IN ACPI_REG_WRITE *pAcpiTbl,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 i;
|
|
||||||
UINT8 Or8;
|
|
||||||
UINT8 Mask8;
|
|
||||||
UINT32 ddtempVar;
|
|
||||||
|
|
||||||
if (pAcpiTbl != NULL) {
|
|
||||||
if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
|
|
||||||
// Signature Checking
|
|
||||||
pAcpiTbl++;
|
|
||||||
for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
|
|
||||||
ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
|
|
||||||
Or8 = pAcpiTbl->DataOrMask;
|
|
||||||
Mask8 = ~pAcpiTbl->DataAndMask;
|
|
||||||
LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader);
|
|
||||||
pAcpiTbl++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] pSciMapTbl - Table data pointer
|
|
||||||
* @param[in] FchResetDataBlock
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ProgramFchSciMapTbl (
|
|
||||||
IN SCI_MAP_CONTROL *pSciMapTbl,
|
|
||||||
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
|
|
||||||
)
|
|
||||||
{
|
|
||||||
AMD_CONFIG_PARAMS *StdHeader;
|
|
||||||
|
|
||||||
UINT32 ddtempVar;
|
|
||||||
StdHeader = FchResetDataBlock->StdHeader;
|
|
||||||
|
|
||||||
if (pSciMapTbl != NULL) {
|
|
||||||
while (pSciMapTbl->InputPin != 0xFF) {
|
|
||||||
if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) {
|
|
||||||
ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin;
|
|
||||||
if (((pSciMapTbl->InputPin == FCH_SMI_xHC0Pme) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \
|
|
||||||
((pSciMapTbl->InputPin == FCH_SMI_xHC1Pme) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) {
|
|
||||||
} else {
|
|
||||||
LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
//Assert Warning "SCI map is invalid"
|
|
||||||
}
|
|
||||||
pSciMapTbl++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] pGpioTbl - Table data pointer
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ProgramFchGpioTbl (
|
|
||||||
IN GPIO_CONTROL *pGpioTbl
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (pGpioTbl != NULL) {
|
|
||||||
while (pGpioTbl->GpioPin != 0xFF) {
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction);
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + ((UINT32)pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte);
|
|
||||||
pGpioTbl++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] pSataPhyTbl - Table data pointer
|
|
||||||
* @param[in] FchResetDataBlock
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ProgramFchSataPhyTbl (
|
|
||||||
IN SATA_PHY_CONTROL *pSataPhyTbl,
|
|
||||||
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (pSataPhyTbl != NULL) {
|
|
||||||
while (pSataPhyTbl->PhyData != 0xFFFFFFFF) {
|
|
||||||
//to be implemented
|
|
||||||
pSataPhyTbl++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* GetChipSysMode - Get Chip status
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Value - Return Chip strap status
|
|
||||||
* StrapStatus [15.0] - Hudson-2 chip Strap Status
|
|
||||||
* @li <b>0001</b> - Not USED FWH
|
|
||||||
* @li <b>0002</b> - Not USED LPC ROM
|
|
||||||
* @li <b>0004</b> - EC enabled
|
|
||||||
* @li <b>0008</b> - Reserved
|
|
||||||
* @li <b>0010</b> - Internal Clock mode
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
GetChipSysMode (
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* IsImcEnabled - Is IMC Enabled
|
|
||||||
* @retval TRUE for IMC Enabled; FALSE for IMC Disabled
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
IsImcEnabled (
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 dbSysConfig;
|
|
||||||
GetChipSysMode (&dbSysConfig, StdHeader);
|
|
||||||
if (dbSysConfig & ChipSysEcEnable) {
|
|
||||||
return TRUE;
|
|
||||||
} else {
|
|
||||||
return FALSE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* GetEfuseStatue - Get Efuse status
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Value - Return Chip strap status
|
|
||||||
* @param[in] StdHeader
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
GetEfuseStatus (
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 Or8;
|
|
||||||
UINT8 Mask8;
|
|
||||||
|
|
||||||
Or8 = BIT5;
|
|
||||||
Mask8 = BIT5;
|
|
||||||
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
|
|
||||||
LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader);
|
|
||||||
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader);
|
|
||||||
Or8 = 0;
|
|
||||||
Mask8 = BIT5;
|
|
||||||
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* SbSleepTrapControl - SB Sleep Trap Control
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] SleepTrap - Whether sleep trap is enabled
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
SbSleepTrapControl (
|
|
||||||
IN BOOLEAN SleepTrap
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (SleepTrap) {
|
|
||||||
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
|
|
||||||
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2;
|
|
||||||
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) &= ~ (BIT5);
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1;
|
|
||||||
} else {
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) |= BIT5;
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
|
|
||||||
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0;
|
|
||||||
|
|
||||||
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@ -1,144 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH memory access lib
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#include "FchPlatform.h"
|
|
||||||
#include "Ids.h"
|
|
||||||
#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ReadMem - Read FCH BAR Memory
|
|
||||||
*
|
|
||||||
* @param[in] Address - Memory BAR address
|
|
||||||
* @param[in] OpFlag - Access width
|
|
||||||
* @param[in] *ValuePtr - In/Out value pointer
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
ReadMem (
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *ValuePtr
|
|
||||||
)
|
|
||||||
{
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
|
|
||||||
switch ( OpFlag ) {
|
|
||||||
case AccessWidth8:
|
|
||||||
*((UINT8*)ValuePtr) = *((volatile UINT8*) ((UINTN)Address));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case AccessWidth16:
|
|
||||||
*((UINT16*)ValuePtr) = *((volatile UINT16*) ((UINTN)Address));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case AccessWidth32:
|
|
||||||
*((UINT32*)ValuePtr) = *((volatile UINT32*) ((UINTN)Address));
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
ASSERT (FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* WriteMem - Write FCH BAR Memory
|
|
||||||
*
|
|
||||||
* @param[in] Address - Memory BAR address
|
|
||||||
* @param[in] OpFlag - Access width
|
|
||||||
* @param[in] *ValuePtr - In/Out Value pointer
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
WriteMem (
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *ValuePtr
|
|
||||||
)
|
|
||||||
{
|
|
||||||
OpFlag = OpFlag & 0x7f;
|
|
||||||
|
|
||||||
switch ( OpFlag ) {
|
|
||||||
case AccessWidth8 :
|
|
||||||
*((volatile UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case AccessWidth16:
|
|
||||||
*((volatile UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case AccessWidth32:
|
|
||||||
*((volatile UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
ASSERT (FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* RwMem - Read & Write FCH BAR Memory
|
|
||||||
*
|
|
||||||
* @param[in] Address - Memory BAR address
|
|
||||||
* @param[in] OpFlag - Access width
|
|
||||||
* @param[in] Mask - Mask Value of data
|
|
||||||
* @param[in] Data - Write data
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
RwMem (
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN UINT32 Mask,
|
|
||||||
IN UINT32 Data
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Result;
|
|
||||||
|
|
||||||
ReadMem (Address, OpFlag, &Result);
|
|
||||||
Result = (Result & Mask) | Data;
|
|
||||||
WriteMem (Address, OpFlag, &Result);
|
|
||||||
ReadMem (Address, OpFlag, &Result);
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,93 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH PCI access lib
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#include "FchPlatform.h"
|
|
||||||
#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE
|
|
||||||
|
|
||||||
VOID
|
|
||||||
ReadPci (
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID* Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
|
|
||||||
LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
VOID
|
|
||||||
WritePci (
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN VOID *Value,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
|
|
||||||
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
|
|
||||||
LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
VOID
|
|
||||||
RwPci (
|
|
||||||
IN UINT32 Address,
|
|
||||||
IN UINT8 OpFlag,
|
|
||||||
IN UINT32 Mask,
|
|
||||||
IN UINT32 Data,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
PCI_ADDR PciAddress;
|
|
||||||
UINT32 rMask;
|
|
||||||
|
|
||||||
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
|
|
||||||
rMask = ~Mask;
|
|
||||||
LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,117 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH platform definition
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#ifndef _FCH_PLATFORM_H_
|
|
||||||
#define _FCH_PLATFORM_H_
|
|
||||||
|
|
||||||
#define MAX_SATA_PORTS 8
|
|
||||||
|
|
||||||
#include "AGESA.h"
|
|
||||||
|
|
||||||
#ifndef FCHOEM_ACPI_RESTORE_SWSMI
|
|
||||||
#define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
|
|
||||||
#define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
|
|
||||||
#define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
|
|
||||||
#define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
|
|
||||||
#define FCHOEM_START_TIMER_SMI 0xBC
|
|
||||||
#define FCHOEM_STOP_TIMER_SMI 0xBD
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_SPI_UNLOCK_SWSMI
|
|
||||||
#define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
|
|
||||||
#endif
|
|
||||||
#ifndef FCHOEM_SPI_LOCK_SWSMI
|
|
||||||
#define FCHOEM_SPI_LOCK_SWSMI 0xAB
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
|
|
||||||
#define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
|
|
||||||
#define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
|
|
||||||
#define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_IO_DELAY_PORT
|
|
||||||
#define FCHOEM_IO_DELAY_PORT 0x80
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_OUTPUT_DEBUG_PORT
|
|
||||||
#define FCHOEM_OUTPUT_DEBUG_PORT 0x80
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define FCH_PCIRST_BASE_IO 0xCF9
|
|
||||||
#define FCH_PCI_RESET_COMMAND06 0x06
|
|
||||||
#define FCH_PCI_RESET_COMMAND0E 0x0E
|
|
||||||
#define FCH_KBDRST_BASE_IO 0x64
|
|
||||||
#define FCH_KBC_RESET_COMMAND 0xFE
|
|
||||||
#define FCH_ROMSIG_BASE_IO 0x20000l
|
|
||||||
#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul
|
|
||||||
#define FCH_MAX_TIMER 0xFFFFFFFFul
|
|
||||||
#define FCH_GEC_INTERNAL_REG 0x6804
|
|
||||||
#define FCH_HPET_REG_MASK 0xFFFFF800ul
|
|
||||||
#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef FCHOEM_ELAPSED_TIME_UNIT
|
|
||||||
#define FCHOEM_ELAPSED_TIME_UNIT 28
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
|
|
||||||
#define FCHOEM_ELAPSED_TIME_DIVIDER 100
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "Fch.h"
|
|
||||||
#include "amdlib.h"
|
|
||||||
#include "FchCommonCfg.h"
|
|
||||||
#include "AcpiLib.h"
|
|
||||||
#include "FchDef.h"
|
|
||||||
#include "FchBiosRamUsage.h"
|
|
||||||
#include "AmdFch.h"
|
|
||||||
|
|
||||||
extern BUILD_OPT_CFG UserOptions;
|
|
||||||
|
|
||||||
#endif // _FCH_PLATFORM_H_
|
|
||||||
@ -1,200 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* FCH registers definition
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: FCH
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#define KERN_FCH_SATA_DID 0x7900
|
|
||||||
#define KERN_FCH_SATA_AHCI_DID 0x7901
|
|
||||||
#define KERN_FCH_SATA_AMDAHCI_DID 0x7904
|
|
||||||
|
|
||||||
#define KERN_FCH_USB_XHCI_DID 0x7914 // Dev 0x10 Func 0
|
|
||||||
#define KERN_FCH_USB_EHCI_DID 0x7908 // Dev 0x12 Func 0
|
|
||||||
#define KERN_FCH_SMBUS_DID 0x790B // Dev 0x14 Func 0
|
|
||||||
#define KERN_FCH_LPC_DID 0x790E // Dev 0x14 Func 3
|
|
||||||
#define KERN_FCH_SD_DID 0x7906 // Dev 0x14 Func 7
|
|
||||||
|
|
||||||
#define KERN_EHCI1_BUS_DEV_FUN ((0x12 << 3) + 0)
|
|
||||||
#define KERN_EHCI1_BUS 0
|
|
||||||
#define KERN_EHCI1_DEV 18
|
|
||||||
#define KERN_EHCI1_FUNC 0
|
|
||||||
#define KERN_EHCI2_BUS_DEV_FUN ((0x13 << 3) + 0)
|
|
||||||
#define KERN_EHCI2_BUS 0
|
|
||||||
#define KERN_EHCI2_DEV 19
|
|
||||||
#define KERN_EHCI2_FUNC 0
|
|
||||||
#define KERN_EHCI3_BUS_DEV_FUN ((0x16 << 3) + 0)
|
|
||||||
#define KERN_EHCI3_BUS 0
|
|
||||||
#define KERN_EHCI3_DEV 22
|
|
||||||
#define KERN_EHCI3_FUNC 0
|
|
||||||
|
|
||||||
// Specific FCH register for Kern
|
|
||||||
#define FCH_EHCI_REG64 0x64
|
|
||||||
#define FCH_EHCI_REGA4 0xA4
|
|
||||||
|
|
||||||
// HD Audio/Azalia
|
|
||||||
#define KERN_EVENT_HD_AUDIO_MSI_ENABLE 0x02010100ul // HD Audio/Azalia MSI enable.
|
|
||||||
#define KERN_EVENT_HD_AUDIO_DISABLE 0x02010101ul // HD Audio/Azalia Disable.
|
|
||||||
#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC 0x02010102ul // HD Audio/Azalia Configure CODEC.
|
|
||||||
#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC_BUSY 0x02010103ul // HD Audio/Azalia Configure CODEC Reset.
|
|
||||||
#define KERN_ERROR_HD_AUDIO_RESET 0x02030100ul // HD Audio/Azalia Reset Failure.
|
|
||||||
#define KERN_ERROR_HD_AUDIO_CODEC 0x02030101ul // HD Audio/Azalia Codec Not Found.
|
|
||||||
// HW ACPI
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_ACPI_PMTBL 0x02010200ul // FCH program ACPI PM Controller Base Address.
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_ACPI_MMIO_IN_RESET 0x02010201ul // FCH program ACPIMMIO registers in RESET.
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_SCI_MAP 0x02010202ul // FCH program SCI map by OEM table (ACPIMMIO 0xFED803xx).
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_GPIO_MAP 0x02010203ul // FCH program GPIO setting by OEM table (ACPIMMIO 0xFED801xx).
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_SATA_PHY 0x02010204ul // FCH program SATA PHY by OEM table.
|
|
||||||
#define KERN_EVENT_RTC_DAYLIGHT_SAVING_TIME 0x02010205ul // FCH RTC DayLight Saving Workaround.
|
|
||||||
#define KERN_EVENT_RTC_CLEAR_BANK_SELECTION 0x02010206ul // FCH RTC clear BankSelection 0x0A Bit4 prevent error.
|
|
||||||
#define KERN_EVENT_RTC_WA 0x02010207ul // FCH RTC workaround is set.
|
|
||||||
#define KERN_EVENT_KBD_CONNECTED_THRU_USB 0x02010208ul // FCH IRQ1/IRQ12 connected to USB controller.
|
|
||||||
#define KERN_EVENT_LEGACY_FREE_SET 0x02010209ul // FCH None Legacy IO setting.
|
|
||||||
#define KERN_EVENT_ENABLED_ASF_REMOTE_CTRL 0x0201020Aul // FCH Enable ASF remote control function.
|
|
||||||
#define KERN_EVENT_PCIEXP_WAKESTATUS_WA 0x0201020Bul // FCH PciExp Wake Status Workaround.
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL_IN_RESET 0x0201020Cul // FCH program OEM/Platform BIOS ACPIMMIO registers.
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_MMIOTBL 0x02010200ul // FCH program ACPIMMIO registers. (1st.)
|
|
||||||
#define KERN_EVENT_HWACPI_NO_SIOKBC_ENABLE 0x02010201ul // FCH No SIO/KBC function is enabled.
|
|
||||||
#define KERN_EVENT_HWACPI_NO_SIOKBC_DISABLE 0x02010202ul // FCH No SIO/KBC function is disabled.
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_SPECIFIC_MMIOTBL 0x02010203ul // FCH program Specific ACPIMMIO registers. (2nd.)
|
|
||||||
#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL 0x02010204ul // FCH program OEM/Platform BIOS ACPIMMIO registers (3rd.)
|
|
||||||
#define KERN_EVENT_HWACPI_SPREAD_SPECTRUM 0x02010205ul // FCH Enable Spread Spectrum function.
|
|
||||||
#define KERN_EVENT_HWACPI_INT_CLK_SET 0x02010206ul // FCH Set Intermal Clock Display as 48Mhz.
|
|
||||||
#define KERN_EVENT_HPET_TIMER_TICK_INTERVAL_WA_SET 0x02010207ul // FCH HPET timer tick interval workaround is set.
|
|
||||||
#define KERN_EVENT_C1E_ENABLE 0x02010208ul // FCH C1e Enabled.
|
|
||||||
#define KERN_EVENT_NATIVEPCIE_MODE_SET 0x02010208ul // FCH Native PCIe mode is set.
|
|
||||||
#define KERN_ERROR_HPET_TBL_NOT_FOUND 0x02030200ul // FCH HPET Table does not found.
|
|
||||||
// HWM
|
|
||||||
#define KERN_EVENT_IMC_DISABLE 0x02010300ul // FCH HWM/IMC is disabled.
|
|
||||||
#define KERN_EVENT_IMC_ENABLE 0x02010301ul // FCH HWM/IMC is enabled.
|
|
||||||
// IMC
|
|
||||||
#define KERN_EVENT_IMC_SW_TOGGLE_EVENT 0x02010302ul // FCH IMC Software Toggle Strapping. (IMC statement change)
|
|
||||||
#define KERN_EVENT_EC_ENABLE 0x02020303ul // FCH EC enabled.
|
|
||||||
#define KERN_EVENT_EC_KBD_ENABLE 0x02010304ul // FCH IMC EC KBD enabled.
|
|
||||||
#define KERN_EVENT_EC_CHANNEL0_ENABLE 0x02010305ul // FCH IMC EC channel0 function enabled.
|
|
||||||
#define KERN_EVENT_IMC_INTO_SLEEP_MODE 0x02010306ul // FCH IMC goes into sleep mode.
|
|
||||||
#define KERN_EVENT_IMC_CRASH_RESET 0x02010307ul // FCH IMC Crash Reset to prevent repeating the reset forever.
|
|
||||||
#define KERN_EVENT_IMC_SW_DISABLE_IMC 0x02010308ul // FCH Software disable IMC thru mailbox command.
|
|
||||||
#define KERN_EVENT_IMC_DISABLE_SUREBOOT_TIMMER 0x02010309ul // FCH Disable SureBoot Timmer.
|
|
||||||
#define KERN_EVENT_IMC_WAKEUP 0x0201030Aul // FCH IMC wakeup command.
|
|
||||||
#define KERN_EVENT_IMC_IDLE 0x0201030Bul // FCH IMC idle command.
|
|
||||||
#define KERN_EVENT_EC_DISABLE 0x0201030Cul // FCH EC disable by jumper setting or board config.
|
|
||||||
#define KERN_ERROR_IMC_FW_VALIDATE_FAILED 0x02030300ul // FCH IMC firmware validation failure.
|
|
||||||
// PCIE/AB
|
|
||||||
#define KERN_EVENT_AB_SLOW_SPEED_ABLINK_CLOCK 0x02010400ul // FCH Set Low Speed AB link clock.
|
|
||||||
#define KERN_EVENT_AB_RESET_CPU_ON_SYNC_FLOOD 0x02010401ul // FCH set AB reset CPU on sync flood enabled.
|
|
||||||
#define KERN_EVENT_AB_CLOCK_GATING_ENABLE 0x02010402ul // FCH set AB Clock Gating function enabled.
|
|
||||||
#define KERN_EVENT_AB_CLOCK_GATING_DISABLE 0x02010403ul // FCH set AB clock Gating function disabled.
|
|
||||||
#define KERN_EVENT_AB_DMA_MEMORY_W3264B_ENABLE 0x02010404ul // FCH set AB DMA MEMORY Write 32/64B enabled.
|
|
||||||
#define KERN_EVENT_AB_DMA_MEMORY_W3264B_DISABLED 0x02010405ul // FCH set AB DMA MEMORY Write 32/64B disabled.
|
|
||||||
#define KERN_EVENT_AB_MEMORY_POWERSAVING_ENABLED 0x02010406ul // FCH Set AB Memory Power Saving enabled.
|
|
||||||
#define KERN_EVENT_AB_MEMORY_POWERSAVING_DISABLED 0x02010407ul // FCH Set AB Memory Power Saving disabled.
|
|
||||||
#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_ENABLED 0x02010408ul // FHC set ALink clock Gate-off enabled.
|
|
||||||
#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_DISABLED 0x02010409ul // FHC set ALink clock Gate-off disabled.
|
|
||||||
#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_ENABLED 0x0201040Aul // FHC set BLink clock Gate-off enabled.
|
|
||||||
#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_DISABLED 0x0201040Bul // FHC set BLink clock Gate-off disabled.
|
|
||||||
// SATA
|
|
||||||
#define KERN_EVENT_SATA_ENABLE 0x02010500ul // FCH set SATA controller enabled.
|
|
||||||
#define KERN_EVENT_SATA_MAX_GEN2_MODE_ENABLE 0x02010501ul // FCH set SATA support only Max. GEN2 mode.
|
|
||||||
#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_EXT 0x02010502ul // FCH set SATA clock source as external 48Mhz.
|
|
||||||
#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_INT 0x02010502ul // FCH set SATA clock source as internal 48Mhz.
|
|
||||||
#define KERN_EVENT_SATA_SET_CLK_SOURCE_100_INT 0x02010503ul // FCH set SATA clock source as internal 100Mhz.
|
|
||||||
#define KERN_EVENT_SATA_STABLE_MEM_SHUTDOWN_ENABLE 0x02010504ul // FCH set SATA stable memory sutdown enable * Misc.
|
|
||||||
#define KERN_EVENT_SATA_PROG_SATA_PORT_PHY 0x02010505ul // FCH programming SATA port's PHY.
|
|
||||||
#define KERN_EVENT_SATA_READ_SQUELCH_FROM_EFUSE 0x02010506ul // FCH programming SATA squelch value from eFuse.
|
|
||||||
#define KERN_EVENT_SATA_DISABLE 0x02010507ul // FCH set SATA controller disabled.
|
|
||||||
#define KERN_EVENT_SATA_AHCI_MODE 0x02010508ul // FCH set SATA as AHCI mode.
|
|
||||||
#define KERN_EVENT_SATA_IDE_2_AHCI_MODE 0x02010509ul // FCH set SATA as IDE_2_AHCI mode.
|
|
||||||
#define KERN_EVENT_SATA_IDE_MODE 0x0201050Aul // FCH set SATA as IDE mode.
|
|
||||||
#define KERN_EVENT_SATA_RAID_MODE 0x0201050Bul // FCH set SATA as RAID mode.
|
|
||||||
#define KERN_EVENT_SATA_MSI_CAP_ENABLE 0x0201050Cul // FCH set SATA MSI Capability Enabled.
|
|
||||||
#define KERN_EVENT_SATA_SUPPORT_8_DEVICE 0x0201050Dul // FCH set SATA support 8 device mode.
|
|
||||||
#define KERN_EVENT_SATA_DISABLED_GENERIC_MODE 0x0201050Eul // FCH set SATA disable generic mode.
|
|
||||||
#define KERN_EVENT_SATA_PHY_PLL_SHUTDOWN 0x0201050Ful // FCH set SATA PHY PLL shutdown.
|
|
||||||
#define KERN_EVENT_SATA_OOB_DETECTION_ENH 0x02010510ul // FCH set SATA OOB Detection Enhance Mode.
|
|
||||||
#define KERN_EVENT_SATA_MEM_POWER_SAVING 0x02010511ul // FCH set SATA memory power saving.
|
|
||||||
#define KERN_EVENT_SATA_DEV_SLP_PORT0 0x02010512ul // FCH set SATA Deep Sleep Mode on Port0.
|
|
||||||
#define KERN_EVENT_SATA_DEV_SLP_PORT1 0x02010513ul // FCH set SATA Deep Sleep Mode on Port1.
|
|
||||||
#define KERN_EVENT_SATA_AHCI_DIS_PREFETCH 0x02010514ul // FCH set SATA AHCI disable Prefetch.
|
|
||||||
#define KERN_EVENT_SATA_PORT_MULT_CAP 0x02010515ul // FCH set SATA Port Mult Capability Enabled.
|
|
||||||
#define KERN_EVENT_SATA_FIS_BASE_SWITCHING 0x02010516ul // FCH set SATA support FIS-based switching.
|
|
||||||
#define KERN_EVENT_SATA_AGGR_LINK_PM_CAP 0x02010517ul // FCH set SATA aggressive link power management.
|
|
||||||
#define KERN_EVENT_SATA_PSC_CAP 0x02010518ul // FCH set SATA support partial state.
|
|
||||||
#define KERN_EVENT_SATA_SSC_CAP 0x02010519ul // FCH set SATA support Slumber mode.
|
|
||||||
#define KERN_EVENT_SATA_CCC_CAP 0x0201051Aul // FCH set SATA support command completion coalescing.
|
|
||||||
#define KERN_EVENT_SATA_AHCI_ENCLOSURE_MANAGEMENT 0x0201051Bul // FCH set SATA support Enclosure Management.
|
|
||||||
#define KERN_EVENT_SATA_ESP_PORT_ENABLE 0x0201051Cul // FCH set SATA ESP ports (one of ESP ports are set).
|
|
||||||
#define KERN_EVENT_SATA_BIOS_OS_HANDOFF 0x0201051Dul // FCH set SATA HBA supports the BIOS/OS handoff mechanism.
|
|
||||||
#define KERN_EVENT_SATA_DRIVE_DETECTION 0x0201051Eul // FCH SATA is excuting SATA drive detection.
|
|
||||||
#define KERN_EVENT_SATA_CLK_AUTO_OFF 0x0201051Ful // FCH set SATA Auto Clock off function.
|
|
||||||
#define KERN_EVENT_SATA_PORT_GEN_MODE 0x02010520ul // FCH set SATA port GEN mode.
|
|
||||||
#define KERN_EVENT_SATA_HOT_REMOVAL_ENH 0x02010521ul // FCH set SATA hot removal enhance mode.
|
|
||||||
// SD
|
|
||||||
#define KERN_EVENT_SD_ENABLE 0x02010600ul // FCH set SD controller to enable.
|
|
||||||
#define KERN_EVENT_SD_AS_DMA_MODE 0x02010601ul // FCH set SD as DMA mode.
|
|
||||||
#define KERN_EVENT_SD_AS_PIO_MODE 0x02010602ul // FCH set SD as PIO mode.
|
|
||||||
#define KERN_EVENT_SD_AS_2_0_MODE 0x02010603ul // FCH set SD as 2.0 mode.
|
|
||||||
#define KERN_EVENT_SD_AS_3_0_MODE 0x02010604ul // FCH set SD as 3.0 mode.
|
|
||||||
#define KERN_EVENT_SD_CLOCK_MULTIPLIER 0x02010605ul // FCH set SD clock multiplier.
|
|
||||||
#define KERN_EVENT_SD_DISABLE 0x02010606ul // FCH set SD controller to disable.
|
|
||||||
// LPC/SPI
|
|
||||||
#define KERN_EVENT_LPC_CLK0_DISABLE 0x02010700ul // FCH set LPC0 clock disabled.
|
|
||||||
#define KERN_EVENT_LPC_CLK1_DISABLE 0x02010701ul // FCH set LPC1 clock disabled.
|
|
||||||
#define KERN_EVENT_LPC_LEGACY_FREE_MODE 0x02010702ul // FCH set LPC as legacy free mode.
|
|
||||||
#define KERN_EVENT_SPI_QUAL_MODE 0x02010703ul // FCH SPI Qual Mode is enabled (by user selection).
|
|
||||||
#define KERN_EVENT_SPI_SPEED 0x02010704ul // FCH SPI speed is set by user selection.
|
|
||||||
#define KERN_EVENT_SPI_FAST_SPEED 0x02010705ul // FCH SPI fast speed is set.
|
|
||||||
#define KERN_EVENT_SPI_QUALIFY_QUAL_MODE 0x02010706ul // FCH SPI Qual Mode is validated.
|
|
||||||
// USB
|
|
||||||
#define KERN_ERROR_USB_ROMSIG_NOT_FOUND 0x02030800ul // FCH ROMSIG not found.
|
|
||||||
#define KERN_ERROR_USB_XHCI_FW_FOUND 0x02030801ul // FCH XHCI firmware does not exist.
|
|
||||||
#define KERN_EVENT_USB_EHCI1_ENABLE 0x02010800ul // FCH set EHCI1 enable.
|
|
||||||
#define KERN_EVENT_USB_EHCI2_ENABLE 0x02010801ul // FCH set EHCI2 enable.
|
|
||||||
#define KERN_EVENT_USB_EHCI3_ENABLE 0x02010802ul // FCH set EHCI3 enable.
|
|
||||||
#define KERN_EVENT_USB_XHCI_DISABLE 0x02010803ul // FCH set XHCI disable.
|
|
||||||
#define KERN_EVENT_USB_PHY_POWER_DOWN 0x02010804ul // FCH set USB PHY powerdown enable.
|
|
||||||
#define KERN_EVENT_USB_PHY_CALIBRATED 0x02010805ul // FCH set USB PHY calibrated.
|
|
||||||
#define KERN_EVENT_USB_PORT_PHY_SETTING 0x02010806ul // FCH set USB Port PHY setting.
|
|
||||||
#define KERN_EVENT_USB_PORT_PHY_CLK_GATING 0x02010807ul // FCH set USB Port PHY Clock Gating.
|
|
||||||
#define KERN_EVENT_USB_XHCI_USED_PREDEFINE_ADDRESS 0x02010808ul // FCH XHCI ROM location is used user-define address.
|
|
||||||
#define KERN_EVENT_USB_XHCI_BOOTRAM_PRELOAD 0x02010809ul // FCH XHCI preload its BOOTRAM.
|
|
||||||
#define KERN_EVENT_USB_XHCI_INSTRUCTRAM_PRELOAD 0x0201080Aul // FCH XHCI preload its InstructionRAM.
|
|
||||||
#define KERN_EVENT_USB_XHCI_ROM_PREINIT_COMPLETED 0x0201080Bul // FCH XHCI preinit completed.
|
|
||||||
#define KERN_EVENT_USB_XHCI0_ENABLE 0x0201080Cul // FCH set XHCI0 enable.
|
|
||||||
#define KERN_EVENT_USB_XHCI1_ENABLE 0x0201080Dul // FCH set XHCI1 enable.
|
|
||||||
@ -1,464 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* PSP Base Library
|
|
||||||
*
|
|
||||||
* Contains interface to the PSP library
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: PSP
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* M O D U L E S U S E D
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#include "AGESA.h"
|
|
||||||
#include "Filecode.h"
|
|
||||||
#include "PspBaseLib.h"
|
|
||||||
|
|
||||||
#define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE
|
|
||||||
#define PSP_BAR1_TMP_BASE 0xFEA00000ul
|
|
||||||
|
|
||||||
#define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF)
|
|
||||||
#define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F)
|
|
||||||
#define GET_PCI_FUNC(Reg) (((UINT32) Reg >> 8) & 0x7)
|
|
||||||
#define GET_PCI_OFFSET(Reg) ((UINT32)Reg & 0xFF)
|
|
||||||
|
|
||||||
#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb Offset index for SMU mbox
|
|
||||||
#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb Offset data for SMU mbox
|
|
||||||
|
|
||||||
#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< offset in GNB to find PSP fusing
|
|
||||||
#define SMU_CC_PSP_FUSES_SECURE BIT0 ///< BIT0
|
|
||||||
#define SMU_CC_PSP_FUSES_FRA_ENABLE BIT1 ///< BIT1
|
|
||||||
#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2
|
|
||||||
#define PLATFORM_SECURE_BOOT_EN BIT4 ///< BIT4
|
|
||||||
|
|
||||||
|
|
||||||
#define PSP_BLANK_PART 0 ///< Blank part
|
|
||||||
#define PSP_PROTO_PART SMU_CC_PSP_FUSES_PROTO ///< Proto Part
|
|
||||||
#define PSP_NON_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_PCPU_DIS) ///< Non Secure Part
|
|
||||||
#define PSP_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< Secure Part
|
|
||||||
#define PSP_FRA_MODE (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< FRA Part
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* D E F I N I T I O N S A N D M A C R O S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* T Y P E D E F S A N D S T R U C T U R E S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------
|
|
||||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
|
||||||
*----------------------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
PspLibPciReadConfig (
|
|
||||||
IN UINT32 Register
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Value;
|
|
||||||
PCI_ADDR PciAddr;
|
|
||||||
|
|
||||||
Value = 0;
|
|
||||||
PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register));
|
|
||||||
|
|
||||||
LibAmdPciRead (AccessWidth32, PciAddr, &Value, NULL);
|
|
||||||
|
|
||||||
return Value;
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID
|
|
||||||
PspLibPciWriteConfig (
|
|
||||||
IN UINT32 Register,
|
|
||||||
IN UINT32 Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
PCI_ADDR PciAddr;
|
|
||||||
PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register));
|
|
||||||
|
|
||||||
LibAmdPciWrite (AccessWidth32, PciAddr, &Value, NULL);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
PspLibPciReadPspConfig (
|
|
||||||
IN UINT16 Offset
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return (PspLibPciReadConfig ((UINT32) (PSP_PCI_BDA + Offset)));
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID
|
|
||||||
PspLibPciWritePspConfig (
|
|
||||||
IN UINT16 Offset,
|
|
||||||
IN UINT32 Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
PspLibPciWriteConfig ((UINT32) (PSP_PCI_BDA + Offset), Value);
|
|
||||||
}
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
GetPspDirBase (
|
|
||||||
IN OUT UINT32 *Address
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINTN i;
|
|
||||||
FIRMWARE_ENTRY_TABLE *FirmwareTableBase;
|
|
||||||
CONST UINT32 RomSigAddrTable[] =
|
|
||||||
{
|
|
||||||
0xFFFA0000, // --> 512KB base
|
|
||||||
0xFFF20000, // --> 1MB base
|
|
||||||
0xFFE20000, // --> 2MB base
|
|
||||||
0xFFC20000, // --> 4MB base
|
|
||||||
0xFF820000, // --> 8MB base
|
|
||||||
0xFF020000 // --> 16MB base
|
|
||||||
};
|
|
||||||
|
|
||||||
for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) {
|
|
||||||
FirmwareTableBase = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i];
|
|
||||||
// Search flash for unique signature 0x55AA55AA
|
|
||||||
if (FirmwareTableBase->Signature == FIRMWARE_TABLE_SIGNATURE) {
|
|
||||||
*Address = FirmwareTableBase->PspDirBase;
|
|
||||||
return TRUE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
PSPEntryInfo (
|
|
||||||
IN PSP_DIRECTORY_ENTRY_TYPE EntryType,
|
|
||||||
IN OUT UINT64 *EntryAddress,
|
|
||||||
IN UINT32 *EntrySize
|
|
||||||
)
|
|
||||||
{
|
|
||||||
PSP_DIRECTORY *PspDir;
|
|
||||||
UINTN i;
|
|
||||||
|
|
||||||
if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
|
|
||||||
return FALSE;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < PspDir->Header.TotalEntries; i++) {
|
|
||||||
if (PspDir->PspEntry[i].Type == EntryType) {
|
|
||||||
*EntryAddress = PspDir->PspEntry[i].Location;
|
|
||||||
*EntrySize = PspDir->PspEntry[i].Size;
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Check if PSP device is present
|
|
||||||
|
|
||||||
@retval BOOLEAN 0: PSP Disabled, 1: PSP Enabled
|
|
||||||
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
CheckPspDevicePresent (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 SecureFuseReg;
|
|
||||||
PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS);
|
|
||||||
SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA);
|
|
||||||
|
|
||||||
if (SecureFuseReg &= SMU_CC_PSP_FUSES_PROTO) {
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Check PSP Platform Seucre Enable State
|
|
||||||
HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode)
|
|
||||||
will be applied if Psp Plaform Secure is enabled
|
|
||||||
|
|
||||||
@retval BOOLEAN 0: PSP Platform Secure Disabled, 1: PSP Platform Secure Enabled
|
|
||||||
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
CheckPspPlatformSecureEnable (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 SecureFuseReg;
|
|
||||||
PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS);
|
|
||||||
SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA);
|
|
||||||
|
|
||||||
if (SecureFuseReg &= PLATFORM_SECURE_BOOT_EN) {
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Check PSP Recovery Flag
|
|
||||||
Target will set Recovery flag if some PSP entry point by PSP directory has been corrupted.
|
|
||||||
|
|
||||||
@retval BOOLEAN 0: Recovery Flag is cleared, 1: Recovery Flag has been set
|
|
||||||
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
CheckPspRecoveryFlag (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
MBOX_STATUS *MboxStatus;
|
|
||||||
|
|
||||||
//Init PSP MMIO
|
|
||||||
PspBarInitEarly ();
|
|
||||||
|
|
||||||
GetPspMboxStatus (&MboxStatus);
|
|
||||||
|
|
||||||
return (BOOLEAN) (MboxStatus->Recovery);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the PspMbox MMIO location
|
|
||||||
|
|
||||||
|
|
||||||
@retval BOOLEAN FALSE: ERROR, TRUE: SUCCEED
|
|
||||||
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
GetPspMboxStatus (
|
|
||||||
IN OUT MBOX_STATUS **MboxStatus
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 PspMmio;
|
|
||||||
|
|
||||||
if (GetPspBar1Addr (&PspMmio) == FALSE) {
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
*MboxStatus = (MBOX_STATUS *)( (UINTN)PspMmio + PSP_MAILBOX_BASE + PSP_MAILBOX_STATUS_OFFSET); // PSPMbox base is at offset CP2MSG_28 ie. offset 28*4 = 0x70
|
|
||||||
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
PspBarInitEarly (void)
|
|
||||||
{
|
|
||||||
UINT32 PspMmioSize;
|
|
||||||
UINT32 Value32;
|
|
||||||
|
|
||||||
if (PspLibPciReadPspConfig (PSP_PCI_DEVID_REG) == 0xffffffff) {
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
//Check if PSP BAR has been assigned, if not do the PSP BAR initialation
|
|
||||||
if (PspLibPciReadPspConfig (PSP_PCI_BAR1_REG) == 0) {
|
|
||||||
/// Get PSP BAR1 Size
|
|
||||||
PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, 0xFFFFFFFF);
|
|
||||||
PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
|
|
||||||
PspMmioSize = ~PspMmioSize + 1;
|
|
||||||
/// Assign BAR1 Temporary Address
|
|
||||||
PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, PSP_BAR1_TMP_BASE);
|
|
||||||
PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06);
|
|
||||||
|
|
||||||
/// Enable GNB redirection to this space @todo use equate & also find proper fix
|
|
||||||
PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR1_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF);
|
|
||||||
PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR1_TMP_BASE >> 8) | 3);
|
|
||||||
/// Enable MsixBarEn, Bar1En, Bar3En
|
|
||||||
PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34);
|
|
||||||
/// Capability chain update
|
|
||||||
Value32 = PspLibPciReadPspConfig (PSP_PCI_MIRRORCTRL1_REG);
|
|
||||||
Value32 &= ~D8F0x44_PmNxtPtrW_MASK;
|
|
||||||
Value32 |= 0xA4;
|
|
||||||
PspLibPciWritePspConfig (PSP_PCI_MIRRORCTRL1_REG, Value32);
|
|
||||||
}
|
|
||||||
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the PspMMIO MMIO location
|
|
||||||
|
|
||||||
@param[in] PspMmio Pointer to Psp MMIO address
|
|
||||||
|
|
||||||
@retval BOOLEAN 0: Error, 1 Success
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
GetPspBar1Addr (
|
|
||||||
IN OUT UINT32 *PspMmio
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (CheckPspDevicePresent () == FALSE) {
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
*PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
|
|
||||||
|
|
||||||
if ((*PspMmio) == 0xffffffff) {
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the PspMMIO MMIO location
|
|
||||||
|
|
||||||
@param[in] PspMmio Pointer to Psp MMIO address
|
|
||||||
|
|
||||||
@retval BOOLEAN 0: Error, 1 Success
|
|
||||||
**/
|
|
||||||
BOOLEAN
|
|
||||||
GetPspBar3Addr (
|
|
||||||
IN OUT UINT32 *PspMmio
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (CheckPspDevicePresent () == FALSE) {
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
*PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG);
|
|
||||||
|
|
||||||
if ((*PspMmio) == 0xffffffff) {
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
return (TRUE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Returns the access width mask for the processor
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] AccessWidth Access width
|
|
||||||
* @retval Width in number of bytes
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
UINT8
|
|
||||||
PspLibAccessWidth (
|
|
||||||
IN ACCESS_WIDTH AccessWidth
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT8 Width;
|
|
||||||
|
|
||||||
switch (AccessWidth) {
|
|
||||||
case AccessWidth8:
|
|
||||||
case AccessS3SaveWidth8:
|
|
||||||
Width = 1;
|
|
||||||
break;
|
|
||||||
case AccessWidth16:
|
|
||||||
case AccessS3SaveWidth16:
|
|
||||||
Width = 2;
|
|
||||||
break;
|
|
||||||
case AccessWidth32:
|
|
||||||
case AccessS3SaveWidth32:
|
|
||||||
Width = 4;
|
|
||||||
break;
|
|
||||||
case AccessWidth64:
|
|
||||||
case AccessS3SaveWidth64:
|
|
||||||
Width = 8;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
Width = 0;
|
|
||||||
}
|
|
||||||
return Width;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Read GNB indirect registers
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address PCI address of indirect register
|
|
||||||
* @param[in] IndirectAddress Offset of indirect register
|
|
||||||
* @param[in] Width Width
|
|
||||||
* @param[out] Value Pointer to value
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
PspLibPciIndirectRead (
|
|
||||||
IN PCI_ADDR Address,
|
|
||||||
IN UINT32 IndirectAddress,
|
|
||||||
IN ACCESS_WIDTH Width,
|
|
||||||
OUT VOID *Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 IndexOffset;
|
|
||||||
|
|
||||||
IndexOffset = PspLibAccessWidth (Width);
|
|
||||||
LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
|
|
||||||
Address.AddressValue += IndexOffset;
|
|
||||||
LibAmdPciRead (Width, Address, Value, NULL);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Write GNB indirect registers
|
|
||||||
*
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] Address PCI address of indirect register
|
|
||||||
* @param[in] IndirectAddress Offset of indirect register
|
|
||||||
* @param[in] Width Width
|
|
||||||
* @param[in] Value Pointer to value
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
PspLibPciIndirectWrite (
|
|
||||||
IN PCI_ADDR Address,
|
|
||||||
IN UINT32 IndirectAddress,
|
|
||||||
IN ACCESS_WIDTH Width,
|
|
||||||
IN VOID *Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 IndexOffset;
|
|
||||||
|
|
||||||
IndexOffset = PspLibAccessWidth (Width);
|
|
||||||
LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
|
|
||||||
Address.AddressValue += IndexOffset;
|
|
||||||
LibAmdPciWrite (Width, Address, Value, NULL);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,198 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* PSP Base Library
|
|
||||||
*
|
|
||||||
* Contains interface to the PSP library
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: PSP
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _PSP_BASE_LIB_H_
|
|
||||||
#define _PSP_BASE_LIB_H_
|
|
||||||
|
|
||||||
#include "AMD.h"
|
|
||||||
#include "amdlib.h"
|
|
||||||
#include "PspDirectory.h"
|
|
||||||
|
|
||||||
#define PSP_PCI_SEG 0x00 ///< PSP Seg address
|
|
||||||
#define PSP_PCI_BUS 0x00 ///< PSP Bus address
|
|
||||||
#define PSP_PCI_DEV 0x08 ///< PSP Device address
|
|
||||||
#define PSP_PCI_FN 0x00 ///< PSP Fn address
|
|
||||||
#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8))
|
|
||||||
#define GET_PSP_PCI_ADDR (Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)
|
|
||||||
|
|
||||||
#define PSP_PCI_DEVID_REG 0x00 ///< DevId
|
|
||||||
#define PSP_PCI_CMD_REG 0x04 ///< CmdReg
|
|
||||||
#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1
|
|
||||||
#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3
|
|
||||||
#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1
|
|
||||||
#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr
|
|
||||||
#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability
|
|
||||||
|
|
||||||
#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR)
|
|
||||||
|
|
||||||
#define D8F0x44_PmNxtPtrW_MASK 0xff
|
|
||||||
|
|
||||||
#define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR
|
|
||||||
#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset
|
|
||||||
|
|
||||||
#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port
|
|
||||||
#define PMIO_DATA_PORT 0xCD7 ///Pmio data port
|
|
||||||
|
|
||||||
#define PMIO_REG62 0x62 ///PMIOx62
|
|
||||||
|
|
||||||
//======================================================================================
|
|
||||||
//
|
|
||||||
// Define Mailbox Status field
|
|
||||||
//
|
|
||||||
//======================================================================================
|
|
||||||
//
|
|
||||||
/// MBox Status MMIO space
|
|
||||||
///
|
|
||||||
typedef struct {
|
|
||||||
UINT32 MboxInitialized:1; ///< Target will set this to 1 to indicate it is initialized (for ex. PSP/TPM ready)
|
|
||||||
UINT32 Error:1; ///< Target in adddtion to Done bit will also set this bit to indicate success/error on last command
|
|
||||||
UINT32 Terminated:1; ///< Target will set this bit if it aborted the command due to abort request
|
|
||||||
UINT32 Halt:1; ///< Target will set this error if there is critical error that require reset etc
|
|
||||||
UINT32 Recovery:1; ///< Target will set this error if some PSP entry point by PSP directory has been corrupted.
|
|
||||||
UINT32 Reserved:27; ///< Reserved
|
|
||||||
} MBOX_STATUS;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Above defined as bitmap
|
|
||||||
#define MBOX_STATUS_INITIALIZED 0x00000001ul ///< Mailbox Status: Initialized
|
|
||||||
#define MBOX_STATUS_ERROR 0x00000002ul ///< Mailbox Status: Error
|
|
||||||
#define MBOX_STATUS_ABORT 0x00000004ul ///< Mailbox Status: Abort
|
|
||||||
#define MBOX_STATUS_HALT 0x00000008ul ///< Mailbox Status: Halt
|
|
||||||
#define MBOX_STATUS_RECOVERY 0x00000010ul ///< Mailbox Status: Recovery required
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
PspLibPciReadConfig (
|
|
||||||
IN UINT32 Register
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
PspLibPciWriteConfig (
|
|
||||||
IN UINT32 Register,
|
|
||||||
IN UINT32 Value
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
PspLibPciReadPspConfig (
|
|
||||||
IN UINT16 Offset
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
PspLibPciWritePspConfig (
|
|
||||||
IN UINT16 Offset,
|
|
||||||
IN UINT32 Value
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
GetPspDirBase (
|
|
||||||
IN OUT UINT32 *Address
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
PSPEntryInfo (
|
|
||||||
IN PSP_DIRECTORY_ENTRY_TYPE EntryType,
|
|
||||||
IN OUT UINT64 *EntryAddress,
|
|
||||||
IN UINT32 *EntrySize
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
CheckPspDevicePresent (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
CheckPspPlatformSecureEnable (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
CheckPspRecoveryFlag (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
GetPspBar1Addr (
|
|
||||||
IN OUT UINT32 *PspMmio
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
GetPspBar3Addr (
|
|
||||||
IN OUT UINT32 *PspMmio
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
GetPspMboxStatus (
|
|
||||||
IN OUT MBOX_STATUS **MboxStatus
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
PspBarInitEarly (VOID);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
PspLibPciIndirectRead (
|
|
||||||
IN PCI_ADDR Address,
|
|
||||||
IN UINT32 IndirectAddress,
|
|
||||||
IN ACCESS_WIDTH Width,
|
|
||||||
OUT VOID *Value
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
PspLibPciIndirectWrite (
|
|
||||||
IN PCI_ADDR Address,
|
|
||||||
IN UINT32 IndirectAddress,
|
|
||||||
IN ACCESS_WIDTH Width,
|
|
||||||
IN VOID *Value
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT8
|
|
||||||
PspLibAccessWidth (
|
|
||||||
IN ACCESS_WIDTH AccessWidth
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
IsS3Resume (VOID);
|
|
||||||
|
|
||||||
#endif // _AMD_LIB_H_
|
|
||||||
@ -1,94 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* PSP directory related functions Prototype definition
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: PSP
|
|
||||||
* @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _PSP_DIRECTORY_H_
|
|
||||||
#define _PSP_DIRECTORY_H_
|
|
||||||
|
|
||||||
|
|
||||||
#define FIRMWARE_TABLE_SIGNATURE 0x55AA55AAul
|
|
||||||
/// Define the structure OEM signature table
|
|
||||||
typedef struct _FIRMWARE_ENTRY_TABLE {
|
|
||||||
UINT32 Signature; ///< Signature should be 0x55AA55AAul
|
|
||||||
UINT32 ImcRomBase; ///< Base Address for Imc Firmware
|
|
||||||
UINT32 GecRomBase; ///< Base Address for Gmc Firmware
|
|
||||||
UINT32 XHCRomBase; ///< Base Address for XHCI Firmware
|
|
||||||
UINT32 PspDirBase; ///< Base Address for PSP directory
|
|
||||||
} FIRMWARE_ENTRY_TABLE;
|
|
||||||
|
|
||||||
/// Define structure for PSP directory
|
|
||||||
typedef struct {
|
|
||||||
UINT32 PspCookie; ///< "$PSP"
|
|
||||||
UINT32 Checksum; ///< 32 bit CRC of header items below and the entire table
|
|
||||||
UINT32 TotalEntries; ///< Number of PSP Entries
|
|
||||||
UINT32 Reserved; ///< Unused
|
|
||||||
} PSP_DIRECTORY_HEADER;
|
|
||||||
|
|
||||||
|
|
||||||
/// define various enum type for PSP entry type
|
|
||||||
enum _PSP_DIRECTORY_ENTRY_TYPE {
|
|
||||||
AMD_PUBLIC_KEY = 0, ///< PSP entry pointer to AMD public key
|
|
||||||
PSP_FW_BOOT_LOADER = 1, ///< PSP entry points to PSP boot loader in SPI space
|
|
||||||
PSP_FW_TRUSTED_OS = 2, ///< PSP entry points to PSP Firmware region in SPI space
|
|
||||||
PSP_FW_RECOVERY_BOOT_LOADER = 3, ///< PSP entry point to PSP recovery region.
|
|
||||||
PSP_NV_DATA = 4, ///< PSP entry points to PSP data region in SPI space
|
|
||||||
BIOS_PUBLIC_KEY = 5, ///< PSP entry points to BIOS public key stored in SPI space
|
|
||||||
BIOS_RTM_FIRMWARE = 6, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space
|
|
||||||
BIOS_RTM_SIGNATURE = 7, ///< PSP entry points to signed BIOS RTM hash stored in SPI space
|
|
||||||
SMU_OFFCHIP_FW = 8 ///< PSP entry points to SMU image
|
|
||||||
};
|
|
||||||
typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE;
|
|
||||||
|
|
||||||
/// Structure for PSP Entry
|
|
||||||
typedef struct {
|
|
||||||
PSP_DIRECTORY_ENTRY_TYPE Type; ///< Type of PSP entry; 32 bit long
|
|
||||||
UINT32 Size; ///< Size of PSP Entry in bytes
|
|
||||||
UINT64 Location; ///< Location of PSP Entry (byte offset from start of SPI-ROM)
|
|
||||||
} PSP_DIRECTORY_ENTRY;
|
|
||||||
|
|
||||||
/// Structure for PSP directory
|
|
||||||
typedef struct {
|
|
||||||
PSP_DIRECTORY_HEADER Header; ///< PSP directory header
|
|
||||||
PSP_DIRECTORY_ENTRY PspEntry[1]; ///< Array of PSP entries each pointing to a binary in SPI flash
|
|
||||||
///< The actual size of this array comes from the
|
|
||||||
///< header (PSP_DIRECTORY.Header.TotalEntries)
|
|
||||||
} PSP_DIRECTORY;
|
|
||||||
|
|
||||||
#endif //_PSP_DIRECTORY_H_
|
|
||||||
@ -1,124 +0,0 @@
|
|||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* IDS Option File
|
|
||||||
*
|
|
||||||
* This file is used to switch on/off IDS features.
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Core
|
|
||||||
* @e \$Revision: 192403 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
|
|
||||||
*/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
***************************************************************************/
|
|
||||||
#include "Ids.h"
|
|
||||||
|
|
||||||
#ifndef _OPTION_IDS_H_
|
|
||||||
#define _OPTION_IDS_H_
|
|
||||||
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* This file generates the defaults tables for the Integrated Debug Support
|
|
||||||
* Module. The documented build options are imported from a user controlled
|
|
||||||
* file for processing. The build options for the Integrated Debug Support
|
|
||||||
* Module are listed below:
|
|
||||||
*
|
|
||||||
* IDSOPT_IDS_ENABLED
|
|
||||||
* IDSOPT_ERROR_TRAP_ENABLED
|
|
||||||
* IDSOPT_CONTROL_ENABLED
|
|
||||||
*
|
|
||||||
* Warning: When you enable the IDSOPT_CONTROL_NV_TO_CMOS feature.
|
|
||||||
* please make the cmos region defined by IDS_OPT_CMOS_REGION_START &
|
|
||||||
* IDS_OPT_CMOS_REGION_END can be touched between IDS HOOK point
|
|
||||||
* IDS_CPU_Early_Override and IDS_BEFORE_AP_EARLY_HALT of BSP
|
|
||||||
*
|
|
||||||
* IDSOPT_CONTROL_NV_TO_CMOS
|
|
||||||
* IDS_OPT_CMOS_INDEX_PORT
|
|
||||||
* IDS_OPT_CMOS_DATA_PORT
|
|
||||||
* IDS_OPT_CMOS_REGION_START
|
|
||||||
* IDS_OPT_CMOS_REGION_END
|
|
||||||
*
|
|
||||||
* IDSOPT_TRACING_ENABLED
|
|
||||||
* IDSOPT_TRACING_CONSOLE_HDTOUT
|
|
||||||
* IDSOPT_TRACING_CONSOLE_SERIALPORT
|
|
||||||
* IDSOPT_SERIAL_PORT (default 0x3F8)
|
|
||||||
* IDSOPT_TRACING_CONSOLE_REDIRECT_IO
|
|
||||||
* IDSOPT_DEBUG_PRINT_IO_PORT (default 0x80)
|
|
||||||
* IDSOPT_TRACING_CONSOLE_RAM
|
|
||||||
* IDSOPT_DPRAM_BASE
|
|
||||||
* IDSOPT_DPRAM_SIZE
|
|
||||||
* IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL (default FALSE)
|
|
||||||
* IDSOPT_CUSTOMIZE_TRACING_SERVICE
|
|
||||||
* IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
|
|
||||||
* IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
|
|
||||||
*
|
|
||||||
* IDSOPT_TRACE_BLD_CFG
|
|
||||||
* IDSOPT_PERF_ANALYSIS
|
|
||||||
* IDSOPT_ASSERT_ENABLED
|
|
||||||
* IDS_DEBUG_PORT
|
|
||||||
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
|
||||||
* IDSOPT_DEBUG_CODE_ENABLED
|
|
||||||
* IDSOPT_IDT_EXCEPTION_TRAP
|
|
||||||
* IDSOPT_C_OPTIMIZATION_DISABLED
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//#include "Ids.h"
|
|
||||||
|
|
||||||
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
#define IDSOPT_IDS_ENABLED TRUE
|
|
||||||
//#define IDSOPT_CONTROL_ENABLED FALSE
|
|
||||||
#define IDSOPT_TRACING_ENABLED TRUE
|
|
||||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
|
||||||
#ifdef IDS_DEBUG_PRINT_MASK
|
|
||||||
#undef IDS_DEBUG_PRINT_MASK
|
|
||||||
#endif
|
|
||||||
#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_ALL | GFX_MISC | CPU_TRACE_ALL | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
|
|
||||||
#define IDSOPT_SERIAL_PORT 0x3F8
|
|
||||||
#define IDSOPT_HEAP_CHECKING TRUE
|
|
||||||
#define IDSOPT_TRACE_BLD_CFG TRUE
|
|
||||||
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
|
|
||||||
#define IDSOPT_DEBUG_CODE_ENABLED TRUE
|
|
||||||
#define IDSOPT_C_OPTIMIZATION_DISABLED TRUE
|
|
||||||
#else
|
|
||||||
#define IDSOPT_IDS_ENABLED FALSE
|
|
||||||
//#define IDSOPT_ERROR_TRAP_ENABLED FALSE
|
|
||||||
//#define IDSOPT_CONTROL_ENABLED FALSE
|
|
||||||
#define IDSOPT_TRACING_ENABLED FALSE
|
|
||||||
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
|
|
||||||
#define IDS_DEBUG_PRINT_MASK (0)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user