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intel post-car: Consolidate choose_top_of_stack()

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Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15463
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-06-27 14:50:27 +03:00
parent 70cd54310b
commit e5c00a5d2c
8 changed files with 62 additions and 69 deletions
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16
src/cpu/intel/haswell/romstage.c
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@@ -65,20 +65,6 @@ static inline u32 *stack_push(u32 *stack, u32 value)
return stack;
}
/* Romstage needs quite a bit of stack for decompressing images since the lzma
* lib keeps its state on the stack during romstage. */
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
static unsigned long choose_top_of_stack(void)
{
unsigned long stack_top;
/* cbmem_add() does a find() before add(). */
stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
ROMSTAGE_RAM_STACK_SIZE);
stack_top += ROMSTAGE_RAM_STACK_SIZE;
return stack_top;
}
/* setup_romstage_stack_after_car() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_romstage_stack_after_car(void)
@@ -90,7 +76,7 @@ static void *setup_romstage_stack_after_car(void)
u32 top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
top_of_stack = choose_top_of_stack() & ~3;
top_of_stack = romstage_ram_stack_top() & ~3;
slot = (void *)top_of_stack;
num_mtrrs = 0;