intel post-car: Consolidate choose_top_of_stack()

Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15463
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-06-27 14:50:27 +03:00
parent 70cd54310b
commit e5c00a5d2c
8 changed files with 62 additions and 69 deletions

View File

@@ -99,10 +99,6 @@ config GOP_SUPPORT
bool "Enable GOP support"
default n
config ROMSTAGE_RAM_STACK_SIZE
hex "Size of the romstage RAM stack in bytes"
default 0x5000
config USE_GENERIC_FSP_CAR_INC
bool
default n

View File

@@ -21,23 +21,7 @@
#include <fsp/romstage.h>
#include <fsp/stack.h>
#include <stdlib.h>
const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
/*
* Romstage needs quite a bit of stack for decompressing images since the lzma
* lib keeps its state on the stack during romstage.
*/
static unsigned long choose_top_of_stack(void)
{
unsigned long stack_top;
/* cbmem_add() does a find() before add(). */
stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
romstage_ram_stack_size);
stack_top += romstage_ram_stack_size;
return stack_top;
}
#include <program_loading.h>
/*
* setup_stack_and_mtrrs() determines the stack to use after
@@ -57,7 +41,7 @@ void *setup_stack_and_mtrrs(void)
soc_display_mtrrs();
/* Top of stack needs to be aligned to a 8-byte boundary. */
top_of_stack = choose_top_of_stack();
top_of_stack = romstage_ram_stack_top();
slot = (void *)top_of_stack;
num_mtrrs = 0;
max_mtrrs = soc_get_variable_mtrr_count(NULL);
@@ -68,8 +52,7 @@ void *setup_stack_and_mtrrs(void)
*/
mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
alignment = mmap_region_granularity();
aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
alignment);
aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment);
/*
* The order for each MTRR is value then base with upper 32-bits of