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mb/system76: Use PAD_NC for unconnected pins

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- Fix indentation level
- Document pins
- Use PAD_NC

Change-Id: Ieeec4a8e56725574225b815d4d05605733d18a24
This commit is contained in:
Tim Crawford
2021-01-29 14:12:49 -07:00
committed by Jeremy Soller
parent eb025e0d6d
commit e5cb4d2fc5
6 changed files with 1529 additions and 1391 deletions
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483
src/mainboard/system76/addw1/gpio.h
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@@ -14,240 +14,263 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW# /* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_GPI(GPD7, NONE, PWROK), // NC PAD_NC(GPD6, NONE),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK PAD_NC(GPD7, NONE), // RESERVED STRAP
PAD_CFG_NF(GPD9, NONE, PWROK, NF1), // NC PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000), // NC PAD_NC(GPD9, NONE),
PAD_CFG_NF(GPD11, NONE, DEEP, NF1), // NC PAD_NC(GPD10, NONE),
PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP), // SB_KBCRST# PAD_NC(GPD11, NONE),
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1 /* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2 PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP), // SB_KBCRST#
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3 PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7 PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN# PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# PAD_NC(GPP_A10, DN_20K),
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC PAD_NC(GPP_A11, UP_20K),
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK# PAD_NC(GPP_A12, NONE),
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP), // NC PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET PAD_NC(GPP_A14, NONE),
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // NC PAD_NC(GPP_A16, DN_20K),
PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // PEX_WAKE# PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
PAD_CFG_GPI(GPP_A21, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SMARTAMP_SW PAD_NC(GPP_A19, NONE),
PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V) PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // PEX_WAKE#
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ# PAD_NC(GPP_A21, NONE),
PAD_CFG_GPI(GPP_B1, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SMARTAMP_SW
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V)
PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), // PCH_GPP_B3 (touchpad interrupt)
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // NC /* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ# PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
PAD_CFG_GPI(GPP_B6, NONE, DEEP), // NC PAD_NC(GPP_B1, NONE),
PAD_CFG_GPI(GPP_B7, NONE, DEEP), // NC PAD_NC(GPP_B2, NONE),
PAD_CFG_GPI(GPP_B8, NONE, DEEP), // NC PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), // PCH_GPP_B3 (touchpad interrupt)
PAD_CFG_GPI(GPP_B9, NONE, DEEP), // NC PAD_NC(GPP_B4, NONE),
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ# PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_GPI(GPP_B11, NONE, DEEP), // NC PAD_NC(GPP_B6, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# PAD_NC(GPP_B7, NONE),
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST# PAD_NC(GPP_B8, NONE),
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR PAD_NC(GPP_B9, NONE),
PAD_CFG_GPI(GPP_B15, NONE, DEEP), // NC PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC PAD_NC(GPP_B11, NONE),
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP _PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
PAD_CFG_GPI(GPP_B19, NONE, DEEP), // NC PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20 PAD_NC(GPP_B15, NONE),
PAD_CFG_GPI(GPP_B21, NONE, DEEP), // NC PAD_NC(GPP_B16, NONE),
PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP PAD_NC(GPP_B17, NONE),
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK PAD_NC(GPP_B19, NONE),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20
_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE# PAD_NC(GPP_B21, NONE),
PAD_CFG_GPI(GPP_C3, NONE, DEEP), // NC PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP
PAD_CFG_GPI(GPP_C4, NONE, DEEP), // NC PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC /* ------- GPIO Group GPP_C ------- */
PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_GPI(GPP_C8, NONE, DEEP), // NC PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2 _PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE#
PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1 PAD_NC(GPP_C3, NONE),
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET# PAD_NC(GPP_C4, NONE),
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET PAD_NC(GPP_C6, NONE),
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT# PAD_NC(GPP_C7, NONE),
PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down PAD_NC(GPP_C8, NONE),
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0 PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0 PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT#
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS# PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS# PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
PAD_CFG_GPI(GPP_D0, NONE, DEEP), // NC PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // NC PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
PAD_CFG_GPI(GPP_D2, NONE, DEEP), // NC PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
PAD_CFG_GPI(GPP_D3, NONE, DEEP), // NC PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // NC PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST# PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
PAD_CFG_GPI(GPP_D7, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_D8, NONE, DEEP), // NC /* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPI(GPP_D9, NONE, DEEP), // NC PAD_NC(GPP_D0, NONE),
PAD_CFG_GPI(GPP_D10, NONE, DEEP), // NC PAD_NC(GPP_D1, NONE),
PAD_CFG_GPI(GPP_D11, NONE, DEEP), // NC PAD_NC(GPP_D2, NONE),
PAD_CFG_GPI(GPP_D12, NONE, DEEP), // NC PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // NC PAD_NC(GPP_D4, NONE),
PAD_CFG_GPI(GPP_D14, NONE, DEEP), // NC PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_GPI(GPP_D15, NONE, DEEP), // NC PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
PAD_CFG_GPI(GPP_D16, NONE, DEEP), // NC PAD_NC(GPP_D7, NONE),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC PAD_NC(GPP_D8, NONE),
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC PAD_NC(GPP_D9, NONE),
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D21, NONE, DEEP), // NC PAD_NC(GPP_D12, NONE),
PAD_CFG_GPI(GPP_D22, NONE, DEEP), // NC PAD_NC(GPP_D13, NONE),
PAD_CFG_GPI(GPP_D23, NONE, DEEP), // NC PAD_NC(GPP_D14, NONE),
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC PAD_NC(GPP_D15, NONE),
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1 PAD_NC(GPP_D16, NONE),
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC PAD_NC(GPP_D17, NONE),
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // NC PAD_NC(GPP_D18, NONE),
PAD_CFG_GPI(GPP_E4, NONE, DEEP), // NC PAD_NC(GPP_D19, NONE),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1 PAD_NC(GPP_D20, NONE),
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP), // PCH_MUTE# PAD_NC(GPP_D21, NONE),
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // NC PAD_NC(GPP_D22, NONE),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED# PAD_NC(GPP_D23, NONE),
PAD_CFG_GPI(GPP_E9, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // NC /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // NC PAD_NC(GPP_E0, NONE),
PAD_CFG_GPI(GPP_E12, NONE, DEEP), // NC PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_F0, NONE, DEEP), // NC PAD_NC(GPP_E2, NONE),
PAD_CFG_GPI(GPP_F1, NONE, DEEP), // NC PAD_NC(GPP_E3, NONE),
PAD_CFG_GPI(GPP_F2, NONE, DEEP), // NC PAD_NC(GPP_E4, NONE),
PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP), // GPP_F3_LAN_RST# PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP), // GPP_F4_TBT_RST# PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP), // PCH_MUTE#
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // NC PAD_NC(GPP_E7, NONE),
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // NC PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
PAD_CFG_GPI(GPP_F7, NONE, DEEP), // NC PAD_NC(GPP_E9, NONE), // USB_OC0# (test point)
PAD_CFG_GPI(GPP_F8, NONE, DEEP), // NC PAD_NC(GPP_E10, NONE), // USB_OC1# (test point)
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW PAD_NC(GPP_E11, NONE), // USB_OC2# (test point)
PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP PAD_NC(GPP_E12, NONE), // USB_OC3# (test point)
PAD_CFG_GPI(GPP_F11, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_F12, NONE, DEEP), // NC /* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI(GPP_F13, NONE, DEEP), // NC PAD_NC(GPP_F0, NONE),
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N PAD_NC(GPP_F1, NONE),
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // NC PAD_NC(GPP_F2, NONE),
PAD_CFG_GPI(GPP_F16, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP), // GPP_F3_LAN_RST#
PAD_CFG_GPI(GPP_F17, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP), // GPP_F4_TBT_RST#
PAD_CFG_GPI(GPP_F18, NONE, DEEP), // NC PAD_NC(GPP_F5, NONE),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_NC(GPP_F6, NONE),
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON PAD_NC(GPP_F7, NONE),
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS PAD_NC(GPP_F8, NONE),
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET PAD_NC(GPP_F11, NONE),
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // NC PAD_NC(GPP_F12, NONE),
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET# PAD_NC(GPP_F13, NONE),
PAD_CFG_GPI(GPP_G3, NONE, DEEP), // NC PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
PAD_CFG_GPI(GPP_G4, NONE, DEEP), // NC PAD_NC(GPP_F15, NONE), // USB_OC4# (test point)
PAD_CFG_GPI(GPP_G5, NONE, DEEP), // NC PAD_NC(GPP_F16, NONE), // USB_OC5# (test point)
PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6 PAD_NC(GPP_F17, NONE), // USB_OC6# (test point)
PAD_CFG_GPI(GPP_G7, NONE, DEEP), // NC PAD_NC(GPP_F18, NONE), // USB_OC7# (test point)
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ# PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ# PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ# PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ# PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_GPI(GPP_H5, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST# /* ------- GPIO Group GPP_G ------- */
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST# PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST# PAD_NC(GPP_G1, NONE),
PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE# PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET#
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC PAD_NC(GPP_G3, NONE),
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC PAD_NC(GPP_G4, NONE),
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP PAD_NC(GPP_G5, NONE),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC PAD_NC(GPP_G7, NONE),
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN /* ------- GPIO Group GPP_H ------- */
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST), // TBT_FORCE_PWR PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_TERM_GPO(GPP_H18, 1, NONE, DEEP), // NC PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ#
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP), // NC PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC PAD_NC(GPP_H5, NONE),
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT# PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE#
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD PAD_NC(GPP_H10, NONE),
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD PAD_NC(GPP_H11, NONE),
PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP), // TBT_GPIO_RST# PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP
PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
PAD_CFG_GPI(GPP_I7, NONE, DEEP), // NC PAD_NC(GPP_H14, NONE),
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN _PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST), // TBT_FORCE_PWR
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // NC PAD_NC(GPP_H18, NONE),
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN PAD_NC(GPP_H19, NONE),
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC PAD_NC(GPP_H20, NONE),
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING PAD_NC(GPP_H22, NONE),
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1 _PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
PAD_CFG_GPI(GPP_J2, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_J3, NONE, DEEP), // NC /* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP), // TBT_GPIO_RST#
PAD_CFG_GPI(GPP_J10, NONE, DEEP), // NC PAD_NC(GPP_I6, NONE),
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // NC PAD_NC(GPP_I7, NONE),
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
PAD_CFG_GPI(GPP_K2, NONE, DEEP), // NC PAD_NC(GPP_I10, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3 PAD_NC(GPP_I11, NONE),
PAD_CFG_GPI(GPP_K4, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
PAD_CFG_GPI(GPP_K5, NONE, DEEP), // NC PAD_NC(GPP_I13, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6 PAD_NC(GPP_I14, NONE),
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // GPP_K8_LAN_RTD3 /* ------- GPIO Group GPP_J ------- */
PAD_CFG_GPI(GPP_K9, NONE, DEEP), // NC PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC PAD_NC(GPP_J2, NONE),
PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP), // PCH_GPP_K12 PAD_NC(GPP_J3, NONE),
PAD_CFG_GPI(GPP_K13, NONE, DEEP), // NC PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_GPI(GPP_K16, NONE, DEEP), // NC PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_GPI(GPP_K17, NONE, DEEP), // NC PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE# PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19 PAD_NC(GPP_J10, NONE),
PAD_CFG_GPI(GPP_K20, NONE, DEEP), // NC PAD_NC(GPP_J11, DN_20K),
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // NC
_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000), // NC /* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE
PAD_NC(GPP_K2, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
PAD_NC(GPP_K4, NONE),
PAD_NC(GPP_K5, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // GPP_K8_LAN_RTD3
PAD_NC(GPP_K9, NONE),
PAD_NC(GPP_K10, NONE),
PAD_NC(GPP_K11, NONE),
PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP), // PCH_GPP_K12
PAD_NC(GPP_K13, NONE),
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
PAD_NC(GPP_K16, NONE),
PAD_NC(GPP_K17, NONE),
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE#
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19
PAD_NC(GPP_K20, NONE),
PAD_NC(GPP_K21, NONE),
PAD_NC(GPP_K22, NONE),
PAD_NC(GPP_K23, NONE),
}; };
#endif #endif

483
src/mainboard/system76/addw2/gpio.h
View File

@@ -14,240 +14,263 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
PAD_CFG_GPI(GPD2, NATIVE, PWROK), PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD6, NONE, DEEP, NF1), PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_GPI(GPD7, NONE, PWROK), PAD_NC(GPD6, NONE),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_NC(GPD7, NONE), // RESERVED STRAP
PAD_CFG_NF(GPD9, NONE, PWROK, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000), PAD_NC(GPD9, NONE),
PAD_CFG_NF(GPD11, NONE, DEEP, NF1), PAD_NC(GPD10, NONE),
PAD_CFG_GPI(GPP_A0, NONE, DEEP), PAD_NC(GPD11, NONE),
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), PAD_NC(GPP_A0, NONE),
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
PAD_CFG_GPI(GPP_A7, NONE, DEEP), PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), PAD_NC(GPP_A10, DN_20K),
PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT# PAD_NC(GPP_A11, UP_20K),
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), PAD_NC(GPP_A12, NONE),
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP), PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_GPI(GPP_A17, NONE, DEEP), PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT#
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PW_ACK#
PAD_CFG_GPI(GPP_A19, NONE, DEEP), PAD_NC(GPP_A16, DN_20K),
PAD_CFG_GPI(GPP_A20, NONE, DEEP), PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000), PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), PAD_NC(GPP_A19, NONE),
PAD_CFG_GPI(GPP_A23, NONE, DEEP), PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), _PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000), // EAPD_MODE
PAD_CFG_GPI(GPP_B1, NONE, DEEP), PAD_NC(GPP_A22, NONE),
PAD_CFG_GPI(GPP_B2, NONE, DEEP), PAD_CFG_GPI(GPP_A23, NONE, DEEP), // DGPU BOARD_ID
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_B6, NONE, DEEP), PAD_NC(GPP_B1, NONE),
PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP), PAD_NC(GPP_B2, NONE),
PAD_CFG_GPI(GPP_B8, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
PAD_CFG_GPI(GPP_B9, NONE, DEEP), PAD_NC(GPP_B4, NONE),
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_GPI(GPP_B11, NONE, DEEP), PAD_NC(GPP_B6, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP), // GPP_B7_CR_RST#
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), PAD_CFG_GPI(GPP_B8, NONE, DEEP), // GPP_B8_CR_WAKE#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), PAD_NC(GPP_B9, NONE),
PAD_CFG_GPI(GPP_B15, NONE, DEEP), PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
PAD_CFG_GPI(GPP_B16, NONE, DEEP), PAD_NC(GPP_B11, NONE),
PAD_CFG_GPI(GPP_B17, NONE, DEEP), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_GPI(GPP_B18, NONE, DEEP), _PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
PAD_CFG_GPI(GPP_B19, NONE, DEEP), PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000), PAD_NC(GPP_B15, NONE),
PAD_CFG_GPI(GPP_B21, NONE, DEEP), PAD_NC(GPP_B16, NONE),
PAD_CFG_GPI(GPP_B22, NONE, DEEP), PAD_NC(GPP_B17, NONE),
PAD_CFG_GPI(GPP_B23, NONE, DEEP), PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), PAD_NC(GPP_B19, NONE),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000), // SMI#_GPP_B20
PAD_CFG_GPI(GPP_C2, NONE, DEEP), PAD_NC(GPP_B21, NONE),
PAD_CFG_GPI(GPP_C3, NONE, DEEP), PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BIOS BOOT STRAP
PAD_CFG_GPI(GPP_C4, NONE, DEEP), PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
PAD_CFG_GPI(GPP_C6, NONE, DEEP), /* ------- GPIO Group GPP_C ------- */
PAD_CFG_GPI(GPP_C7, NONE, DEEP), PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_GPI(GPP_C8, NONE, DEEP), PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C9, NONE, DEEP), PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE#
PAD_CFG_GPI(GPP_C10, NONE, DEEP), PAD_NC(GPP_C3, NONE),
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET# PAD_NC(GPP_C4, NONE),
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPI(GPP_C13, NONE, PLTRST), PAD_NC(GPP_C6, NONE),
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), PAD_NC(GPP_C7, NONE),
PAD_CFG_GPI(GPP_C15, NONE, DEEP), PAD_NC(GPP_C8, NONE),
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_C20, NONE, DEEP), PAD_CFG_GPI(GPP_C13, NONE, PLTRST), // TPM_DET
PAD_CFG_GPI(GPP_C21, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT#
PAD_CFG_GPI(GPP_C22, NONE, DEEP), PAD_CFG_GPI(GPP_C15, NONE, DEEP), // GPP_C15
PAD_CFG_GPI(GPP_C23, NONE, DEEP), PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
PAD_CFG_GPI(GPP_D0, NONE, DEEP), PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
PAD_CFG_GPI(GPP_D1, NONE, DEEP), PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
PAD_CFG_GPI(GPP_D2, NONE, DEEP), PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
PAD_CFG_GPI(GPP_D3, NONE, DEEP), PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_GPI(GPP_D4, NONE, DEEP), PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
PAD_CFG_GPI(GPP_D8, NONE, DEEP), /* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPI(GPP_D9, NONE, DEEP), PAD_NC(GPP_D0, NONE),
PAD_CFG_GPI(GPP_D10, NONE, DEEP), PAD_NC(GPP_D1, NONE),
PAD_CFG_GPI(GPP_D11, NONE, DEEP), PAD_NC(GPP_D2, NONE),
PAD_CFG_GPI(GPP_D12, NONE, DEEP), PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D13, NONE, DEEP), PAD_NC(GPP_D4, NONE),
PAD_CFG_GPI(GPP_D14, NONE, DEEP), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_GPI(GPP_D15, NONE, DEEP), PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
PAD_CFG_GPI(GPP_D16, NONE, DEEP), PAD_NC(GPP_D7, NONE),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), PAD_NC(GPP_D8, NONE),
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), PAD_NC(GPP_D9, NONE),
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D21, NONE, DEEP), PAD_NC(GPP_D12, NONE),
PAD_CFG_GPI(GPP_D22, NONE, DEEP), PAD_NC(GPP_D13, NONE),
PAD_CFG_GPI(GPP_D23, NONE, DEEP), PAD_NC(GPP_D14, NONE),
PAD_CFG_GPI(GPP_E0, NONE, DEEP), PAD_NC(GPP_D15, NONE),
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), PAD_NC(GPP_D16, NONE),
PAD_CFG_GPI(GPP_E2, NONE, DEEP), PAD_NC(GPP_D17, NONE),
PAD_CFG_GPI(GPP_E3, NONE, DEEP), PAD_NC(GPP_D18, NONE),
PAD_CFG_GPI(GPP_E4, NONE, DEEP), PAD_NC(GPP_D19, NONE),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), PAD_NC(GPP_D20, NONE),
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP), PAD_NC(GPP_D21, NONE),
PAD_CFG_GPI(GPP_E7, NONE, DEEP), PAD_NC(GPP_D22, NONE),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), PAD_NC(GPP_D23, NONE),
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
PAD_CFG_GPI(GPP_E10, NONE, DEEP), /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E11, NONE, DEEP), PAD_NC(GPP_E0, NONE),
PAD_CFG_GPI(GPP_E12, NONE, DEEP), PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_F0, NONE, DEEP), PAD_NC(GPP_E2, NONE),
PAD_CFG_GPI(GPP_F1, NONE, DEEP), PAD_NC(GPP_E3, NONE),
PAD_CFG_GPI(GPP_F2, NONE, DEEP), PAD_NC(GPP_E4, NONE),
PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP), // GPP_F3_LAN_RST# PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
PAD_CFG_GPI(GPP_F4, NONE, DEEP), // GPP_F4_TBT_RST# PAD_NC(GPP_E6, NONE),
PAD_CFG_GPI(GPP_F5, NONE, DEEP), PAD_NC(GPP_E7, NONE),
PAD_CFG_GPI(GPP_F6, NONE, DEEP), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
PAD_CFG_GPI(GPP_F7, NONE, DEEP), PAD_NC(GPP_E9, NONE), // USB_OC0# (test point)
PAD_CFG_GPI(GPP_F8, NONE, DEEP), PAD_NC(GPP_E10, NONE), // USB_OC1# (test point)
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW PAD_NC(GPP_E11, NONE), // USB_OC2# (test point)
PAD_CFG_GPI(GPP_F10, NONE, DEEP), PAD_NC(GPP_E12, NONE), // USB_OC3# (test point)
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI(GPP_F13, NONE, DEEP), PAD_NC(GPP_F0, NONE),
PAD_CFG_GPI(GPP_F14, NONE, DEEP), PAD_NC(GPP_F1, NONE),
PAD_CFG_GPI(GPP_F15, NONE, DEEP), PAD_NC(GPP_F2, NONE),
PAD_CFG_GPI(GPP_F16, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP), // GPP_F3_LAN_RST#
PAD_CFG_GPI(GPP_F17, NONE, DEEP), PAD_CFG_GPI(GPP_F4, NONE, DEEP), // GPP_F4_TBT_RST#
PAD_CFG_GPI(GPP_F18, NONE, DEEP), PAD_NC(GPP_F5, NONE),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), PAD_NC(GPP_F6, NONE),
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON PAD_NC(GPP_F7, NONE),
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), PAD_NC(GPP_F8, NONE),
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY STRAP
PAD_CFG_GPI(GPP_G0, NONE, DEEP), PAD_NC(GPP_F11, NONE),
PAD_CFG_GPI(GPP_G1, NONE, DEEP), PAD_NC(GPP_F12, NONE),
PAD_CFG_GPI(GPP_G2, NONE, DEEP), PAD_NC(GPP_F13, NONE),
PAD_CFG_GPI(GPP_G3, NONE, DEEP), PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
PAD_CFG_GPI(GPP_G4, NONE, DEEP), PAD_NC(GPP_F15, NONE), // USB_OC4# (test point)
PAD_CFG_GPI(GPP_G5, NONE, DEEP), PAD_NC(GPP_F16, NONE), // USB_OC5# (test point)
PAD_CFG_GPI(GPP_G6, NONE, DEEP), PAD_NC(GPP_F17, NONE), // USB_OC6# (test point)
PAD_CFG_GPI(GPP_G7, NONE, DEEP), PAD_NC(GPP_F18, NONE), // USB_OC7# (test point)
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CR_CLKREQ# PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ# PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ# PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ# PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST# /* ------- GPIO Group GPP_G ------- */
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST# PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
PAD_CFG_GPI(GPP_H8, NONE, DEEP), PAD_NC(GPP_G1, NONE),
_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000), PAD_CFG_GPI(GPP_G2, NONE, DEEP), // DDS_DET
PAD_CFG_GPI(GPP_H10, NONE, DEEP), PAD_NC(GPP_G3, NONE),
PAD_CFG_GPI(GPP_H11, NONE, DEEP), PAD_NC(GPP_G4, NONE),
PAD_CFG_GPI(GPP_H12, NONE, DEEP), PAD_NC(GPP_G5, NONE),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
PAD_CFG_GPI(GPP_H14, NONE, DEEP), PAD_NC(GPP_G7, NONE),
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, DEEP), // TBT_RTD3_PWR_EN_R /* ------- GPIO Group GPP_H ------- */
PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_GPI(GPP_H18, NONE, DEEP), PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CR_CLKREQ#
PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP), PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP), PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
PAD_CFG_GPI(GPP_H21, NONE, DEEP), PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_CFG_GPI(GPP_H22, NONE, DEEP), PAD_NC(GPP_H5, NONE),
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), _PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000), // GPP_H9_TBT_WAKE#
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), PAD_NC(GPP_H10, NONE),
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), PAD_NC(GPP_H11, NONE),
PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST# PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE STRAP
PAD_CFG_GPI(GPP_I6, NONE, DEEP), PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
PAD_CFG_GPI(GPP_I7, NONE, DEEP), PAD_NC(GPP_H14, NONE),
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, DEEP), // TBT_RTD3_PWR_EN_R
PAD_CFG_GPI(GPP_I10, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
PAD_CFG_GPI(GPP_I11, NONE, DEEP), PAD_NC(GPP_H18, NONE),
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP), // GPP_H19_CR_AUX33
PAD_CFG_GPI(GPP_I13, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP), // GPP_H20_CR_MV33
PAD_CFG_GPI(GPP_I14, NONE, DEEP), PAD_CFG_GPI(GPP_H21, NONE, DEEP), // 100k pull up, 10k pull down
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), PAD_NC(GPP_H22, NONE),
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), _PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
PAD_CFG_GPI(GPP_J3, NONE, DEEP), /* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // MDP_B_HPD
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // HDMI_HPD
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // MDP_E_HPD
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // PS8330B_HPD
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST#
PAD_CFG_GPI(GPP_J10, NONE, DEEP), PAD_NC(GPP_I6, NONE),
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), PAD_NC(GPP_I7, NONE),
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
PAD_CFG_GPI(GPP_K2, NONE, DEEP), PAD_NC(GPP_I10, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), PAD_NC(GPP_I11, NONE),
_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000), PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
PAD_CFG_GPI(GPP_K5, NONE, DEEP), PAD_NC(GPP_I13, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), PAD_NC(GPP_I14, NONE),
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), /* ------- GPIO Group GPP_J ------- */
PAD_CFG_GPI(GPP_K9, NONE, DEEP), PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_K10, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
PAD_CFG_GPI(GPP_K11, NONE, DEEP), PAD_NC(GPP_J2, NONE),
PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP), PAD_NC(GPP_J3, NONE),
PAD_CFG_GPI(GPP_K13, NONE, DEEP), PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_GPI(GPP_K16, NONE, DEEP), PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_GPI(GPP_K17, NONE, DEEP), PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_CFG_GPI(GPP_K19, NONE, DEEP), PAD_NC(GPP_J10, NONE),
PAD_CFG_GPI(GPP_K20, NONE, DEEP), PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // 75k pull down
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP), /* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPI(GPP_K23, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE
PAD_NC(GPP_K2, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
PAD_NC(GPP_K4, NONE),
PAD_NC(GPP_K5, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // GPP_K8_LAN_RTD3
PAD_NC(GPP_K9, NONE),
PAD_NC(GPP_K10, NONE),
PAD_NC(GPP_K11, NONE),
PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP), // GPP_K12_PLVDD_SEL
PAD_NC(GPP_K13, NONE),
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
PAD_NC(GPP_K16, NONE),
PAD_NC(GPP_K17, NONE),
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE#
PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_GPP_K19
PAD_NC(GPP_K20, NONE),
PAD_NC(GPP_K21, NONE),
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP), // DGPU_OVRM
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWR_OK
}; };
#endif #endif

486
src/mainboard/system76/bonw14/gpio.h
View File

@@ -10,242 +10,264 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
//TODO: add early GPIO settings //TODO: add early GPIO settings
PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN# PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
//TODO: GPIO names and verify everything /* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // BATLOW_N
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_GPI(GPD2, NATIVE, PWROK), PAD_CFG_GPI(GPD2, NATIVE, PWROK), // PCH_LAN_WAKE#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1), PAD_NC(GPD6, UP_20K),
PAD_CFG_GPI(GPD7, UP_20K, PWROK), PAD_CFG_GPI(GPD7, UP_20K, PWROK),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
PAD_CFG_NF(GPD9, NONE, DEEP, NF1), PAD_NC(GPD9, NONE),
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), PAD_NC(GPD10, NONE),
PAD_CFG_GPI(GPD11, UP_20K, PWROK), PAD_CFG_GPI(GPD11, UP_20K, PWROK), // LANPHYPC
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // 10k pull up
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), PAD_NC(GPP_A10, UP_20K),
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), _PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
PAD_CFG_GPI(GPP_A14, UP_20K, DEEP), PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // 10k pull up
PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUS_PWR_ACK
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), PAD_NC(GPP_A14, UP_20K),
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP), PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUSACK#
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), PAD_NC(GPP_A16, NONE),
PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), PAD_NC(GPP_A17, UP_20K),
PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), // XFI_GAIN
PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // GPP_A20 (MB det)
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), PAD_NC(GPP_A21, UP_20K),
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ# PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), // GPP_A22 (MB det)
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP), PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPP_A23 (MB det)
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), /* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), _PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ# PAD_NC(GPP_B1, UP_20K),
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ# PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // BT_UART_WAKE_N
PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R PAD_NC(GPP_B4, UP_20K),
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ# PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT# PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ#
PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP), PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT#
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP), PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP), // PCIE_GLAN_RESET
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP), PAD_NC(GPP_B15, UP_20K),
_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), PAD_NC(GPP_B16, UP_20K),
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP), PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // LPSS_GSPI0_MISO
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), PAD_NC(GPP_B19, UP_20K),
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI#_3242
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), PAD_NC(GPP_B21, UP_20K),
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // EXI BOOT STALL STRAP
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C8, NONE, PLTRST), PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // TLS CONFIDENTIALITY STRAP
PAD_CFG_GPI(GPP_C9, NONE, DEEP), PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SMLINK0_CLK
PAD_CFG_GPI(GPP_C10, DN_20K, DEEP), PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SMLINK0_DATA
PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP), PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // ESPI/LPC SELECT STRAP
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP), PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SMC_CPU_THERM_R
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP), PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SMD_CPU_THERM
PAD_CFG_GPI(GPP_C14, UP_20K, DEEP), PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET#
PAD_CFG_GPI(GPP_C15, UP_20K, DEEP), PAD_CFG_GPI(GPP_C9, NONE, DEEP), // GSYNC_ID
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), PAD_NC(GPP_C10, DN_20K),
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP), // FW_RST#
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), PAD_NC(GPP_C12, UP_20K),
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), PAD_NC(GPP_C13, UP_20K),
PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), PAD_NC(GPP_C14, UP_20K),
PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), PAD_NC(GPP_C15, UP_20K),
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP), PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // T_SDA
PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // T_SCL
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP), PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP), PAD_NC(GPP_C22, UP_20K),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), PAD_NC(GPP_C23, UP_20K),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* ------- GPIO Group GPP_D ------- */
PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), PAD_NC(GPP_D0, UP_20K),
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP), PAD_NC(GPP_D1, UP_20K),
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP), PAD_NC(GPP_D2, UP_20K),
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP), PAD_NC(GPP_D3, UP_20K),
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP), PAD_NC(GPP_D4, UP_20K),
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP), PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), // M.2_BT_PCMIN
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP), PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), // M.2_BT_PCMCLK
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), PAD_NC(GPP_D9, UP_20K),
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), PAD_NC(GPP_D10, UP_20K),
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), PAD_NC(GPP_D11, UP_20K),
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), PAD_NC(GPP_D12, UP_20K),
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP), PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 5825_I2C_DAT
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP), PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 5825_I2C_CLK
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP), PAD_NC(GPP_D15, UP_20K),
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), PAD_NC(GPP_D16, UP_20K),
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N PAD_NC(GPP_D17, UP_20K),
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL PAD_NC(GPP_D18, UP_20K),
PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI# PAD_NC(GPP_D19, UP_20K),
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), PAD_NC(GPP_D20, UP_20K),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), PAD_NC(GPP_D21, UP_20K),
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), PAD_NC(GPP_D22, UP_20K),
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN# PAD_NC(GPP_D23, UP_20K),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), // 10k pull up
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI#
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N PAD_NC(GPP_E4, UP_20K),
PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST# PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SSD1_SATA_DEVSLP
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2), PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // SSD3_SATA_DEVSLP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // RING OSCILLATOR BYPASS STRAP
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP), PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP), PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // DFX TEST MODE
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER
PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP), // SSD1_PWR_DN# /* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP), PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), // 10k pull up
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2), PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST#
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP), PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2), // 10k pull up
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP), PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), // 10k pull up
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD4_SATA_DEVSLP
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // SSD2_SATA_DEVSLP
PAD_CFG_GPI(GPP_F19, UP_20K, DEEP), PAD_NC(GPP_F7, UP_20K),
PAD_CFG_GPI(GPP_F20, UP_20K, DEEP), PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // GPU_PWR_EN#
PAD_CFG_GPI(GPP_F21, UP_20K, DEEP), PAD_NC(GPP_F9, UP_20K),
PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // GC_OFF_EN PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP), // SSD1_PWR_DN#
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
PAD_CFG_GPI(GPP_G1, UP_20K, DEEP), PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
PAD_CFG_GPI(GPP_G2, UP_20K, DEEP), PAD_NC(GPP_F14, NONE),
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), PAD_NC(GPP_F15, UP_20K),
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), PAD_NC(GPP_F16, UP_20K),
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP), PAD_NC(GPP_F17, UP_20K),
PAD_CFG_GPI(GPP_G6, UP_20K, DEEP), PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // GPIO_PCIESLOT_RST_R
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP), PAD_NC(GPP_F19, UP_20K),
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ# PAD_NC(GPP_F20, UP_20K),
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ# PAD_NC(GPP_F21, UP_20K),
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ# PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPI(GPP_H3, NONE, PLTRST), PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // GC_OFF_EN
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ#
PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N PAD_NC(GPP_G0, UP_20K),
PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP), // PCIE_SSD2_RESET PAD_NC(GPP_G1, UP_20K),
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ# PAD_NC(GPP_G2, UP_20K),
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ# PAD_NC(GPP_G3, UP_20K),
PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), PAD_NC(GPP_G4, UP_20K),
PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP), // SSD3_PWR_DN# PAD_NC(GPP_G5, UP_20K),
PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), PAD_NC(GPP_G6, UP_20K),
PAD_CFG_GPI(GPP_H13, UP_20K, DEEP), PAD_NC(GPP_G7, UP_20K),
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000), /* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPI(GPP_H16, UP_20K, DEEP), PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_GPI(GPP_H17, UP_20K, DEEP), PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ#
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP), PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), PAD_NC(GPP_H3, NONE),
PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ#
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP), PAD_NC(GPP_H5, NONE),
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP), PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N
PAD_CFG_GPI(GPP_H23, UP_20K, DEEP), PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP), // PCIE_SSD2_RESET
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ#
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ#
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), PAD_NC(GPP_H10, NONE),
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP), // SSD3_PWR_DN#
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12
PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP), // GPIO_TBT_RESET PAD_NC(GPP_H13, UP_20K),
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), PAD_NC(GPP_H14, UP_20K),
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), _PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000), // GPP_H15_TBT_WAKE#
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), PAD_NC(GPP_H16, UP_20K),
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), PAD_NC(GPP_H17, UP_20K),
PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP), PAD_NC(GPP_H18, UP_20K),
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD_AUX
PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP), PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD
PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP), PAD_NC(GPP_H21, UP_20K),
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP), PAD_NC(GPP_H22, UP_20K),
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), PAD_NC(GPP_H23, UP_20K),
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), /* ------- GPIO Group GPP_I ------- */
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP), _PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // GPPDPA_I0
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // GPPDPB_I1
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // HDMI_HPD
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), _PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // DP_F_HPD
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // 100k pull down
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP), // GPIO_TBT_RESET
PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1), PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // MXM_GPIO0
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // 10k pull up
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // GPIO_WIFI_RESET_R
PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // WLAN_EN
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP), // SSD2_PWR_DN#
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI# PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP), // PCIE_SSD3_RESET
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP), // PCIE_SSD1_RESET
PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP), // DP_MUX_SW PAD_NC(GPP_I14, UP_20K),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN /* ------- GPIO Group GPP_J ------- */
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // SSD4_PWR_DN# PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // CPI_C10_GATE_N (VCCIO_3P3_PWRGATE)
PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH PAD_NC(GPP_J2, UP_20K),
PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH PAD_NC(GPP_J3, UP_20K),
_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000), PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT_R
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP), PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT_R
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP), PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP), PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // EDP_OD_EN
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // GPP_J11
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN /* ------- GPIO Group GPP_K ------- */
PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN# PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE
PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R
PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP), // DP_MUX_SW
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // SSD4_PWR_DN#
PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET
PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH
PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH
_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT#
PAD_NC(GPP_K13, UP_20K),
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // 7411_TEST_R
PAD_NC(GPP_K15, UP_20K),
PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R
PAD_NC(GPP_K17, UP_20K),
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // PCH_MUTE#
PAD_NC(GPP_K19, UP_20K),
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // TEST_SETUP_MENU
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN
PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
}; };
#endif #endif

489
src/mainboard/system76/gaze15/gpio.h
View File

@@ -14,243 +14,266 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_C20, NONE, DEEP), // UART2_RXD PAD_CFG_GPI(GPP_C20, NONE, DEEP), // UART2_RXD
PAD_CFG_GPI(GPP_C21, NONE, DEEP), // UART2_TXD PAD_CFG_GPI(GPP_C21, NONE, DEEP), // UART2_TXD
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_TERM_GPO(DGPU_RST_N, 0, NONE, DEEP), // DGPU_RST#_PCH PAD_CFG_TERM_GPO(DGPU_RST_N, 0, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(DGPU_PWR_EN, 0, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_TERM_GPO(DGPU_PWR_EN, 0, NONE, DEEP), // DGPU_PWR_EN
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPD0, NONE, PWROK), // PM_BATLOW# /* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT PAD_CFG_GPI(GPD0, NONE, PWROK), // PM_BATLOW#
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB# PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC# PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#
PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# ==> NC (test point) PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#
PAD_CFG_GPI(GPD7, NONE, PWROK), // 100k pull up PAD_NC(GPD6, NONE, DEEP), // SLP_A# (test point)
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R PAD_CFG_GPI(GPD7, NONE, PWROK), // 100k pull up
PAD_CFG_GPI(GPD9, NONE, PWROK), // PCH_SLP_WLAN# ==> NC (test point) PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC PAD_NC(GPD9, NONE), // PCH_SLP_WLAN# (test point)
PAD_CFG_GPI(GPD11, NONE, PWROK), // LAN_DISABLE_N ==> NC (test point) PAD_NC(GPD10, NONE),
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# PAD_NC(GPD11, NONE), // LAN_DISABLE_N (test point)
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1 /* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2 PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3 PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
_PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), // INTP_OUT PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // CLK_PCI_KBC_R PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC _PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), // INTP_OUT
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WUP# PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // ISH_GP6 ==> NC PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // CLK_PCI_KBC_R
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# PAD_NC(GPP_A10, DN_20K),
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE# PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WAKEUP#
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#_R PAD_NC(GPP_A12, NONE), // ISH_GP6 (test point)
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP), // NC PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_GPI(GPP_A17, NONE, DEEP), // NC PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE#
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#_R
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // NC PAD_NC(GPP_A16, DN_20K),
PAD_CFG_GPI(GPP_A20, NONE, DEEP), // NC PAD_NC(GPP_A17, NONE),
PAD_CFG_GPI(GPP_A21, NONE, DEEP), // 3G_CONFIG2 (test point) PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SATA_PWR_EN PAD_NC(GPP_A19, NONE),
PAD_CFG_GPI(GPP_A23, NONE, DEEP), // DGPU_PWM_SELECT# (test point) PAD_NC(GPP_A20, NONE),
PAD_CFG_GPI(GPP_B0, NONE, DEEP),// TPM_PIRQ# PAD_NC(GPP_A21, NONE), // 3G_CONFIG2 (test point)
PAD_CFG_GPI(GPP_B1, NONE, DEEP), // GPP_B1 ==> NC (test point) PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SATA_PWR_EN
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // VRALERTB# ==> NC (test point) PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT# (test point)
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // BT_EN_PCH
PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), // EXTTS_SNI_DRV1 /* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPI(GPP_B5, NONE, DEEP), // NC PAD_CFG_GPI(GPP_B0, NONE, DEEP),// TPM_PIRQ#
PAD_CFG_GPI(GPP_B6, NONE, DEEP), // NC PAD_NC(GPP_B1, NONE), // GPP_B1 (test point)
PAD_CFG_GPI(GPP_B7, NONE, DEEP), // NC PAD_NC(GPP_B2, NONE), // VRALERTB# (test point)
PAD_CFG_GPI(GPP_B8, NONE, DEEP), // NC PAD_CFG_GPI(GPP_B3, NONE, DEEP), // BT_EN_PCH
PAD_CFG_GPI(GPP_B9, NONE, DEEP), // NC PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), // EXTTS_SNI_DRV1
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ# PAD_NC(GPP_B5, NONE),
PAD_CFG_GPI(GPP_B11, NONE, DEEP), // NC PAD_NC(GPP_B6, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# PAD_NC(GPP_B7, NONE),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# PAD_NC(GPP_B8, NONE),
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPKR_SMC_EXTSMI (PCH_SPKR) PAD_NC(GPP_B9, NONE),
PAD_CFG_GPI(GPP_B15, NONE, DEEP), // NC PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC PAD_NC(GPP_B11, NONE),
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // LPSS_GSPI0_MOSI (no reboot) PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_GPI(GPP_B19, NONE, DEEP), // NC PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPKR_SMC_EXTSMI (PCH_SPKR)
PAD_CFG_GPI(GPP_B20, NONE, DEEP), // NC PAD_NC(GPP_B15, NONE),
PAD_CFG_GPI(GPP_B21, NONE, DEEP), // NC PAD_NC(GPP_B16, NONE),
PAD_CFG_GPI(GPP_B22, NONE, DEEP), // LPSS_GSPI1_MOSI (boot strap) PAD_NC(GPP_B17, NONE),
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // PCH_HOT_GNSS_DISABLE PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK PAD_NC(GPP_B19, NONE),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA PAD_NC(GPP_B20, NONE),
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N PAD_NC(GPP_B21, NONE),
PAD_CFG_GPI(GPP_C3, NONE, DEEP), // SML0_CLK PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT STRAP
PAD_CFG_GPI(GPP_C4, NONE, DEEP), // SMK0_DATA PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI BSSB MODE STRAP
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // GPP_C5 ==> NC (test point)
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SMC_CPU_THERM /* ------- GPIO Group GPP_C ------- */
PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SMD_CPU_THERM PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_GPI(GPP_C8, NONE, DEEP), // NC PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // NC PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
PAD_CFG_GPI(GPP_C10, NONE, DEEP), // NC PAD_CFG_GPI(GPP_C3, NONE, DEEP), // SML0_CLK
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // NC PAD_CFG_GPI(GPP_C4, NONE, DEEP), // SMK0_DATA
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // NC PAD_NC(GPP_C5, NONE), // GPP_C5 (test point)
PAD_CFG_GPI(GPP_C13, NONE, DEEP), // NC PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SMC_CPU_THERM
PAD_CFG_GPI(GPP_C14, NONE, DEEP), // NC PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SMD_CPU_THERM
PAD_CFG_GPI(GPP_C15, NONE, DEEP), // NC PAD_NC(GPP_C8, NONE),
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP PAD_NC(GPP_C9, NONE),
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP PAD_NC(GPP_C10, NONE),
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_I2C PAD_NC(GPP_C11, NONE),
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_I2C PAD_NC(GPP_C12, NONE),
PAD_CFG_GPI(GPP_C20, NONE, DEEP), // UART2_RXD PAD_NC(GPP_C13, NONE),
PAD_CFG_GPI(GPP_C21, NONE, DEEP), // UART2_TXD PAD_NC(GPP_C14, NONE),
PAD_CFG_GPI(GPP_C22, NONE, DEEP), // NC PAD_NC(GPP_C15, NONE),
PAD_CFG_GPI(GPP_C23, NONE, DEEP), // NC PAD_CFG_NF(GPP_C16, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_GPI(GPP_D0, NONE, DEEP), // NC PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // NC PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_I2C
PAD_CFG_GPI(GPP_D2, NONE, DEEP), // NC PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_I2C
PAD_CFG_GPI(GPP_D3, NONE, DEEP), // NC PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // I2C2_SDA PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST# PAD_NC(GPP_C22, NONE),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ PAD_NC(GPP_C23, NONE),
PAD_CFG_GPI(GPP_D7, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_D8, NONE, DEEP), // NC /* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPI(GPP_D9, NONE, DEEP), // NC PAD_NC(GPP_D0, NONE),
PAD_CFG_GPI(GPP_D10, NONE, DEEP), // NC PAD_NC(GPP_D1, NONE),
PAD_CFG_GPI(GPP_D11, NONE, DEEP), // NC PAD_NC(GPP_D2, NONE),
PAD_CFG_GPI(GPP_D12, NONE, DEEP), // NC PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // NC PAD_CFG_GPI(GPP_D4, NONE, DEEP), // I2C2_SDA
PAD_CFG_GPI(GPP_D14, NONE, DEEP), // NC PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_GPI(GPP_D15, NONE, DEEP), // NC PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_CFG_GPI(GPP_D16, NONE, DEEP), // NC PAD_(GPP_D7, NONE),
PAD_CFG_GPI(GPP_D17, NONE, DEEP), // 100k pull down PAD_(GPP_D8, NONE),
PAD_CFG_GPI(GPP_D18, NONE, DEEP), // NC PAD_NC(GPP_D9, NONE),
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // MIC_CLK_PCH_R PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // MIC_DATA_PCH_R PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D21, NONE, DEEP), // NC PAD_NC(GPP_D12, NONE),
PAD_CFG_GPI(GPP_D22, NONE, DEEP), // NC PAD_NC(GPP_D13, NONE),
PAD_CFG_GPI(GPP_D23, NONE, DEEP), // I2C2_SCL PAD_NC(GPP_D14, NONE),
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // SATAGP0 (test point) PAD_NC(GPP_D15, NONE),
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1 PAD_NC(GPP_D16, NONE),
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SATAGP2 PAD_CFG_GPI(GPP_D17, NONE, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // EXTTS_SNI_DRV0 PAD_NC(GPP_D18, NONE),
PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0 PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // MIC_CLK_PCH_R
PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1 PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // MIC_DATA_PCH_R
PAD_CFG_GPI(GPP_E6, NONE, DEEP), // PCH_MUTE# (test point) PAD_NC(GPP_D21, NONE),
PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# PAD_NC(GPP_D22, NONE),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# PAD_CFG_GPI(GPP_D23, NONE, DEEP), // I2C2_SCL
PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# PAD_NC(GPP_E0, NONE), // SATAGP0 (test point)
PAD_CFG_GPI(GPP_E12, NONE, DEEP), // VISACH2_D3 PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_F0, NONE, DEEP), // SATAGP3 PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SATAGP2
PAD_CFG_GPI(GPP_F1, NONE, DEEP), // NC PAD_CFG_GPI(GPP_E3, NONE, DEEP), // EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_F2, NONE, DEEP), // ODD_DA#_R (test point) PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_F3, NONE, DEEP), // (test point) PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1
PAD_CFG_GPI(GPP_F4, NONE, DEEP), // NC PAD_NC(GPP_E6, NONE), // PCH_MUTE# (test point)
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // DEVSLP4 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_CFG_GPI(GPP_F7, NONE, DEEP), // LIGHT_KB_DET# PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GPP_F8 PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
PAD_CFG_GPI(GPP_F9, NONE, DEEP), // GPP_F9 PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC PAD_CFG_GPI(GPP_E12, NONE, DEEP), // VISACH2_D3
PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
PAD_CFG_GPI(GPP_F12, NONE, DEEP), // MFG_MODE /* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT PAD_CFG_GPI(GPP_F0, NONE, DEEP), // SATAGP3
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // 10k pull up to H_SKTOCC_N PAD_NC(GPP_F1, NONE),
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // USB_OC4# PAD_NC(GPP_F2, NONE), // ODD_DA#_R (test point)
PAD_CFG_GPI(GPP_F16, NONE, DEEP), // USB_OC5# PAD_NC(GPP_F3, NONE), // (test point)
PAD_CFG_GPI(GPP_F17, NONE, DEEP), // USB_OC6# PAD_NC(GPP_F4, NONE),
PAD_CFG_GPI(GPP_F18, NONE, DEEP), // USB_OC7# PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_GPI(GPP_F6, NONE, DEEP), // DEVSLP4
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON PAD_CFG_GPI(GPP_F7, NONE, DEEP), // LIGHT_KB_DET#
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GPP_F8
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH PAD_CFG_GPI(GPP_F9, NONE, DEEP), // GPP_F9
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY STRAP
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // BOARD_ID1 PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2 PAD_CFG_GPI(GPP_F12, NONE, DEEP), // MFG_MODE
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT
PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPIO4_1V8_MAIN_EN_R PAD_CFG_GPI(GPP_F14, NONE, DEEP), // 10k pull up to H_SKTOCC_N
PAD_CFG_GPI(GPP_G4, NONE, DEEP), // SMI#_R PAD_CFG_GPI(GPP_F15, NONE, DEEP), // USB_OC4#
PAD_CFG_GPI(GPP_G5, NONE, DEEP), // NC PAD_CFG_GPI(GPP_F16, NONE, DEEP), // USB_OC5#
PAD_CFG_GPI(GPP_G6, NONE, DEEP), // NC PAD_CFG_GPI(GPP_F17, NONE, DEEP), // USB_OC6#
PAD_CFG_GPI(GPP_G7, NONE, DEEP), // NC PAD_CFG_GPI(GPP_F18, NONE, DEEP), // USB_OC7#
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_GPI(GPP_H1, NONE, DEEP), // NC PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ# PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // NC PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ# PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_CFG_GPI(GPP_H6, NONE, DEEP), // NC /* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_H7, NONE, DEEP), // NC PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_H8, NONE, DEEP), // NC PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_H9, NONE, DEEP), // NC PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // SML2CLK (test point) PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPIO4_1V8_MAIN_EN_R
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // SML2DATA (test point) PAD_CFG_GPI(GPP_G4, NONE, DEEP), // SMI#_R
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 PAD_NC(GPP_G5, NONE),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK PAD_NC(GPP_G6, NONE),
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // SML3DATA (test point) PAD_NC(GPP_G7, NONE),
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // SML3ALERT#
PAD_CFG_GPI(GPP_H16, NONE, DEEP), // SML4CLK (test point) /* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPI(GPP_H17, NONE, DEEP), // SML4DATA (test point) PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_GPI(GPP_H18, NONE, DEEP), // SML4ALERT# (test point) PAD_NC(GPP_H1, NONE),
PAD_CFG_GPI(GPP_H19, NONE, DEEP), // NC PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC PAD_NC(GPP_H3, NONE),
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // NC PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT# PAD_NC(GPP_H6, NONE),
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // I_MDP_HPD (on 1660 Ti), NC (on 1650/1650 Ti) PAD_NC(GPP_H7, NONE),
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD PAD_NC(GPP_H8, NONE),
PAD_CFG_GPI(GPP_I2, NONE, DEEP), // 1k pull to MDP_E_HPD PAD_NC(GPP_H9, NONE),
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // 1k pull to MDP_E_HPD PAD_NC(GPP_H10, NONE), // SML2CLK (test point)
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD PAD_NC(GPP_H11, NONE), // SML2DATA (test point)
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // I_MDP_CLK (on 1660 Ti), NC (on 1650/1650 Ti) PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE STRAP
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // I_MDP_DATA (on 1660 Ti), NC (on 1650/1650 Ti) PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK (on 1650/1650 Ti), test point (on 1660 Ti) PAD_NC(GPP_H14, NONE), // SML3DATA (test point)
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA (on 1650/1650 Ti), test point (on 1660 Ti) PAD_CFG_GPI(GPP_H15, NONE, DEEP), // SML3ALERT#
PAD_CFG_GPI(GPP_I9, NONE, DEEP), // NC PAD_NC(GPP_H16, NONE), // SML4CLK (test point)
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC PAD_NC(GPP_H17, NONE), // SML4DATA (test point)
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // 10k pull up to H_SKTOCC_N PAD_NC(GPP_H18, NONE), // SML4ALERT# (test point)
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // NC PAD_NC(GPP_H19, NONE),
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC PAD_NC(GPP_H20, NONE),
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC PAD_NC(GPP_H21, NONE),
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING PAD_NC(GPP_H22, NONE),
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // GPP_J1 PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT#
PAD_CFG_GPI(GPP_J2, NONE, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_J3, NONE, DEEP), // 100k pull down /* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // I_MDP_HPD (on 1660 Ti), NC (on 1650/1650 Ti)
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT PAD_CFG_GPI(GPP_I2, NONE, DEEP), // 1k pull to MDP_E_HPD
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // 1k pull to MDP_E_HPD
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // I_MDP_CLK (on 1660 Ti), NC (on 1650/1650 Ti)
PAD_CFG_GPI(GPP_J10, NONE, DEEP), // NC PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // I_MDP_DATA (on 1660 Ti), NC (on 1650/1650 Ti)
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // 75k pull down PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK (on 1650/1650 Ti), test point (on 1660 Ti)
PAD_CFG_GPI(GPP_K0, NONE, DEEP), // PCH_GPPK0_PCH_PEXVDD_EN ==> NC (test point) PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA (on 1650/1650 Ti), test point (on 1660 Ti)
PAD_CFG_GPI(GPP_K1, NONE, DEEP), // PCH_GPPK1_PCH_FBVDDQ_EN ==> NC (test point) PAD_NC(GPP_I9, NONE),
PAD_CFG_GPI(GPP_K2, NONE, DEEP), // PCH_GPPK2_PCH_1V8RUN_EN ==> NC (test point) PAD_NC(GPP_I10, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000), // SCI#_R PAD_CFG_GPI(GPP_I11, NONE, DEEP), // 10k pull up to H_SKTOCC_N
PAD_CFG_GPI(GPP_K4, NONE, DEEP), // NC PAD_NC(GPP_I12, NONE),
PAD_CFG_GPI(GPP_K5, NONE, DEEP), // NC PAD_NC(GPP_I13, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_R PAD_NC(GPP_I14, NONE),
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1 /* ------- GPIO Group GPP_J ------- */
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2 PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_K10, NONE, DEEP), // PCH_GPPK10_PCH_NVVDD_EN ==> NC (test point) PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // GPP_J1
PAD_CFG_GPI(GPP_K11, NONE, DEEP), // PCH_GPPK11_PCH_NVVDD_EN ==> NC (test point) PAD_CFG_GPI(GPP_J2, NONE, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_K12, NONE, DEEP), // (test point) PAD_CFG_GPI(GPP_J3, NONE, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_K13, NONE, DEEP), // NC PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_GPI(GPP_K15, NONE, DEEP), // NC PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_GPI(GPP_K16, NONE, DEEP), // (test point) PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_GPI(GPP_K17, NONE, DEEP), // NC PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_GPI(GPP_K18, NONE, DEEP), // NC PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR PAD_NC(GPP_J10, NONE),
PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP), // GPU_EVENT# PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // 75k pull down
PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R /* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT# PAD_NC(GPP_K0, NONE), // PCH_GPPK0_PCH_PEXVDD_EN (test point)
PAD_NC(GPP_K1, NONE), // PCH_GPPK1_PCH_FBVDDQ_EN (test point)
PAD_NC(GPP_K2, NONE), // PCH_GPPK2_PCH_1V8RUN_EN (test point)
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000), // SCI#_R
PAD_NC(GPP_K4, NONE),
PAD_NC(GPP_K5, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_R
PAD_NC(GPP_K7, NONE),
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2
PAD_NC(GPP_K10, NONE), // PCH_GPPK10_PCH_NVVDD_EN (test point)
PAD_NC(GPP_K11, NONE), // PCH_GPPK11_PCH_NVVDD_EN (test point)
PAD_NC(GPP_K12, NONE), // (test point)
PAD_NC(GPP_K13, NONE),
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
PAD_NC(GPP_K15, NONE),
PAD_NC(GPP_K16, NONE), // (test point)
PAD_NC(GPP_K17, NONE),
PAD_NC(GPP_K18, NONE),
PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR
PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP), // GPU_EVENT#
PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT#
}; };
#endif #endif

483
src/mainboard/system76/oryp5/gpio.h
View File

@@ -14,240 +14,263 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW# /* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1), // NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_GPI(GPD7, UP_20K, PWROK), // GPD_7 PAD_NC(GPD6, UP_20K),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK PAD_CFG_GPI(GPD7, UP_20K, PWROK), // GPD_7
PAD_CFG_GPI(GPD9, UP_20K, PWROK), // NC PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK
PAD_CFG_NF(GPD10, UP_20K, PWROK, NF1), // NC PAD_NC(GPD9, UP_20K),
PAD_CFG_TERM_GPO(GPD11, 1, NONE, DEEP), // LAN_DISABLE# PAD_NC(GPD10, UP_20K),
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# PAD_CFG_TERM_GPO(GPD11, 1, NONE, DEEP), // LAN_DISABLE#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 /* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA# PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // NC PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA#
PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, PLTRST), // INTP_OUT PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUSWARN# PAD_NC(GPP_A10, UP_20K),
PAD_CFG_GPI(GPP_A14, UP_20K, DEEP), // NC (test point) PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, PLTRST), // INTP_OUT
PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUS_PWR_ACK# PAD_NC(GPP_A12, UP_20K),
PAD_CFG_GPI(GPP_A16, UP_20K, DEEP), // NC PAD_NC(GPP_A13, UP_20K), // SUSWARN# (test point)
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP), // NC PAD_NC(GPP_A14, UP_20K),
PAD_CFG_GPI(GPP_A18, UP_20K, DEEP), // NC PAD_NC(GPP_A15, UP_20K), // SUS_PWR_ACK# (test point)
PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON PAD_NC(GPP_A16, UP_20K),
PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE# PAD_NC(GPP_A17, UP_20K),
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), // NC PAD_NC(GPP_A18, UP_20K),
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1 PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON
PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
PAD_CFG_GPI(GPP_B0, UP_20K, DEEP), // TPM_PIRQ# PAD_NC(GPP_A21, UP_20K),
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_RF_KILL_R_N
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WIFI_RF_KILL_R_N /* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPI(GPP_B5, UP_20K, PLTRST), // NC PAD_CFG_GPI(GPP_B0, UP_20K, DEEP), // TPM_PIRQ#
PAD_CFG_GPI(GPP_B6, UP_20K, PLTRST), // NC PAD_NC(GPP_B1, UP_20K),
PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST# PAD_NC(GPP_B2, UP_20K),
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE# PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_RF_KILL_R_N
PAD_CFG_GPI(GPP_B9, UP_20K, PLTRST), // NC PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WIFI_RF_KILL_R_N
PAD_CFG_TERM_GPO(GPP_B10, 0, NONE, PLTRST), // NC PAD_NC(GPP_B5, UP_20K),
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // NC PAD_NC(GPP_B6, UP_20K),
PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0# PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR PAD_NC(GPP_B9, UP_20K),
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP), // NC PAD_NC(GPP_B10, UP_20K),
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP), // NC PAD_NC(GPP_B11, UP_20K),
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0#
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_CFG_GPI_SMI(GPP_B20, NONE, DEEP, EDGE_SINGLE, NONE), // SMI# PAD_NC(GPP_B15, UP_20K),
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP), // NC PAD_NC(GPP_B16, UP_20K),
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI PAD_NC(GPP_B17, UP_20K),
PAD_CFG_GPI_SCI_LOW(GPP_B23, UP_20K, PLTRST, LEVEL), // SCI# PAD_NC(GPP_B18, UP_20K), // LPSS_GSPI0_MOSI (test point)
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK PAD_NC(GPP_B19, UP_20K),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA PAD_CFG_GPI_SMI(GPP_B20, NONE, DEEP, EDGE_SINGLE, NONE), // SMI#
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // GPP_C2_BT_UART_WAKE_N PAD_NC(GPP_B21, UP_20K),
PAD_CFG_GPI(GPP_C3, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI
PAD_CFG_GPI(GPP_C4, UP_20K, DEEP), // NC PAD_CFG_GPI_SCI_LOW(GPP_B23, UP_20K, PLTRST, LEVEL), // SCI#
PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // M.2_WLAN_WIFI_WAKE_N
PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM /* ------- GPIO Group GPP_C ------- */
PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C9, DN_20K, DEEP), // BOARD_ID1 PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // GPP_C2_BT_UART_WAKE_N
PAD_CFG_GPI(GPP_C10, DN_20K, DEEP), // BOARD_ID2 PAD_NC(GPP_C3, UP_20K),
PAD_CFG_GPI(GPP_C11, DN_20K, DEEP), // BOARD_ID3 PAD_NC(GPP_C4, UP_20K),
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // M.2_WLAN_WIFI_WAKE_N
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, DEEP), // GPU_EVENT# PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL1# PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL2# PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP PAD_CFG_GPI(GPP_C9, DN_20K, DEEP), // BOARD_ID1
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP PAD_CFG_GPI(GPP_C10, DN_20K, DEEP), // BOARD_ID2
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411_I2C PAD_CFG_GPI(GPP_C11, DN_20K, DEEP), // BOARD_ID3
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411_I2C PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD ==> NC (test point) PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, DEEP), // GPU_EVENT#
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD ==> NC (test point) PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL1#
PAD_CFG_NF(GPP_C22, UP_20K, DEEP, NF1), // UART2_RTS# (test point), LAN_PLT_RST# PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL2#
PAD_CFG_NF(GPP_C23, UP_20K, DEEP, NF1), // BOARD_ID4 PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411_I2C
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411_I2C
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD ==> NC (test point)
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD ==> NC (test point)
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N PAD_CFG_NF(GPP_C22, UP_20K, DEEP, NF1), // UART2_RTS# (test point), LAN_PLT_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0 PAD_CFG_NF(GPP_C23, UP_20K, DEEP, NF1), // BOARD_ID4
PAD_CFG_GPI(GPP_D7, UP_20K, DEEP), // M.2_BT_PCMIN
PAD_CFG_GPI(GPP_D8, UP_20K, DEEP), // M.2_BT_PCMCLK /* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP), // NC PAD_NC(GPP_D0, UP_20K),
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP), // NC PAD_NC(GPP_D1, UP_20K),
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP), // NC PAD_NC(GPP_D2, UP_20K),
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP), // NC PAD_NC(GPP_D3, UP_20K),
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 10k pull up PAD_NC(GPP_D4, UP_20K),
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 10k pull up PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_D7, UP_20K, DEEP), // M.2_BT_PCMIN
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), // NC PAD_CFG_GPI(GPP_D8, UP_20K, DEEP), // M.2_BT_PCMCLK
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D9, UP_20K),
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D10, UP_20K),
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D11, UP_20K),
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP), // NC PAD_NC(GPP_D12, UP_20K),
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP), // NC PAD_NC(GPP_D13, NONE), // 10k pull up
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP), // NC PAD_NC(GPP_D14, NONE), // 10k pull up
PAD_CFG_GPI(GPP_E0, UP_20K, DEEP), // NC PAD_NC(GPP_D15, UP_20K),
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET PAD_NC(GPP_D16, UP_20K),
PAD_CFG_GPI(GPP_E2, UP_20K, DEEP), // NC PAD_NC(GPP_D17, UP_20K),
PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // NC PAD_NC(GPP_D18, UP_20K),
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // NC PAD_NC(GPP_D19, UP_20K),
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // M2_P0_SATA_DEVSLP PAD_NC(GPP_D20, UP_20K),
PAD_CFG_GPI(GPP_E6, UP_20K, DEEP), // NC PAD_NC(GPP_D21, UP_20K),
PAD_CFG_GPI_APIC_EDGE_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# PAD_NC(GPP_D22, UP_20K),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# PAD_NC(GPP_D23, UP_20K),
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // USB_OC0# ==> NC (test point)
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // USB_OC1# ==> NC (test point) /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // USB_OC2# ==> NC (test point) PAD_NC(GPP_E0, UP_20K),
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // USB_OC3# ==> NC (test point) PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET
PAD_CFG_GPI(GPP_F0, UP_20K, DEEP), // NC PAD_NC(GPP_E2, UP_20K),
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_PEDET PAD_NC(GPP_E3, UP_20K),
PAD_CFG_GPI(GPP_F2, UP_20K, DEEP), // NC PAD_NC(GPP_E4, UP_20K),
PAD_CFG_GPI(GPP_F3, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // M2_P0_SATA_DEVSLP
PAD_CFG_GPI(GPP_F4, UP_20K, DEEP), // NC PAD_NC(GPP_E6, UP_20K),
PAD_CFG_GPI(GPP_F5, UP_20K, DEEP), // NC PAD_CFG_GPI_APIC_EDGE_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP), // NC PAD_NC(GPP_E9, UP_20K), // USB_OC0# (test point)
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // NC PAD_NC(GPP_E10, UP_20K), // USB_OC1# (test point)
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP), // NC PAD_NC(GPP_E11, UP_20K), // USB_OC2# (test point)
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC PAD_NC(GPP_E12, UP_20K), // USB_OC3# (test point)
PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // GPP_F11
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP), // NC /* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT PAD_NC(GPP_F0, UP_20K),
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull up to H_SKTOCC_N PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_PEDET
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP), // USB_OC4# ==> NC (test point) PAD_NC(GPP_F2, UP_20K),
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP), // NC PAD_NC(GPP_F3, UP_20K),
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), // NC PAD_NC(GPP_F4, UP_20K),
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // USB_OC7# ==> NC (test point) PAD_NC(GPP_F5, UP_20K),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON PAD_NC(GPP_F7, UP_20K),
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS PAD_NC(GPP_F8, UP_20K),
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH PAD_NC(GPP_F9, UP_20K),
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // GPP_F11
PAD_NC(GPP_G1, NONE), // CNVI_WIGIG_DET# PAD_NC(GPP_F12, UP_20K),
PAD_CFG_GPI(GPP_G2, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull up to H_SKTOCC_N
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), // NC PAD_NC(GPP_F15, UP_20K), // USB_OC4# (test point)
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP), // NC PAD_NC(GPP_F16, UP_20K),
PAD_CFG_GPI_SCI_LOW(GPP_G6, NONE, DEEP, LEVEL), // SWI# PAD_NC(GPP_F17, UP_20K),
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP), // NC PAD_NC(GPP_F18, UP_20K), // USB_OC7# (test point)
PAD_CFG_TERM_GPO(GPP_H0, 0, NONE, PLTRST), // NC PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_TERM_GPO(GPP_H1, 0, NONE, PLTRST), // NC PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ9_PEG# PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_H3, 0, NONE, PLTRST), // NC PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_H4, 0, NONE, PLTRST), // NC PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ12_SSD2#
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ13_SSD1# /* ------- GPIO Group GPP_G ------- */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GPP_H_0_SRCCLKREQB_14 PAD_NC(GPP_G0, UP_20K),
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CLK_REQ15_LAN# PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), // CNVI_WIGIG_DET#
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CLK_REQ16_CARD# PAD_NC(GPP_G2, UP_20K),
PAD_CFG_GPI(GPP_H10, UP_20K, DEEP), // NC PAD_NC(GPP_G3, UP_20K),
PAD_CFG_GPI(GPP_H11, UP_20K, DEEP), // NC PAD_NC(GPP_G4, UP_20K),
PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12 (test point) PAD_NC(GPP_G5, UP_20K),
PAD_CFG_GPI(GPP_H13, UP_20K, DEEP), // NC PAD_CFG_GPI_SCI_LOW(GPP_G6, NONE, DEEP, LEVEL), // SWI#
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP), // NC PAD_NC(GPP_G7, UP_20K),
PAD_CFG_GPI(GPP_H15, UP_20K, DEEP), // GPP_H15
PAD_CFG_GPI(GPP_H16, UP_20K, DEEP), // NC /* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPI(GPP_H17, UP_20K, DEEP), // NC PAD_NC(GPP_H0, UP_20K),
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP), // NC PAD_NC(GPP_H1, UP_20K),
PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD1 PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ9_PEG#
PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD PAD_NC(GPP_H3, UP_20K),
PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), // 4.7k pull up, 20k pull down PAD_NC(GPP_H4, UP_20K),
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ12_SSD2#
PAD_CFG_GPI(GPP_H23, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ13_SSD1#
PAD_CFG_GPI_SCI_LOW(GPP_I0, NONE, DEEP, EDGE_BOTH), // G_DP_DHPD_A PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GPP_H_0_SRCCLKREQB_14
PAD_CFG_GPI_SCI_LOW(GPP_I1, NONE, DEEP, EDGE_BOTH), // HDMI_HPD PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CLK_REQ15_LAN#
PAD_CFG_GPI_SCI_LOW(GPP_I2, NONE, DEEP, EDGE_BOTH), // G_DP_DHPD_E PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CLK_REQ16_CARD#
PAD_CFG_GPI(GPP_I3, UP_20K, DEEP), // NC PAD_NC(GPP_H10, UP_20K),
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HDP PAD_NC(GPP_H11, UP_20K),
PAD_CFG_GPI(GPP_I5, UP_20K, DEEP), // NC PAD_NC(GPP_H12, UP_20K), // GPP_H_12 (test point)
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // NC PAD_NC(GPP_H13, UP_20K),
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // NC PAD_NC(GPP_H14, UP_20K),
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // NC PAD_NC(GPP_H15, NONE), // GPP_H15 (reserved)
PAD_CFG_GPI(GPP_I9, UP_20K, DEEP), // NC PAD_NC(GPP_H16, UP_20K),
PAD_CFG_GPI(GPP_I10, UP_20K, DEEP), // NC PAD_NC(GPP_H17, UP_20K),
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N PAD_NC(GPP_H18, UP_20K),
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD1
PAD_CFG_GPI(GPP_I13, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), // 4.7k pull up, 20k pull down
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING PAD_NC(GPP_H22, UP_20K),
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1 PAD_NC(GPP_H23, UP_20K),
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), // NC
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP), // NC /* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_VRI_DT_BT_UART0_RTS PAD_CFG_GPI_SCI_LOW(GPP_I0, NONE, DEEP, EDGE_BOTH), // G_DP_DHPD_A
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP PAD_CFG_GPI_SCI_LOW(GPP_I1, NONE, DEEP, EDGE_BOTH), // HDMI_HPD
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX PAD_CFG_GPI_SCI_LOW(GPP_I2, NONE, DEEP, EDGE_BOTH), // G_DP_DHPD_E
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP PAD_NC(GPP_I3, UP_20K),
PAD_CFG_GPI(GPP_J8, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HDP
PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // CNVI_MFUART2_TXD PAD_NC(GPP_I5, UP_20K),
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // NC PAD_NC(GPP_I6, UP_20K),
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // NC PAD_NC(GPP_I7, UP_20K),
PAD_NC(GPP_K0, NONE), // NC PAD_NC(GPP_I8, UP_20K),
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // NC PAD_NC(GPP_I9, UP_20K),
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // NC PAD_NC(GPP_I10, UP_20K),
PAD_CFG_GPI(GPP_K3, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
PAD_CFG_GPI(GPP_K5, UP_20K, DEEP), // NC PAD_NC(GPP_I13, UP_20K),
PAD_CFG_GPI(GPP_K6, UP_20K, DEEP), // NC PAD_NC(GPP_I14, UP_20K),
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1 /* ------- GPIO Group GPP_J ------- */
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2 PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // NC PAD_NC(GPP_J2, UP_20K),
PAD_CFG_GPI(GPP_K12, UP_20K, DEEP), // NC PAD_NC(GPP_J3, UP_20K),
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_VRI_DT_BT_UART0_RTS
PAD_CFG_TERM_GPO(GPP_K14, 0, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point), 7411_TEST_R PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX
PAD_CFG_GPI(GPP_K16, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP), // NC PAD_NC(GPP_J8, UP_20K),
PAD_CFG_GPI(GPP_K18, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // CNVI_MFUART2_TXD
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), // NC PAD_NC(GPP_J10, UP_20K),
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // NC PAD_NC(GPP_J11, UP_20K),
PAD_CFG_GPI(GPP_K21, UP_20K, DEEP), // NC
PAD_CFG_GPI(GPP_K22, UP_20K, DEEP), // NC /* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPI(GPP_K23, UP_20K, DEEP), // NC PAD_NC(GPP_K0, UP_20K),
PAD_NC(GPP_K1, UP_20K),
PAD_NC(GPP_K2, UP_20K),
PAD_NC(GPP_K3, UP_20K),
PAD_NC(GPP_K4, UP_20K),
PAD_NC(GPP_K5, UP_20K),
PAD_NC(GPP_K6, UP_20K),
PAD_NC(GPP_K7, UP_20K),
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2
PAD_NC(GPP_K10, UP_20K),
PAD_NC(GPP_K11, UP_20K),
PAD_NC(GPP_K12, UP_20K),
PAD_NC(GPP_K13, UP_20K),
PAD_CFG_TERM_GPO(GPP_K14, 0, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point), 7411_TEST_R
PAD_NC(GPP_K15, UP_20K),
PAD_NC(GPP_K16, UP_20K),
PAD_NC(GPP_K17, UP_20K),
PAD_NC(GPP_K18, UP_20K),
PAD_NC(GPP_K19, UP_20K),
PAD_NC(GPP_K20, UP_20K),
PAD_NC(GPP_K21, UP_20K),
PAD_NC(GPP_K22, UP_20K),
PAD_NC(GPP_K23, UP_20K),
}; };
#endif #endif

496
src/mainboard/system76/oryp6/gpio.h
View File

@@ -14,246 +14,270 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1# PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2# PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_TERM_GPO(GPP_F0, 1, NONE, RSMRST), // TBT_PERST_N PAD_CFG_TERM_GPO(GPP_F0, 1, NONE, RSMRST), // TBT_PERST_N
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1 PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2 PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3 PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW# /* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1), // NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_GPI(GPD7, UP_20K, PWROK), // GPD_7 (crystal input, low = single ended, high = differential) PAD_NC(GPD6, UP_20K),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK PAD_CFG_GPI(GPD7, UP_20K, PWROK), // GPD_7 (crystal input, low = single ended, high = differential)
PAD_CFG_GPI(GPD9, UP_20K, PWROK), // NC PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5# PAD_NC(GPD9, UP_20K),
PAD_CFG_GPI(GPD11, UP_20K, PWROK), // NC PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5#
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# PAD_NC(GPD11, UP_20K),
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 /* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA# PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // NC PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA#
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WAKEUP# PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# (test point) PAD_NC(GPP_A10, UP_20K),
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WAKEUP#
PAD_CFG_GPI(GPP_A15, NONE, DEEP), // SUS_PWR_ACK# (test point) PAD_NC(GPP_A12, UP_20K),
PAD_CFG_GPI(GPP_A16, UP_20K, DEEP), // NC PAD_NC(GPP_A13, NONE), // SUSWARN# (test point)
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP), // NC PAD_NC(GPP_A14, NONE),
PAD_CFG_GPI(GPP_A18, UP_20K, DEEP), // NC PAD_NC(GPP_A15, NONE), // SUS_PWR_ACK# (test point)
PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON PAD_NC(GPP_A16, UP_20K),
PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE# PAD_NC(GPP_A17, UP_20K),
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), // EAPD_MODE PAD_NC(GPP_A18, UP_20K),
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1 PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON
PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ# PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), // EAPD_MODE
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WLAN_EN /* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ# _PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_B6, UP_20K, DEEP), // NC PAD_NC(GPP_B1, UP_20K),
PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST# PAD_NC(GPP_B2, UP_20K),
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE# PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
PAD_CFG_GPI(GPP_B9, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WLAN_EN
PAD_CFG_GPI(GPP_B10, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // NC PAD_NC(GPP_B6, UP_20K),
PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0# PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR PAD_NC(GPP_B9, UP_20K),
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP), // NC PAD_NC(GPP_B10, UP_20K),
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP), // NC PAD_NC(GPP_B11, UP_20K),
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0#
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI_MOSI (test point) PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_CFG_GPI(GPP_B20, UP_20K, DEEP), // NC PAD_NC(GPP_B15, UP_20K),
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP), // NC PAD_NC(GPP_B16, UP_20K),
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI (boot strap) PAD_NC(GPP_B17, UP_20K),
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE (boot strap) PAD_NC(GPP_B18, UP_20K), // LPSS_GSPI0_MOSI (test point)
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK PAD_NC(GPP_B19, UP_20K),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA PAD_NC(GPP_B20, UP_20K),
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // CNVI_WAKE# PAD_NC(GPP_B21, UP_20K),
PAD_CFG_GPI(GPP_C3, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI (boot strap)
PAD_CFG_GPI(GPP_C4, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE (boot strap)
PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM /* ------- GPIO Group GPP_C ------- */
PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // CNVI_DET# PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // CNVI_WAKE#
PAD_CFG_GPI(GPP_C10, UP_20K, DEEP), // NC PAD_NC(GPP_C3, UP_20K),
PAD_CFG_GPI(GPP_C11, UP_20K, DEEP), // NC PAD_NC(GPP_C4, UP_20K),
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1# PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2# PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP PAD_CFG_GPI(GPP_C9, NONE, DEEP), // CNVI_DET#
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP PAD_NC(GPP_C10, UP_20K),
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone PAD_NC(GPP_C11, UP_20K),
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C_SCL_Pantone PAD_NC(GPP_C12, UP_20K),
PAD_CFG_GPI(GPP_C20, UP_20K, DEEP), // CNVI_MFUART2_RXD PAD_NC(GPP_C13, UP_20K),
PAD_CFG_GPI(GPP_C21, UP_20K, DEEP), // CNVI_MFUART2_TXD PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP), // LAN_PLT_RST# PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C_SCL_Pantone
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C20, UP_20K, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C21, UP_20K, DEEP), // CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST# PAD_CFG_GPI(GPP_C22, UP_20K, DEEP), // LAN_PLT_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ PAD_NC(GPP_C23, UP_20K),
PAD_CFG_GPI(GPP_D7, UP_20K, DEEP), // M.2_BT_PCMIN (test point)
PAD_CFG_GPI(GPP_D8, UP_20K, DEEP), // M.2_BT_PCMCLK (test point) /* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP), // NC PAD_NC(GPP_D0, UP_20K),
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP), // NC PAD_NC(GPP_D1, UP_20K),
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP), // NC PAD_NC(GPP_D2, UP_20K),
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP), // NC PAD_NC(GPP_D3, UP_20K),
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // NC PAD_NC(GPP_D4, UP_20K),
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP), // NC PAD_NC(GPP_D7, UP_20K), // M.2_BT_PCMIN (test point)
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D8, UP_20K), // M.2_BT_PCMCLK (test point)
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D9, UP_20K),
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D10, UP_20K),
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), // NC PAD_NC(GPP_D11, UP_20K),
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP), // NC PAD_NC(GPP_D12, UP_20K),
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP), // NC PAD_NC(GPP_D13, UP_20K),
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP), // NC PAD_NC(GPP_D14, UP_20K),
PAD_CFG_GPI(GPP_E0, UP_20K, DEEP), // NC PAD_NC(GPP_D15, UP_20K),
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET PAD_NC(GPP_D16, UP_20K),
PAD_CFG_GPI(GPP_E2, UP_20K, DEEP), // NC PAD_NC(GPP_D17, UP_20K),
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // 10k pull up PAD_NC(GPP_D18, UP_20K),
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // NC PAD_NC(GPP_D19, UP_20K),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // M2_P1_SATA_DEVSLP PAD_NC(GPP_D20, UP_20K),
_PAD_CFG_STRUCT(GPP_E6, 0x82040100, 0x0000), // SMI# PAD_NC(GPP_D21, UP_20K),
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN# PAD_NC(GPP_D22, UP_20K),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# PAD_NC(GPP_D23, UP_20K),
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // USB_OC0# (test point)
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // USB_OC1# (test point) /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // USB_OC2# (test point) PAD_NC(GPP_E0, UP_20K),
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // USB_OC3# (test point) PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET
PAD_CFG_TERM_GPO(GPP_F0, 1, NONE, RSMRST), // TBT_PERST_N PAD_NC(GPP_E2, UP_20K),
PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error) PAD_CFG_GPI(GPP_E3, NONE, DEEP), // 10k pull up
PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET PAD_NC(GPP_E4, UP_20K),
PAD_CFG_GPI(GPP_F3, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // M2_P1_SATA_DEVSLP
PAD_CFG_GPI(GPP_F4, UP_20K, DEEP), // NC _PAD_CFG_STRUCT(GPP_E6, 0x82040100, 0x0000), // SMI#
PAD_CFG_GPI(GPP_F5, UP_20K, DEEP), // NC PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP (board error) PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP), // NC PAD_NC(GPP_E9, UP_20K), // USB_OC0# (test point)
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // NC PAD_NC(GPP_E10, UP_20K), // USB_OC1# (test point)
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP), // NC PAD_NC(GPP_E11, UP_20K), // USB_OC2# (test point)
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC PAD_NC(GPP_E12, UP_20K), // USB_OC3# (test point)
PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // PCH_RSVD
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP), // NC /* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT PAD_CFG_TERM_GPO(GPP_F0, 1, NONE, RSMRST), // TBT_PERST_N
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull to H_SKTOCC_N PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error)
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP), // USB_OC4# (test point) PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP), // NC PAD_NC(GPP_F3, UP_20K),
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), // NC PAD_NC(GPP_F4, UP_20K),
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // USB_OC7# (test point) PAD_NC(GPP_F5, UP_20K),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP (board error)
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON PAD_NC(GPP_F7, UP_20K),
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS PAD_NC(GPP_F8, UP_20K),
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH PAD_NC(GPP_F9, UP_20K),
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC
PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), // BOARD_ID1 PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // PCH_RSVD
PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), // BOARD_ID2 PAD_NC(GPP_F12, UP_20K),
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), // BOARD_ID3 PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT
PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), // BOARD_ID4 PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull to H_SKTOCC_N
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), // GPIO4_1V8_MAIN_EN_R PAD_NC(GPP_F15, UP_20K), // USB_OC4# (test point)
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP), // NC PAD_NC(GPP_F16, UP_20K),
PAD_CFG_GPI(GPP_G6, UP_20K, DEEP), // test point PAD_NC(GPP_F17, UP_20K),
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP), // NC PAD_NC(GPP_F18, UP_20K), // USB_OC7# (test point)
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CLK_REQ7_LAN# PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ8_PEG# PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // CLK_REQ9_CARD# PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
_PAD_CFG_STRUCT(GPP_H4, 0x40880100, 0x3000), // RTD3_PCIE_WAKE# PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ11_SSD2#
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ12_SSD1# /* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_H7, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_H8, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_H9, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), // BOARD_ID3
PAD_CFG_GPI(GPP_H10, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), // BOARD_ID4
PAD_CFG_GPI(GPP_H11, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), // GPIO4_1V8_MAIN_EN_R
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 (test point) PAD_NC(GPP_G5, UP_20K),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up PAD_NC(GPP_G6, UP_20K),
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP), // NC PAD_NC(GPP_G7, UP_20K),
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 20k pull up
PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R /* ------- GPIO Group GPP_H ------- */
PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CLK_REQ7_LAN#
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP), // GPIO_CARD_AUX PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ8_PEG#
PAD_CFG_TERM_GPO(GPP_H20, 1, NONE, DEEP), // GPIO_CARD PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // CLK_REQ9_CARD#
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP), // 20k pull down, 4.7k pull up _PAD_CFG_STRUCT(GPP_H4, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ11_SSD2#
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT# PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ12_SSD1#
PAD_CFG_GPI(GPP_I0, UP_20K, DEEP), // NC PAD_NC(GPP_H7, UP_20K),
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD PAD_NC(GPP_H8, UP_20K),
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // G_DP_DHPD_E PAD_NC(GPP_H9, UP_20K),
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // OUT2_HPD PAD_NC(GPP_H10, UP_20K),
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD PAD_NC(GPP_H11, UP_20K),
PAD_CFG_GPI(GPP_I5, UP_20K, DEEP), // NC PAD_NC(GPP_H12, NONE), // eSPI flash sharing mode strap
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // NC PAD_NC(GPP_H14, UP_20K),
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 20k pull up
PAD_CFG_GPI(GPP_I9, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
_PAD_CFG_STRUCT(GPP_I10, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // 10k pull to H_SKTOCC_N, 10k pull up PAD_NC(GPP_H18, UP_20K),
PAD_CFG_GPI(GPP_I12, DN_20K, DEEP), // D02C_BOARD_ID PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP), // GPIO_CARD_AUX
PAD_CFG_GPI(GPP_I13, UP_20K, DEEP), // NC PAD_CFG_TERM_GPO(GPP_H20, 1, NONE, DEEP), // GPIO_CARD
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_H21, UP_20K, DEEP), // 20k pull down, 4.7k pull up
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // GPP_J1 (really CPU_VCCIO_PWR_GATE#) PAD_NC(GPP_H22, UP_20K),
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), // 100k pull down PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT#
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP), // NC
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_BRI_DT_BT_UART0_RTS /* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP PAD_NC(GPP_I0, UP_20K),
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX _PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP _PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // G_DP_DHPD_E
PAD_CFG_GPI(GPP_J8, UP_20K, DEEP), // NC _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // OUT2_HPD
PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // 100k pull up, 100k pull down PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // 100k pull down PAD_NC(GPP_I5, UP_20K),
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // 75k pull down PAD_NC(GPP_I6, UP_20K),
PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // NC PAD_NC(GPP_I7, UP_20K),
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // NC PAD_NC(GPP_I8, UP_20K),
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // NC PAD_NC(GPP_I9, UP_20K),
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI# _PAD_CFG_STRUCT(GPP_I10, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // 10k pull to H_SKTOCC_N, 10k pull up
PAD_CFG_GPI(GPP_K5, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_I12, DN_20K, DEEP), // D02C_BOARD_ID (10k pull up)
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI# PAD_NC(GPP_I13, UP_20K),
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // NC PAD_NC(GPP_I14, UP_20K),
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2 /* ------- GPIO Group GPP_J ------- */
PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP), // LANRTD3_WAKE# PAD_CFG_GPI(GPP_J0, NONE, DEEP), // CNVI_GNSS_PA_BLANKING
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3 PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_VCCIO_PWR_GATE
PAD_CFG_GPI(GPP_K12, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP), // NC PAD_NC(GPP_J3, UP_20K),
PAD_CFG_GPI(GPP_K14, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point) PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_BRI_DT_BT_UART0_RTS
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP
PAD_CFG_GPI(GPP_K16, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP), // NC PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP
PAD_CFG_GPI(GPP_K18, UP_20K, DEEP), // NC PAD_NC(GPP_J8, UP_20K),
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), // SMI# PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // 100k pull up, 100k pull down
PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT# PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // 75k pull down
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP), // OVRM
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R /* ------- GPIO Group GPP_K ------- */
PAD_NC(GPP_K0, UP_20K),
PAD_NC(GPP_K1, UP_20K),
PAD_NC(GPP_K2, UP_20K),
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, UP_20K),
PAD_NC(GPP_K5, UP_20K),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_NC(GPP_K7, UP_20K),
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP), // LANRTD3_WAKE#
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3
PAD_NC(GPP_K12, UP_20K),
PAD_NC(GPP_K13, UP_20K),
PAD_CFG_GPI(GPP_K14, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point)
PAD_NC(GPP_K15, UP_20K),
PAD_NC(GPP_K16, UP_20K),
PAD_NC(GPP_K17, UP_20K),
PAD_NC(GPP_K18, UP_20K),
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), // SMI#
PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT#
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP), // OVRM
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R
}; };
#endif #endif