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mb/google/asurada: fine tune the data lane trail for ANX7625

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The ANX7625 display bridge requires customized
hs_da_trail time.

This patch is based on CB:51433 (commit 6482b16,
"mb/google/kukui: fine tune the data lane trail")

BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0eedb8fa6a1b3dfd9619c7cbf755c9c4071a8484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Hung-Te Lin
2021-09-03 15:44:04 +08:00
parent 2ef4b7ed18
commit e5cf666b9a
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/asurada/mainboard.c
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@ -64,6 +64,12 @@ static void register_reset_to_bl31(void)
register_bl31_aux_param(&param_reset.h); register_bl31_aux_param(&param_reset.h);
} }
/* Override hs_da_trail for ANX7625 */
void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
{
timing->da_hs_trail += 9;
}
/* Set up backlight control pins as output pin and power-off by default */ /* Set up backlight control pins as output pin and power-off by default */
static void configure_backlight_and_bridge(void) static void configure_backlight_and_bridge(void)
{ {