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soc/intel/apollolake: Improve cold boot and S3 resume

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FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.

BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified system_resume_firmware_ec time reduction.

Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
John Zhao
2018-10-30 15:12:11 -07:00
committed by Patrick Georgi
parent e05fa66b24
commit e673e5c09e
3 changed files with 21 additions and 2 deletions
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10
src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
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@@ -1715,9 +1715,15 @@ typedef struct {
**/
UINT8 SkipSpiPCP;
/** Offset 0x03AB
/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration
Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
(23:16) + OR Value (15:8) + AND Value (7:0)
**/
UINT8 ReservedFspsUpd[5];
UINT32 PmicPmcIpcCtrl;
/** Offset 0x03AF
**/
UINT8 ReservedFspsUpd[1];
} FSP_S_CONFIG;
/** Fsp S SGX Configuration