intel: fix microcode compilation failure in bootblock
When not building with CONFIG_SSE there are not enough registers for ROMCC to use for spilling. The previous changes to this file had too many local variables that needed to be tracked -- thus causing romcc compilation issues. Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4845 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -110,11 +110,10 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
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const void *intel_microcode_find(void)
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const void *intel_microcode_find(void)
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{
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{
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struct cbfs_file *microcode_file;
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struct cbfs_file *microcode_file;
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void *microcode_updates;
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const struct microcode *ucode_updates;
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u32 eax, microcode_len;
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u32 eax, microcode_len;
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u32 pf, rev, sig, update_size;
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u32 pf, rev, sig, update_size;
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unsigned int x86_model, x86_family;
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unsigned int x86_model, x86_family;
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const struct microcode *m;
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msr_t msr;
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msr_t msr;
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#ifdef __PRE_RAM__
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#ifdef __PRE_RAM__
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@ -127,7 +126,7 @@ const void *intel_microcode_find(void)
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if (!microcode_file)
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if (!microcode_file)
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return NULL;
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return NULL;
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microcode_updates = CBFS_SUBHEADER(microcode_file);
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ucode_updates = CBFS_SUBHEADER(microcode_file);
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microcode_len = ntohl(microcode_file->len);
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microcode_len = ntohl(microcode_file->len);
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/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
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/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
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@ -154,12 +153,11 @@ const void *intel_microcode_find(void)
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sig, pf, rev);
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sig, pf, rev);
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#endif
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#endif
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while (microcode_len >= sizeof(*m)) {
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while (microcode_len >= sizeof(*ucode_updates)) {
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m = microcode_updates;
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/* Newer microcode updates include a size field, whereas older
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/* Newer microcode updates include a size field, whereas older
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* containers set it at 0 and are exactly 2048 bytes long */
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* containers set it at 0 and are exactly 2048 bytes long */
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if (m->total_size) {
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if (ucode_updates->total_size) {
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update_size = m->total_size;
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update_size = ucode_updates->total_size;
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} else {
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} else {
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#if !defined(__ROMCC__)
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#if !defined(__ROMCC__)
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printk(BIOS_SPEW, "Microcode size field is 0\n");
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printk(BIOS_SPEW, "Microcode size field is 0\n");
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@ -175,10 +173,10 @@ const void *intel_microcode_find(void)
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break;
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break;
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}
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}
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if ((m->sig == sig) && (m->pf & pf))
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if ((ucode_updates->sig == sig) && (ucode_updates->pf & pf))
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return m;
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return ucode_updates;
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microcode_updates += update_size;
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ucode_updates = (void *)((char *)ucode_updates + update_size);
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microcode_len -= update_size;
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microcode_len -= update_size;
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}
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}
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