sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tgl: Add config to disable IME

Browse Source 
Unlike CNL, default to false due to the S0ix issue.

Change-Id: I6da4f59759c25dc0247d2beaaa7d793d6f4e6795
This commit is contained in:
Tim Crawford
2021-04-20 11:51:33 -06:00
committed by Jeremy Soller
parent 9962529199
commit e67769d719
2 changed files with 33 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/intel/tigerlake/Kconfig
View File

@@ -250,4 +250,9 @@ config EARLY_TCSS_DISPLAY
help
Enable displays to be detected over Type-C ports during boot.
config DISABLE_ME
bool "Disable the IME by setting the HAP bit at run-time"
# XXX: Prevents CPU from reaching C10
default n
endif

28
src/soc/intel/tigerlake/me.c
View File

@@ -163,5 +163,33 @@ static void dump_me_status(void *unused)
hfsts6.fields.txt_support ? "YES" : "NO");
}
#if CONFIG(DISABLE_ME)
static void disable_me(void* unused)
{
printk(BIOS_DEBUG, "ME: send disable message\n");
struct disable_command {
uint32_t hdr;
uint32_t rule_id;
uint8_t rule_len;
uint32_t rule_data;
} __packed msg;
msg.hdr = 0x303;
msg.rule_id = 6;
msg.rule_len = 4;
msg.rule_data = 0;
if (!heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR))
printk(BIOS_ERR, "ME: Error sending DISABLE msg\n");
dump_me_status(unused);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, disable_me, NULL);
#else // DISABLE_ME
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL);
#endif // DISABLE_ME