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AGESA fam15: Common agesawrapper

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Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a
common file for now and split eventlog parser to a separate file.

Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7155
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-10-22 15:53:34 +03:00
parent 9bb38c963f
commit e68f4ffb97
15 changed files with 526 additions and 3396 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

421
src/mainboard/amd/dinar/agesawrapper.c
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@ -38,18 +38,6 @@
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ /*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/
/* /*
BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the
@ -62,17 +50,13 @@ Bits Buses Bits Buses
3h 8 8h 256 3h 8 8h 256
4h 16 Fh-9h Reserved 4h 16 Fh-9h Reserved
*/ */
STATIC STATIC UINT8 GetEndBusNum(VOID)
UINT8
GetEndBusNum (
VOID
)
{ {
UINT64 BusNum; UINT64 BusNum;
UINT8 Index; UINT8 Index;
for (Index = 1; Index <= 8; Index ++ ) { for (Index = 1; Index <= 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1 ) { if (BusNum == 1) {
break; break;
} }
} }
@ -87,15 +71,15 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void)
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
UINT32 TopMem; UINT32 TopMem;
UINT32 NodeCnt; UINT32 nodes;
UINT32 Node; UINT32 node;
UINT32 SbLink; UINT32 SbLink;
UINT32 Index; UINT32 i;
/* get the number of coherent nodes in the system */ /* get the number of coherent nodes in the system */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4] nodes = ((PciData >> 4) & 7) + 1; //nodes[6:4]
/* Find out the Link ID of Node0 that connects to the /* Find out the Link ID of Node0 that connects to the
* Southbridge (system IO hub). e.g. family10 MCM Processor, * Southbridge (system IO hub). e.g. family10 MCM Processor,
* SbLink is Processor0 Link2, internal Node0 Link3 * SbLink is Processor0 Link2, internal Node0 Link3
@ -104,48 +88,47 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void)
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
SbLink = (PciData >> 8) & 3; //assume ganged SbLink = (PciData >> 8) & 3; //assume ganged
/* Enable MMIO on AMD CPU Address Map Controller for all nodes */ /* Enable MMIO on AMD CPU Address Map Controller for all nodes */
for (Node = 0; Node < NodeCnt; Node ++) { for (node = 0; node < nodes; node++) {
/* clear all MMIO Mapped Base/Limit Registers */ /* clear all MMIO Mapped Base/Limit Registers */
for (Index = 0; Index < 8; Index ++) { for (i = 0; i < 8; i++) {
PciData = 0x00000000; PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
} }
/* clear all IO Space Base/Limit Registers */ /* clear all IO Space Base/Limit Registers */
for (Index = 0; Index < 4; Index ++) { for (i = 0; i < 4; i++) {
PciData = 0x00000000; PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
} }
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
PciData = (0xA0000 >> 8) |3; PciData = (0xA0000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
PciData = 0xB0000 >> 8; PciData = 0xB0000 >> 8;
PciData &= (~0xFF); PciData &= (~0xFF);
PciData |= SbLink << 4; PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set UMA MMIO. */ /* Set UMA MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
TopMem = (UINT32)MsrReg; TopMem = (UINT32) MsrReg;
MsrReg = (MsrReg >> 8) | 3; MsrReg = (MsrReg >> 8) | 3;
PciData = (UINT32)MsrReg; PciData = (UINT32) MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8c);
if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) {
PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8;
} } else {
else {
PciData = (0x100000000ull - 1) >> 8; PciData = (0x100000000ull - 1) >> 8;
} }
PciData &= (~0xFF); PciData &= (~0xFF);
@ -153,21 +136,21 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void)
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set PCIE MMIO. */ /* Set PCIE MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x90);
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x94);
PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF); PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) & (~0xFF);
PciData &= (~0xFF); PciData &= (~0xFF);
PciData |= MMIO_NP_BIT; PciData |= MMIO_NP_BIT;
PciData |= SbLink << 4; PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set XAPIC MMIO. 24K */ /* Set XAPIC MMIO. 24K */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x98);
PciData = (0xFEC00000 >> 8) |3; PciData = (0xFEC00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x9c);
PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8);
PciData &= (~0xFF); PciData &= (~0xFF);
PciData |= MMIO_NP_BIT; PciData |= MMIO_NP_BIT;
@ -175,21 +158,21 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void)
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA0);
PciData = (0xFEE00000 >> 8) |3; PciData = (0xFEE00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA8);
PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8;
PciData &= (~0xFF); PciData &= (~0xFF);
PciData |= MMIO_NP_BIT; PciData |= MMIO_NP_BIT;
PciData |= SbLink << 4; PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/ /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
PciData = 0x13; PciData = 0x13;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
PciData = 0x00FFF000; PciData = 0x00FFF000;
PciData &= (~0x7F); PciData &= (~0x7F);
PciData |= SbLink << 4; PciData |= SbLink << 4;
@ -211,346 +194,38 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register. Address MSR register.
*/ */
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1; MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum() << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/* /*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/ */
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | BIT46; MsrReg = MsrReg | BIT46;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set PCIE MMIO. */ /* Set PCIE MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x90);
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3;
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x94);
PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT; PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) | MMIO_NP_BIT;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Enable memory access */ /* Enable memory access */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
PciData |= BIT1; PciData |= BIT1;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); LibAmdMsrWrite(0x20E, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); LibAmdMsrWrite(0x20F, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
return Status; return Status;
} }
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
#endif
#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
#else
status = AGESA_SUCCESS;
#endif
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
}
static VOID
OemCustomizeInitPost (
IN AMD_POST_PARAMS *InitPost
)
{
InitPost->MemConfig.UmaMode = UMA_AUTO;
InitPost->MemConfig.BottomIo = 0xE0;
InitPost->MemConfig.UmaSize = 0xE0-0xC0;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
/* OEM Should Customize the defaults through this hook */
OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
printk(BIOS_DEBUG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate(AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
AP_EXE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams,
0,
sizeof (AP_EXE_PARAMS),
&(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdLateRunApTask (&AmdLateParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog(void)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass, AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1, AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3, AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

4
src/mainboard/supermicro/h8qgi/Makefile.inc
View File

@ -20,16 +20,12 @@
romstage-y += rd890_cfg.c romstage-y += rd890_cfg.c
romstage-y += sb700_cfg.c romstage-y += sb700_cfg.c
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += platform_oem.c
ramstage-y += rd890_cfg.c ramstage-y += rd890_cfg.c
ramstage-y += sb700_cfg.c ramstage-y += sb700_cfg.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += platform_oem.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx

49
src/mainboard/supermicro/h8qgi/platform_oem.c
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "Filecode.h"
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
}

4
src/mainboard/supermicro/h8scm/Makefile.inc
View File

@ -20,16 +20,12 @@
romstage-y += rd890_cfg.c romstage-y += rd890_cfg.c
romstage-y += sb700_cfg.c romstage-y += sb700_cfg.c
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += platform_oem.c
ramstage-y += rd890_cfg.c ramstage-y += rd890_cfg.c
ramstage-y += sb700_cfg.c ramstage-y += sb700_cfg.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += platform_oem.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx

1179
src/mainboard/supermicro/h8scm/agesawrapper.c
View File

File diff suppressed because it is too large Load Diff

49
src/mainboard/supermicro/h8scm/platform_oem.c
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "Filecode.h"
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
}

4
src/mainboard/tyan/s8226/Makefile.inc
View File

@ -20,16 +20,12 @@
romstage-y += rd890_cfg.c romstage-y += rd890_cfg.c
romstage-y += sb700_cfg.c romstage-y += sb700_cfg.c
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += platform_oem.c
ramstage-y += rd890_cfg.c ramstage-y += rd890_cfg.c
ramstage-y += sb700_cfg.c ramstage-y += sb700_cfg.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += platform_oem.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx

1179
src/mainboard/tyan/s8226/agesawrapper.c
View File

File diff suppressed because it is too large Load Diff

49
src/mainboard/tyan/s8226/platform_oem.c
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "Filecode.h"
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
}

3
src/northbridge/amd/agesa/Makefile.inc
View File

@ -26,3 +26,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += def_callouts.c romstage-y += def_callouts.c
ramstage-y += def_callouts.c ramstage-y += def_callouts.c
romstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c
ramstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c

2
src/northbridge/amd/agesa/agesawrapper.h
View File

@ -48,7 +48,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void);
AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitpost(void);
AGESA_STATUS agesawrapper_amdinitmid(void); AGESA_STATUS agesawrapper_amdinitmid(void);
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_BOARD_AMD_DINAR #if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14
AGESA_STATUS agesawrapper_amdreadeventlog(void); AGESA_STATUS agesawrapper_amdreadeventlog(void);
#else #else
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus);

2
src/northbridge/amd/agesa/agesawrapper_call.h
View File

@ -59,7 +59,7 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name)
#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() #define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func()
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_BOARD_AMD_DINAR #if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14
/* TODO: These families do not pass valid HeapStatus. */ /* TODO: These families do not pass valid HeapStatus. */
#define AGESA_EVENTLOG(status) \ #define AGESA_EVENTLOG(status) \
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog() if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog()

489
src/mainboard/supermicro/h8qgi/agesawrapper.c → src/northbridge/amd/agesa/eventlog.c
View File

@ -1,489 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*---------------------------------------------------------------------------------------- #include <console/console.h>
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include <stdint.h>
#include <string.h>
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h" #include "amdlib.h"
#include "Filecode.h"
#include "heapManager.h"
#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
#define FILECODE UNASSIGNED_FILE_FILECODE #if 0
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
AGESA_STATUS Status;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT32 nodes;
UINT32 node;
UINT32 sblink;
UINT32 i;
UINT32 TOM;
/* get the number of coherent nodes in the system */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
/* Find out the Link ID of Node0 that connects to the
* Southbridge (system IO hub). e.g. family10 MCM Processor,
* sbLink is Processor0 Link2, internal Node0 Link3
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
sblink = (PciData >> 8) & 3; //assume ganged
/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
for (node = 0; node < nodes; node++) {
/* clear all MMIO Mapped Base/Limit Registers */
for (i = 0; i < 8; i++) {
PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
/* clear all IO Space Base/Limit Registers */
for (i = 0; i < 4; i++) {
PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
PciData = 0x00000B00;
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
PciData = 0x00000A03;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set TOM1-FFFFFFFF to Node0 sbLink. */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
PciData = 0x00FFFF00;
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
TOM = (UINT32)MsrRead(TOP_MEM);
PciData = (TOM >> 8) | 0x03;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set MMCONF space to Node0 sbLink with NP set.
* default E0000000-EFFFFFFF
* Just have all mmio set to non-posted,
* coreboot not implemente the range by range setting yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
PciData = 0x00FFF000;
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
PciData = 0x00000033;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
* Set the MMIO Configuration Base Address and Bus Range onto
* MMIO configuration base Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | (1ULL << 46);
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof(AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdResetParams,
0,
sizeof(AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
AmdResetParams.HtConfig.Depth = 0;
//MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
//but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
#endif
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof(AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly(AmdEarlyParamsPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof(AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParams;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof(AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParams);
AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
VOID * agesawrapper_getlateinitptr(int pick)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
return NULL;
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio();
LibAmdMemFill(&AmdParamStruct,
0,
sizeof(AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate(AmdLateParamsPtr);
AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
/**
* @param[in] UINTN ApicIdOfCore,
* @param[in] AP_EXE_PARAMS *LaunchApParams
*/
AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill(&AmdLateParams,
0,
sizeof(AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0;
AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data);
Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr);
AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus);
ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED));
return Status;
}
/** /**
* *
@ -992,7 +514,7 @@ static void agesa_critical(EVENT_PARAMS *event)
break; break;
case HT_EVENT_COH_PROCESSOR_TYPE_MIX: case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
(unsigned int)event->DataParam1, (unsigned int)event->DataParam1,
(unsigned int)event->DataParam2, (unsigned int)event->DataParam2,
(unsigned int)event->DataParam3); (unsigned int)event->DataParam3);
@ -1140,13 +662,13 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event)
break; break;
} }
} }
#endif
/** /**
* @param HeapStatus -the current HeapStatus * @param HeapStatus -the current HeapStatus
*/ */
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
{ {
printk(BIOS_DEBUG, "enter in %s\n", __func__);
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
@ -1159,7 +681,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
/* I have to know the current HeapStatus to Locate the EventLogHeapPointer */
AmdEventParams.StdHeader.HeapStatus = HeapStatus; AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog(&AmdEventParams); Status = AmdReadEventLog(&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
@ -1172,10 +693,8 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",
(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam3,
(unsigned int)AmdEventParams.DataParam4); (unsigned int)AmdEventParams.DataParam4);
interpret_agesa_eventlog(&AmdEventParams);
Status = AmdReadEventLog(&AmdEventParams); Status = AmdReadEventLog(&AmdEventParams);
} }
printk(BIOS_DEBUG, "exit %s\n", __func__);
return Status; return Status;
} }

2
src/northbridge/amd/agesa/family15/Makefile.inc
View File

@ -18,5 +18,7 @@
# #
romstage-y += dimmSpd.c romstage-y += dimmSpd.c
romstage-y += agesawrapper.c
ramstage-y += northbridge.c ramstage-y += northbridge.c
ramstage-y += agesawrapper.c

448
src/northbridge/amd/agesa/family15/agesawrapper.c Normal file
View File

@ -0,0 +1,448 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "Filecode.h"
#include "heapManager.h"
#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
#define FILECODE UNASSIGNED_FILE_FILECODE
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/* TODO: Function body should be in mainboard directory. */
static VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS * InitEarly)
{
}
static VOID OemCustomizeInitPost(AMD_POST_PARAMS *InitPost)
{
#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
InitPost->MemConfig.UmaMode = UMA_AUTO;
InitPost->MemConfig.BottomIo = 0xE0;
InitPost->MemConfig.UmaSize = 0xE0-0xC0;
#endif
}
#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT32 nodes;
UINT32 node;
UINT32 sblink;
UINT32 i;
UINT32 TOM;
/* get the number of coherent nodes in the system */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
/* Find out the Link ID of Node0 that connects to the
* Southbridge (system IO hub). e.g. family10 MCM Processor,
* sbLink is Processor0 Link2, internal Node0 Link3
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
sblink = (PciData >> 8) & 3; //assume ganged
/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
for (node = 0; node < nodes; node++) {
/* clear all MMIO Mapped Base/Limit Registers */
for (i = 0; i < 8; i++) {
PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
/* clear all IO Space Base/Limit Registers */
for (i = 0; i < 4; i++) {
PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
PciData = 0x00000B00;
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
PciData = 0x00000A03;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set TOM1-FFFFFFFF to Node0 sbLink. */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
PciData = 0x00FFFF00;
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
TOM = (UINT32) MsrRead(TOP_MEM);
PciData = (TOM >> 8) | 0x03;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set MMCONF space to Node0 sbLink with NP set.
* default E0000000-EFFFFFFF
* Just have all mmio set to non-posted,
* coreboot not implemente the range by range setting yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; //1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
PciData = 0x00FFF000;
PciData |= sblink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
PciData = 0x00000033;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
* Set the MMIO Configuration Base Address and Bus Range onto
* MMIO configuration base Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | (1ULL << 46);
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
return AGESA_SUCCESS;
}
#endif
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
AmdResetParams.HtConfig.Depth = 0;
//MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
//but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
#endif
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
/* OEM Should Customize the defaults through this hook */
OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly(AmdEarlyParamsPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
&AmdParamStruct.StdHeader);
FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
/* OEM Should Customize the defaults through this hook */
OemCustomizeInitPost(PostParams);
status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
&AmdParamStruct.StdHeader);
FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParams;
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParams);
AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
VOID *agesawrapper_getlateinitptr(int pick)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
return NULL;
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio();
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct(&AmdParamStruct);
if (status != AGESA_SUCCESS) {
return status;
}
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr);
status = AmdInitLate(AmdLateParamsPtr);
AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus);
ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return status;
}
/**
* @param[in] UINTN ApicIdOfCore,
* @param[in] AP_EXE_PARAMS *LaunchApParams
*/
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
{
AGESA_STATUS status;
AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill(&AmdLateParams, 0, sizeof(AMD_LATE_PARAMS), &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0;
AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data);
status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr);
AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus);
ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED));
return status;
}