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intel fsp1_1: prepare for romstage vboot verification split

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In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:

- Add fsp/car.h to house the declarations for functions in
  the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
  cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
  in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
  romstage separated from cache-as-ram as well as one that
  is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
  soc/intel/{braswell,common,skylake}.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
2015-09-24 12:26:31 -05:00
committed by Aaron Durbin
parent cc5ac17fab
commit e6af4be158
13 changed files with 321 additions and 241 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/drivers/intel/fsp1_1/Makefile.inc
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@@ -18,6 +18,7 @@
# Foundation, Inc.
#
romstage-y += car.c
romstage-y += fsp_util.c
romstage-y += hob.c

153
src/drivers/intel/fsp1_1/after_raminit.S Normal file
View File

@@ -0,0 +1,153 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
/*
* This is the common entry point after DRAM has been initialized.
*/
/*
* eax: New stack address
* ebx: FSP_INFO_HEADER address
*/
/* Switch to the stack in RAM */
movl %eax, %esp
/* Calculate TempRamExit entry into FSP */
movl %ebx, %ebp
mov 0x40(%ebp), %eax
add 0x1c(%ebp), %eax
/* Build the call frame */
pushl $0
/* Call TempRamExit */
call *%eax
add $4, %esp
cmp $0, %eax
jz 1f
/*
* Failures for post code BC - failed in TempRamExit
*
* 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
* 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
*/
movb $0xBC, %ah
jmp .Lhlt
1:
/* Display the MTRRs */
call soc_display_mtrrs
/*
* The stack contents are initialized in src/soc/intel/common/stack.c
* to be the following:
*
* *
* *
* *
* +36: MTRR mask 1 63:32
* +32: MTRR mask 1 31:0
* +28: MTRR base 1 63:32
* +24: MTRR base 1 31:0
* +20: MTRR mask 0 63:32
* +16: MTRR mask 0 31:0
* +12: MTRR base 0 63:32
* +8: MTRR base 0 31:0
* +4: Number of MTRRs to setup (described above)
* +0: Number of variable MTRRs to clear
*/
/* Clear all of the variable MTRRs. */
popl %ebx
movl $MTRRphysBase_MSR(0), %ecx
clr %eax
clr %edx
1:
testl %ebx, %ebx
jz 1f
wrmsr /* Write MTRR base. */
inc %ecx
wrmsr /* Write MTRR mask. */
inc %ecx
dec %ebx
jmp 1b
1:
/* Get number of MTRRs. */
popl %ebx
movl $MTRRphysBase_MSR(0), %ecx
2:
testl %ebx, %ebx
jz 2f
/* Low 32 bits of MTRR base. */
popl %eax
/* Upper 32 bits of MTRR base. */
popl %edx
/* Write MTRR base. */
wrmsr
inc %ecx
/* Low 32 bits of MTRR mask. */
popl %eax
/* Upper 32 bits of MTRR mask. */
popl %edx
/* Write MTRR mask. */
wrmsr
inc %ecx
dec %ebx
jmp 2b
2:
post_code(0x39)
/* And enable cache again after setting MTRRs. */
movl %cr0, %eax
andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0
post_code(0x3a)
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
orl $MTRRdefTypeEn, %eax
wrmsr
post_code(0x3b)
/* Invalidate the cache again. */
invd
post_code(0x3c)
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
call after_cache_as_ram

137
src/drivers/intel/fsp1_1/cache_as_ram.inc
View File

@@ -28,10 +28,6 @@
* performs the final stage of initialization.
*/
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
#include <cbmem.h>
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
@@ -125,12 +121,10 @@ CAR_init_done:
* mm1: high 32-bits of TSC value
*/
/* Create fsp_car_context on stack. */
/* Create cache_as_ram_params on stack */
pushl %edx /* bootloader CAR end */
pushl %ecx /* bootloader CAR begin */
pushl %ebp /* FSP_INFO_HEADER */
/* Create cache_as_ram_params on stack */
pushl %esp /* chipset_context -> fsp_car_context */
pushl %edi /* bist */
movd %mm1, %eax
pushl %eax /* tsc[63:32] */
@@ -154,122 +148,10 @@ CAR_init_done:
before_romstage:
post_code(0x23)
/* Call romstage_main(struct cache_as_ram_params *) */
call romstage_main
/*
* eax: New stack address
* ebx: FSP_INFO_HEADER address
*/
/* Switch to the stack in RAM */
movl %eax, %esp
/* Calculate TempRamExit entry into FSP */
movl %ebx, %ebp
mov 0x40(%ebp), %eax
add 0x1c(%ebp), %eax
/* Build the call frame */
pushl $0
/* Call TempRamExit */
call *%eax
add $4, %esp
cmp $0, %eax
jne halt3
/* Display the MTRRs */
call soc_display_mtrrs
/*
* The stack contents are initialized in src/soc/intel/common/stack.c
* to be the following:
*
* *
* *
* *
* +36: MTRR mask 1 63:32
* +32: MTRR mask 1 31:0
* +28: MTRR base 1 63:32
* +24: MTRR base 1 31:0
* +20: MTRR mask 0 63:32
* +16: MTRR mask 0 31:0
* +12: MTRR base 0 63:32
* +8: MTRR base 0 31:0
* +4: Number of MTRRs to setup (described above)
* +0: Number of variable MTRRs to clear
*/
/* Clear all of the variable MTRRs. */
popl %ebx
movl $MTRRphysBase_MSR(0), %ecx
clr %eax
clr %edx
1:
testl %ebx, %ebx
jz 1f
wrmsr /* Write MTRR base. */
inc %ecx
wrmsr /* Write MTRR mask. */
inc %ecx
dec %ebx
jmp 1b
1:
/* Get number of MTRRs. */
popl %ebx
movl $MTRRphysBase_MSR(0), %ecx
2:
testl %ebx, %ebx
jz 2f
/* Low 32 bits of MTRR base. */
popl %eax
/* Upper 32 bits of MTRR base. */
popl %edx
/* Write MTRR base. */
wrmsr
inc %ecx
/* Low 32 bits of MTRR mask. */
popl %eax
/* Upper 32 bits of MTRR mask. */
popl %edx
/* Write MTRR mask. */
wrmsr
inc %ecx
dec %ebx
jmp 2b
2:
post_code(0x39)
/* And enable cache again after setting MTRRs. */
movl %cr0, %eax
andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0
post_code(0x3a)
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
orl $MTRRdefTypeEn, %eax
wrmsr
post_code(0x3b)
/* Invalidate the cache again. */
invd
post_code(0x3c)
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
call romstage_after_car
/* Call cache_as_ram_main(struct cache_as_ram_params *) */
call cache_as_ram_main
#include "after_raminit.S"
movb $0x69, %ah
jmp .Lhlt
@@ -304,17 +186,6 @@ halt2:
movb $0xBB, %ah
jmp .Lhlt
halt3:
/*
* Failures for post code BC - failed in TempRamExit
*
* 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
* 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
*/
movb $0xBC, %ah
.Lhlt:
xchg %al, %ah
#if IS_ENABLED(CONFIG_POST_IO)

85
src/drivers/intel/fsp1_1/car.c Normal file
View File

@@ -0,0 +1,85 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <fsp/car.h>
#include <soc/intel/common/util.h>
#include <timestamp.h>
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
{
/* Initialize timestamp book keeping only once. */
timestamp_init(car_params->tsc);
/* Call into pre-console init code then initialize console. */
car_soc_pre_console_init();
car_mainboard_pre_console_init();
console_init();
printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
car_params->bootloader_car_end !=
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
CONFIG_DCACHE_RAM_BASE,
CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
(long)car_params->bootloader_car_start,
(long)car_params->bootloader_car_end);
}
car_soc_post_console_init();
car_mainboard_post_console_init();
/* Ensure the EC is in the right mode for recovery */
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
google_chromeec_early_init();
/* Return new stack value in ram back to assembly stub. */
return cache_as_ram_stage_main(car_params->fih);
}
asmlinkage void after_cache_as_ram(void *chipset_context)
{
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
soc_display_mtrrs();
after_cache_as_ram_stage();
}
void __attribute__((weak)) car_mainboard_pre_console_init(void)
{
}
void __attribute__((weak)) car_soc_pre_console_init(void)
{
}
void __attribute__((weak)) car_mainboard_post_console_init(void)
{
}
void __attribute__((weak)) car_soc_post_console_init(void)
{
}

52
src/drivers/intel/fsp1_1/include/fsp/car.h Normal file
View File

@@ -0,0 +1,52 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef FSP1_1_CAR_H
#define FSP1_1_CAR_H
#include <arch/cpu.h>
#include <fsp/api.h>
#include <stdint.h>
/* cache-as-ram support for FSP 1.1. */
struct cache_as_ram_params {
uint64_t tsc;
uint32_t bist;
FSP_INFO_HEADER *fih;
uintptr_t bootloader_car_start;
uintptr_t bootloader_car_end;
};
/* Entry points from the cache-as-ram assembly code. */
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
asmlinkage void after_cache_as_ram(void *chipset_context);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in ram after
* exiting cache-as-ram mode. */
void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
void after_cache_as_ram_stage(void);
/* Mainboard and SoC initialization prior to console. */
void car_mainboard_pre_console_init(void);
void car_soc_pre_console_init(void);
/* Mainboard and SoC initialization post console initialization. */
void car_mainboard_post_console_init(void);
void car_soc_post_console_init(void);
#endif

7
src/drivers/intel/fsp1_1/include/fsp/util.h
View File

@@ -28,13 +28,6 @@
#include <program_loading.h>
#include <commonlib/region.h>
/* cache-as-ram context for FSP 1.1. */
struct fsp_car_context {
FSP_INFO_HEADER *fih;
uintptr_t bootloader_car_start;
uintptr_t bootloader_car_end;
};
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
/* Set FSP's runtime information. */