intel fsp1_1: prepare for romstage vboot verification split

In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:

- Add fsp/car.h to house the declarations for functions in
  the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
  cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
  in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
  romstage separated from cache-as-ram as well as one that
  is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
  soc/intel/{braswell,common,skylake}.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/skylake/romstage/romstage.c

@@ -46,8 +46,15 @@
 #include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-/* SOC initialization before the console is enabled */
-void soc_pre_console_init(void)
+/* SOC initialization before RAM is enabled */
+void soc_pre_ram_init(struct romstage_params *params)
+{
+	/* Prepare to initialize memory */
+	soc_fill_pei_data(params->pei_data);
+}
+
+/* SOC initialization before the console is enabled. */
+void car_soc_pre_console_init(void)
 {
 	/* System Agent Early Initialization */
 	systemagent_early_init();
@@ -56,14 +63,7 @@ void soc_pre_console_init(void)
 		pch_uart_init();
 }
 
-/* SOC initialization before RAM is enabled */
-void soc_pre_ram_init(struct romstage_params *params)
-{
-	/* Prepare to initialize memory */
-	soc_fill_pei_data(params->pei_data);
-}
-
-void soc_romstage_init(struct romstage_params *params)
+void car_soc_post_console_init(void)
 {
 	report_platform_info();
 	set_max_freq();