PIT: memory setup
Tested and working. Gets us to ramstage. Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ronald G. Minnich
committed by
Stefan Reinauer
Stefan Reinauer
parent
eb9517cce9
commit
e6af929661
@@ -24,6 +24,7 @@
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#include "clk.h"
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#include "cpu.h"
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#include "dp.h"
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#include "dmc.h"
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#include "setup.h"
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void system_clock_init(void)
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@@ -93,6 +93,82 @@
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/* Distance between each Trust Zone PC register set */
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#define TZPC_BASE_OFFSET 0x10000
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/* EXYNOS5420 Common*/
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#define EXYNOS5420_I2C_SPACING 0x10000
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#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
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#define EXYNOS5420_PRO_ID 0x10000000
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#define EXYNOS5420_CLOCK_BASE 0x10010000
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#define EXYNOS5420_POWER_BASE 0x10040000
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#define EXYNOS5420_SWRESET 0x10040400
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#define EXYNOS5420_SYSREG_BASE 0x10050000
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#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
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#define EXYNOS5420_DMC_PHY0_BASE 0x10C00000
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#define EXYNOS5420_DMC_PHY1_BASE 0x10C10000
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#define EXYNOS5420_DMC_DREXI_0 0x10C20000
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#define EXYNOS5420_DMC_DREXI_1 0x10C30000
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#define EXYNOS5420_DMC_TZASC_0 0x10D40000
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#define EXYNOS5420_DMC_TZASC_1 0x10D50000
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#define EXYNOS5420_USB_HOST_XHCI_BASE 0x12000000
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#define EXYNOS5420_USB3PHY_BASE 0x12100000
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#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
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#define EXYNOS5420_MMC_BASE 0x12200000
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#define EXYNOS5420_SROMC_BASE 0x12250000
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#define EXYNOS5420_UART_BASE 0x12C00000
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#define EXYNOS5420_I2C_BASE 0x12C60000
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#define EXYNOS5420_I2C_8910_BASE 0x12E00000
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#define EXYNOS5420_SPI_BASE 0x12D20000
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#define EXYNOS5420_I2S_BASE 0x12D60000
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#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
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#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
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#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
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#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
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#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
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#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
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#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
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#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
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#define EXYNOS5420_DP_BASE 0x145B0000
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#define EXYNOS5420_INF_REG_BASE 0x10040800
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#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
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#define ARM_CORE0_CONFIG (EXYNOS5420_POWER_BASE + 0x2000)
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#define ARM_CORE0_STATUS (EXYNOS5420_POWER_BASE + 0x2004)
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#define CORE_CONFIG_OFFSET 0x80
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#define CORE_COUNT 0x8
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/*
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* POWER
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*/
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#define PMU_BASE EXYNOS5420_POWER_BASE
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#define SW_RST_REG_OFFSET 0x400
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#define INF_REG_BASE EXYNOS5420_INF_REG_BASE
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#define INF_REG0_OFFSET 0x00
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#define INF_REG1_OFFSET 0x04
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#define INF_REG2_OFFSET 0x08
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#define INF_REG3_OFFSET 0x0C
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#define INF_REG4_OFFSET 0x10
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#define INF_REG5_OFFSET 0x14
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#define INF_REG6_OFFSET 0x18
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#define INF_REG7_OFFSET 0x1C
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#define PMU_SPARE_BASE (EXYNOS5420_INF_REG_BASE + 0x100)
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#define PMU_SPARE_0 PMU_SPARE_BASE
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#define PMU_SPARE_1 (PMU_SPARE_BASE + 0x4)
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#define PMU_SPARE_2 (PMU_SPARE_BASE + 0x8)
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#define PMU_SPARE_3 (PMU_SPARE_BASE + 0xc)
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#define RST_FLAG_REG PMU_SPARE_BASE
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#define RST_FLAG_VAL 0xfcba0d10
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#define PAD_RETENTION_DRAM_STATUS (EXYNOS5420_POWER_BASE + 0x3004)
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#define PAD_RETENTION_DRAM_COREBLK_OPTION (EXYNOS5420_POWER_BASE + 0x31E8)
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#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
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#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE)
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#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE)
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#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE)
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@@ -18,17 +18,68 @@
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#ifndef CPU_SAMSUNG_EXYNOS5420_DMC_H
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#define CPU_SAMSUNG_EXYNOS5420_DMC_H
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#define DMC_INTERLEAVE_SIZE 0x1f
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/* CONCONTROL register fields */
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#define CONCONTROL_DFI_INIT_START_SHIFT 28
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#define CONCONTROL_RD_FETCH_SHIFT 12
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#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
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#define CONCONTROL_AREF_EN_SHIFT 5
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/* PRECHCONFIG register field */
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#define PRECHCONFIG_TP_CNT_SHIFT 24
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/* PWRDNCONFIG register field */
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#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
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#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
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/* PHY_CON0 register fields */
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#define PHY_CON0_T_WRRDCMD_SHIFT 17
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#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
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#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
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#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
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/* PHY_CON1 register fields */
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#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
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/* PHY_CON12 register fields */
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#define PHY_CON12_CTRL_START_POINT_SHIFT 24
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#define PHY_CON12_CTRL_INC_SHIFT 16
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#define PHY_CON12_CTRL_FORCE_SHIFT 8
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#define PHY_CON12_CTRL_START_SHIFT 6
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#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
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#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
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#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
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#define PHY_CON12_CTRL_REF_SHIFT 1
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/* PHY_CON16 register fields */
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#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
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#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
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#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
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#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
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#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
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/* PHY_CON42 register fields */
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#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
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#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
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#define PHY_CON42_CTRL_RDLAT_SHIFT 0
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#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
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#ifndef __ASSEMBLER__
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struct exynos5_dmc {
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unsigned int concontrol;
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unsigned int memcontrol;
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unsigned int memconfig0;
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unsigned int cgcontrol;
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unsigned int memconfig1;
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unsigned int directcmd;
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unsigned int prechconfig;
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unsigned int prechconfig0;
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unsigned int phycontrol0;
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unsigned char res1[0xc];
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unsigned int pwrdnconfig;
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unsigned int prechconfig1;
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unsigned char res1[0x8];
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unsigned int pwrdnconfig; /* 0x0028*/
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unsigned int timingpzq;
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unsigned int timingref;
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unsigned int timingrow;
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@@ -36,12 +87,12 @@ struct exynos5_dmc {
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unsigned int timingpower;
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unsigned int phystatus;
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unsigned char res2[0x4];
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unsigned int chipstatus_ch0;
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unsigned int chipstatus_ch0; /* 0x0048 */
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unsigned int chipstatus_ch1;
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unsigned char res3[0x4];
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unsigned int mrstatus;
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unsigned char res4[0x8];
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unsigned int qoscontrol0;
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unsigned int qoscontrol0; /* 0x0060 */
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unsigned char resr5[0x4];
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unsigned int qoscontrol1;
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unsigned char res6[0x4];
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@@ -72,45 +123,83 @@ struct exynos5_dmc {
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unsigned int qoscontrol14;
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unsigned char res19[0x4];
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unsigned int qoscontrol15;
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unsigned char res20[0x14];
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unsigned char res20[0x4];
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unsigned int timing_set_sw; /* 0x00e0 */
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unsigned int timingrow1;
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unsigned int timingdata1;
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unsigned int timingpower1;
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unsigned int ivcontrol;
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unsigned int wrtra_config;
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unsigned int rdlvl_config;
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unsigned char res21[0x8];
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unsigned char res21[0x4];
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unsigned int brbrsvcontrol; /* 0x0100*/
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unsigned int brbrsvconfig;
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unsigned int brbqosconfig;
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unsigned int membaseconfig0;
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unsigned int membaseconfig1;
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unsigned int membaseconfig1; /* 0x0110 */
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unsigned char res22[0xc];
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unsigned int wrlvl_config;
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unsigned char res23[0xc];
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unsigned int perevcontrol;
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unsigned int wrlvl_config0; /* 0x0120 */
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unsigned int wrlvl_config1;
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unsigned int wrlvl_status;
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unsigned char res23[0x4];
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unsigned int perevcontrol; /* 0x0130 */
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unsigned int perev0config;
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unsigned int perev1config;
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unsigned int perev2config;
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unsigned int perev3config;
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unsigned char res24[0xdebc];
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unsigned int pmnc_ppc_a;
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unsigned char res25[0xc];
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unsigned int cntens_ppc_a;
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unsigned char res26[0xc];
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unsigned int cntenc_ppc_a;
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unsigned char res27[0xc];
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unsigned int intens_ppc_a;
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unsigned char res28[0xc];
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unsigned int intenc_ppc_a;
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unsigned char res29[0xc];
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unsigned int flag_ppc_a;
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unsigned char res30[0xac];
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unsigned int ccnt_ppc_a;
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unsigned char res31[0xc];
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unsigned int pmcnt0_ppc_a;
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unsigned char res22a[0xc];
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unsigned int ctrl_io_rdata_ch0;
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unsigned int ctrl_io_rdata_ch1;
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unsigned char res23a[0x8];
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unsigned int cacal_config0;
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unsigned int cacal_config1;
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unsigned int cacal_status;
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unsigned char res24[0x94];
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unsigned int emergent_config0; /* 0x0200 */
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unsigned int emergent_config1;
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unsigned char res25[0x8];
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unsigned int bp_control0;
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unsigned int bp_control0_r;
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unsigned int bp_control0_w;
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unsigned char res26[0x4];
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unsigned int bp_control1;
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unsigned int bp_control1_r;
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unsigned int bp_control1_w;
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unsigned char res27[0x4];
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unsigned int bp_control2;
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unsigned int bp_control2_r;
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unsigned int bp_control2_w;
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unsigned char res28[0x4];
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unsigned int bp_control3;
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unsigned int bp_control3_r;
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unsigned int bp_control3_w;
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unsigned char res29[0xb4];
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unsigned int winconfig_odt_w; /* 0x0300 */
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unsigned char res30[0x4];
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unsigned int winconfig_ctrl_read;
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unsigned int winconfig_ctrl_gate;
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unsigned char res31[0xdcf0];
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unsigned int pmnc_ppc;
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unsigned char res32[0xc];
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unsigned int pmcnt1_ppc_a;
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unsigned int cntens_ppc;
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unsigned char res33[0xc];
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unsigned int pmcnt2_ppc_a;
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unsigned int cntenc_ppc;
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unsigned char res34[0xc];
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unsigned int pmcnt3_ppc_a;
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unsigned int intens_ppc;
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unsigned char res35[0xc];
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unsigned int intenc_ppc;
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unsigned char res36[0xc];
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unsigned int flag_ppc; /* 0xe050 */
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unsigned char res37[0xac];
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unsigned int ccnt_ppc;
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unsigned char res38[0xc];
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unsigned int pmcnt0_ppc;
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unsigned char res39[0xc];
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unsigned int pmcnt1_ppc;
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unsigned char res40[0xc];
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unsigned int pmcnt2_ppc;
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unsigned char res41[0xc];
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unsigned int pmcnt3_ppc; /* 0xe140 */
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};
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struct exynos5_phy_control {
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@@ -160,6 +249,15 @@ struct exynos5_phy_control {
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unsigned int phy_con42;
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};
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struct exynos5_tzasc {
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unsigned char res1[0xf00];
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unsigned int membaseconfig0;
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unsigned int membaseconfig1;
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unsigned char res2[0x8];
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unsigned int memconfig0;
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unsigned int memconfig1;
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};
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enum ddr_mode {
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DDR_MODE_DDR2,
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DDR_MODE_DDR3,
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@@ -196,54 +294,6 @@ enum {
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MEM_TIMINGS_MSR_COUNT = 4,
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};
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#define DMC_INTERLEAVE_SIZE 0x1f
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/* CONCONTROL register fields */
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#define CONCONTROL_DFI_INIT_START_SHIFT 28
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#define CONCONTROL_RD_FETCH_SHIFT 12
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#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
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#define CONCONTROL_AREF_EN_SHIFT 5
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/* PRECHCONFIG register field */
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#define PRECHCONFIG_TP_CNT_SHIFT 24
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/* PWRDNCONFIG register field */
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#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
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#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
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/* PHY_CON0 register fields */
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#define PHY_CON0_T_WRRDCMD_SHIFT 17
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#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
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#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
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/* PHY_CON1 register fields */
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#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
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/* PHY_CON12 register fields */
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#define PHY_CON12_CTRL_START_POINT_SHIFT 24
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#define PHY_CON12_CTRL_INC_SHIFT 16
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#define PHY_CON12_CTRL_FORCE_SHIFT 8
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#define PHY_CON12_CTRL_START_SHIFT 6
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#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
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#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
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#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
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#define PHY_CON12_CTRL_REF_SHIFT 1
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/* PHY_CON16 register fields */
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#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
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#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
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#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
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#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
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#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
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/* PHY_CON42 register fields */
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#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
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#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
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#define PHY_CON42_CTRL_RDLAT_SHIFT 0
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#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
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/* These are the memory timings for a particular memory type and speed */
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struct mem_timings {
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@@ -23,10 +23,9 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <delay.h>
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#include "setup.h"
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#include "dmc.h"
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#include "clk.h"
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#include "setup.h"
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#include "clk.h"
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#define ZQ_INIT_TIMEOUT 10000
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@@ -173,11 +172,3 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
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}
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}
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void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
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{
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writel(mem->memconfig, &dmc->memconfig0);
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writel(mem->memconfig, &dmc->memconfig1);
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writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
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writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
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}
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@@ -1,11 +1,17 @@
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/*
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* This file is part of the coreboot project.
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*
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* DDR3 mem setup file for EXYNOS5 based board
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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* See file CREDITS for list of people who contributed to this
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* project.
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||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
@@ -14,181 +20,181 @@
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* DDR3 mem setup file for SMDK5420 board based on EXYNOS5 */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <arch/io.h>
|
||||
#include "clk.h"
|
||||
#include "cpu.h"
|
||||
#include "dmc.h"
|
||||
#include "setup.h"
|
||||
#include "cpu.h"
|
||||
#include "clk.h"
|
||||
|
||||
#define RDLVL_COMPLETE_TIMEOUT 10000
|
||||
#define TIMEOUT 10000
|
||||
|
||||
static void reset_phy_ctrl(void)
|
||||
/* 'reset' field is currently ignored. */
|
||||
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
|
||||
{
|
||||
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
|
||||
|
||||
writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
|
||||
writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* For proper memory initialization there should be a minimum delay of
|
||||
* 500us after the LPDDR3PHY_CTRL_PHY_RESET signal.
|
||||
* The below value is an approximate value whose calculation in done
|
||||
* considering that sdelay takes 2 instruction for every 1 delay cycle.
|
||||
* And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec
|
||||
* So for 500 usec, the number of delay cycle should be
|
||||
* (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000
|
||||
*
|
||||
* TODO(hatim.rv@samsung.com): Implement the delay using timer/counter
|
||||
*/
|
||||
sdelay(425000);
|
||||
#endif
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
||||
int mem_reset)
|
||||
{
|
||||
unsigned int val;
|
||||
struct exynos5420_clock *clk =
|
||||
(struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
|
||||
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
|
||||
struct exynos5_dmc *dmc;
|
||||
struct exynos5_dmc *drex0, *drex1;
|
||||
struct exynos5_tzasc *tzasc0, *tzasc1;
|
||||
u32 val, nLockR, nLockW_phy0, nLockW_phy1;
|
||||
int i;
|
||||
|
||||
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
|
||||
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
|
||||
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
|
||||
drex0 = (struct exynos5_dmc *)EXYNOS5420_DMC_DREXI_0;
|
||||
drex1 = (struct exynos5_dmc *)EXYNOS5420_DMC_DREXI_1;
|
||||
tzasc0 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC_0;
|
||||
tzasc1 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC_1;
|
||||
|
||||
if (mem_reset) {
|
||||
printk(BIOS_SPEW, "%s: reset phy: ", __func__);
|
||||
reset_phy_ctrl();
|
||||
printk(BIOS_SPEW, "done\n");
|
||||
} else {
|
||||
printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__);
|
||||
}
|
||||
/* Enable PAUSE for DREX */
|
||||
setbits_le32(&clk->pause, ENABLE_BIT);
|
||||
|
||||
/* Set Impedance Output Driver */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n");
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: mem->impedance 0x%x\n",
|
||||
mem->impedance);
|
||||
val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
|
||||
(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
|
||||
(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
|
||||
(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: val 0x%x\n", val);
|
||||
writel(val, &phy0_ctrl->phy_con39);
|
||||
writel(val, &phy1_ctrl->phy_con39);
|
||||
/* Enable BYPASS mode */
|
||||
setbits_le32(&clk->bpll_con1, BYPASS_EN);
|
||||
|
||||
writel(MUX_BPLL_SEL_FOUTBPLL, &clk->clk_src_cdrex);
|
||||
do {
|
||||
val = readl(&clk->clk_mux_stat_cdrex);
|
||||
val &= BPLL_SEL_MASK;
|
||||
} while (val != FOUTBPLL);
|
||||
|
||||
clrbits_le32(&clk->bpll_con1, BYPASS_EN);
|
||||
|
||||
/* Specify the DDR memory type as DDR3 */
|
||||
val = readl(&phy0_ctrl->phy_con0);
|
||||
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
|
||||
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
|
||||
writel(val, &phy0_ctrl->phy_con0);
|
||||
|
||||
val = readl(&phy1_ctrl->phy_con0);
|
||||
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
|
||||
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
|
||||
writel(val, &phy1_ctrl->phy_con0);
|
||||
|
||||
/* Set Read Latency and Burst Length for PHY0 and PHY1 */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"Set Read Latency and Burst Length for PHY0 and PHY1\n");
|
||||
val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
|
||||
(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
|
||||
writel(val, &phy0_ctrl->phy_con42);
|
||||
writel(val, &phy1_ctrl->phy_con42);
|
||||
|
||||
val = readl(&phy0_ctrl->phy_con26);
|
||||
val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
|
||||
val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
|
||||
writel(val, &phy0_ctrl->phy_con26);
|
||||
|
||||
val = readl(&phy1_ctrl->phy_con26);
|
||||
val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
|
||||
val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
|
||||
writel(val, &phy1_ctrl->phy_con26);
|
||||
|
||||
/* Set Driver strength for CK, CKE, CS & CA to 0x7
|
||||
* Set Driver strength for Data Slice 0~3 to 0x6
|
||||
*/
|
||||
val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
|
||||
(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
|
||||
val |= (0x6 << DA_3_DS_OFFSET) | (0x6 << DA_2_DS_OFFSET) |
|
||||
(0x6 << DA_1_DS_OFFSET) | (0x6 << DA_0_DS_OFFSET);
|
||||
writel(val, &phy0_ctrl->phy_con39);
|
||||
writel(val, &phy1_ctrl->phy_con39);
|
||||
|
||||
/* ZQ Calibration */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: ZQ Calibration\n");
|
||||
if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
|
||||
return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
|
||||
|
||||
clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
|
||||
clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
|
||||
|
||||
/* DQ Signal */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQ Signal\n");
|
||||
writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
|
||||
writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
|
||||
|
||||
writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
|
||||
| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
|
||||
&dmc->concontrol);
|
||||
val = MEM_TERM_EN | PHY_TERM_EN;
|
||||
writel(val, &drex0->phycontrol0);
|
||||
writel(val, &drex1->phycontrol0);
|
||||
|
||||
update_reset_dll(dmc, DDR_MODE_DDR3);
|
||||
writel(mem->concontrol |
|
||||
(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
|
||||
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
|
||||
&drex0->concontrol);
|
||||
writel(mem->concontrol |
|
||||
(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
|
||||
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
|
||||
&drex1->concontrol);
|
||||
|
||||
/* DQS Signal */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQS Signal\n");
|
||||
writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
|
||||
writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
|
||||
do {
|
||||
val = readl(&drex0->phystatus);
|
||||
} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
|
||||
do {
|
||||
val = readl(&drex1->phystatus);
|
||||
} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
|
||||
|
||||
writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
|
||||
writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
|
||||
clrbits_le32(&drex0->concontrol, DFI_INIT_START);
|
||||
clrbits_le32(&drex1->concontrol, DFI_INIT_START);
|
||||
|
||||
writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
|
||||
writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
|
||||
update_reset_dll(drex0, DDR_MODE_DDR3);
|
||||
update_reset_dll(drex1, DDR_MODE_DDR3);
|
||||
|
||||
val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
|
||||
(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
|
||||
(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
|
||||
(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
|
||||
writel(val, &phy0_ctrl->phy_con12);
|
||||
writel(val, &phy1_ctrl->phy_con12);
|
||||
/* Set Base Address:
|
||||
* 0x2000_0000 ~ 0x5FFF_FFFF
|
||||
* 0x6000_0000 ~ 0x9FFF_FFFF
|
||||
*/
|
||||
/* MEMBASECONFIG0 */
|
||||
val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
|
||||
DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
|
||||
writel(val, &tzasc0->membaseconfig0);
|
||||
writel(val, &tzasc1->membaseconfig0);
|
||||
|
||||
/* Start DLL locking */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Start DLL Locking\n");
|
||||
writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
|
||||
&phy0_ctrl->phy_con12);
|
||||
writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
|
||||
&phy1_ctrl->phy_con12);
|
||||
/* MEMBASECONFIG1 */
|
||||
val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
|
||||
DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
|
||||
writel(val, &tzasc0->membaseconfig1);
|
||||
writel(val, &tzasc1->membaseconfig1);
|
||||
|
||||
update_reset_dll(dmc, DDR_MODE_DDR3);
|
||||
|
||||
writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
|
||||
&dmc->concontrol);
|
||||
|
||||
/* Memory Channel Inteleaving Size */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"Memory Channel Inteleaving Size\n");
|
||||
writel(mem->iv_size, &dmc->ivcontrol);
|
||||
|
||||
/* Set DMC MEMCONTROL register */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set DMC MEMCONTROL register\n");
|
||||
val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE;
|
||||
writel(val, &dmc->memcontrol);
|
||||
|
||||
writel(mem->memconfig, &dmc->memconfig0);
|
||||
writel(mem->memconfig, &dmc->memconfig1);
|
||||
writel(mem->membaseconfig0, &dmc->membaseconfig0);
|
||||
writel(mem->membaseconfig1, &dmc->membaseconfig1);
|
||||
/* Memory Channel Inteleaving Size
|
||||
* Exynos5420 Channel interleaving = 128 bytes
|
||||
*/
|
||||
/* MEMCONFIG0/1 */
|
||||
writel(mem->memconfig, &tzasc0->memconfig0);
|
||||
writel(mem->memconfig, &tzasc1->memconfig0);
|
||||
writel(mem->memconfig, &tzasc0->memconfig1);
|
||||
writel(mem->memconfig, &tzasc1->memconfig1);
|
||||
|
||||
/* Precharge Configuration */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Precharge Configuration\n");
|
||||
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
|
||||
&dmc->prechconfig);
|
||||
|
||||
/* Power Down mode Configuration */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"Power Down mode Configuraation\n");
|
||||
writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
|
||||
mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
|
||||
&dmc->pwrdnconfig);
|
||||
&drex0->prechconfig0);
|
||||
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
|
||||
&drex1->prechconfig0);
|
||||
|
||||
/* TimingRow, TimingData, TimingPower and Timingaref
|
||||
* values as per Memory AC parameters
|
||||
*/
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"TimingRow, TimingData, TimingPower and Timingaref\n");
|
||||
writel(mem->timing_ref, &dmc->timingref);
|
||||
writel(mem->timing_row, &dmc->timingrow);
|
||||
writel(mem->timing_data, &dmc->timingdata);
|
||||
writel(mem->timing_power, &dmc->timingpower);
|
||||
|
||||
/* Send PALL command */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n");
|
||||
dmc_config_prech(mem, dmc);
|
||||
writel(mem->timing_ref, &drex0->timingref);
|
||||
writel(mem->timing_ref, &drex1->timingref);
|
||||
writel(mem->timing_row, &drex0->timingrow);
|
||||
writel(mem->timing_row, &drex1->timingrow);
|
||||
writel(mem->timing_data, &drex0->timingdata);
|
||||
writel(mem->timing_data, &drex1->timingdata);
|
||||
writel(mem->timing_power, &drex0->timingpower);
|
||||
writel(mem->timing_power, &drex1->timingpower);
|
||||
|
||||
/* Send NOP, MRS and ZQINIT commands */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send NOP, MRS, and ZQINIT\n");
|
||||
dmc_config_mrs(mem, dmc);
|
||||
dmc_config_mrs(mem, drex0);
|
||||
dmc_config_mrs(mem, drex1);
|
||||
|
||||
if (mem->gate_leveling_enable) {
|
||||
val = PHY_CON0_RESET_VAL;
|
||||
val |= P0_CMD_EN;
|
||||
writel(val, &phy0_ctrl->phy_con0);
|
||||
writel(val, &phy1_ctrl->phy_con0);
|
||||
|
||||
setbits_le32(&phy0_ctrl->phy_con0, CTRL_ATGATE);
|
||||
setbits_le32(&phy1_ctrl->phy_con0, CTRL_ATGATE);
|
||||
|
||||
setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
|
||||
setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
|
||||
|
||||
val = PHY_CON2_RESET_VAL;
|
||||
val |= INIT_DESKEW_EN;
|
||||
@@ -201,38 +207,51 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
||||
writel(val, &phy0_ctrl->phy_con0);
|
||||
writel(val, &phy1_ctrl->phy_con0);
|
||||
|
||||
val = (mem->ctrl_start_point <<
|
||||
PHY_CON12_CTRL_START_POINT_SHIFT) |
|
||||
(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
|
||||
(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
|
||||
(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
|
||||
(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
|
||||
writel(val, &phy0_ctrl->phy_con12);
|
||||
writel(val, &phy1_ctrl->phy_con12);
|
||||
|
||||
val = PHY_CON2_RESET_VAL;
|
||||
val |= INIT_DESKEW_EN;
|
||||
val |= RDLVL_GATE_EN;
|
||||
writel(val, &phy0_ctrl->phy_con2);
|
||||
writel(val, &phy1_ctrl->phy_con2);
|
||||
|
||||
val = PHY_CON0_RESET_VAL;
|
||||
val |= P0_CMD_EN;
|
||||
val |= BYTE_RDLVL_EN;
|
||||
val |= CTRL_SHGATE;
|
||||
writel(val, &phy0_ctrl->phy_con0);
|
||||
writel(val, &phy1_ctrl->phy_con0);
|
||||
|
||||
val = PHY_CON1_RESET_VAL;
|
||||
val &= ~(CTRL_GATEDURADJ_MASK);
|
||||
val = readl(&phy0_ctrl->phy_con1);
|
||||
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
|
||||
writel(val, &phy0_ctrl->phy_con1);
|
||||
|
||||
val = readl(&phy1_ctrl->phy_con1);
|
||||
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
|
||||
writel(val, &phy1_ctrl->phy_con1);
|
||||
|
||||
writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
|
||||
i = RDLVL_COMPLETE_TIMEOUT;
|
||||
while ((readl(&dmc->phystatus) &
|
||||
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
|
||||
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
|
||||
nLockR = readl(&phy0_ctrl->phy_con13);
|
||||
nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2;
|
||||
nLockR = readl(&phy0_ctrl->phy_con12);
|
||||
nLockR &= ~CTRL_DLL_ON;
|
||||
nLockR |= nLockW_phy0;
|
||||
writel(nLockR, &phy0_ctrl->phy_con12);
|
||||
|
||||
nLockR = readl(&phy1_ctrl->phy_con13);
|
||||
nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2;
|
||||
nLockR = readl(&phy1_ctrl->phy_con12);
|
||||
nLockR &= ~CTRL_DLL_ON;
|
||||
nLockR |= nLockW_phy1;
|
||||
writel(nLockR, &phy1_ctrl->phy_con12);
|
||||
|
||||
writel(0x00030004, &drex0->directcmd);
|
||||
writel(0x00130004, &drex0->directcmd);
|
||||
writel(0x00030004, &drex1->directcmd);
|
||||
writel(0x00130004, &drex1->directcmd);
|
||||
|
||||
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
|
||||
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
|
||||
|
||||
setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
|
||||
setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
|
||||
|
||||
val = readl(&phy0_ctrl->phy_con1);
|
||||
val &= ~(CTRL_GATEDURADJ_MASK);
|
||||
writel(val, &phy0_ctrl->phy_con1);
|
||||
|
||||
val = readl(&phy1_ctrl->phy_con1);
|
||||
val &= ~(CTRL_GATEDURADJ_MASK);
|
||||
writel(val, &phy1_ctrl->phy_con1);
|
||||
|
||||
writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
|
||||
i = TIMEOUT;
|
||||
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
|
||||
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
* TODO(waihong): Comment on how long this take to
|
||||
* timeout
|
||||
@@ -240,38 +259,116 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
||||
udelay(1);
|
||||
i--;
|
||||
}
|
||||
if (!i){
|
||||
printk(BIOS_SPEW, "Timeout on RDLVL. No DRAM.\n");
|
||||
if (!i)
|
||||
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
||||
writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
|
||||
|
||||
writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
|
||||
i = TIMEOUT;
|
||||
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
|
||||
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
* TODO(waihong): Comment on how long this take to
|
||||
* timeout
|
||||
*/
|
||||
udelay(1);
|
||||
i--;
|
||||
}
|
||||
writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
|
||||
if (!i)
|
||||
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
||||
writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
|
||||
|
||||
writel(0, &phy0_ctrl->phy_con14);
|
||||
writel(0, &phy1_ctrl->phy_con14);
|
||||
|
||||
val = (mem->ctrl_start_point <<
|
||||
PHY_CON12_CTRL_START_POINT_SHIFT) |
|
||||
(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
|
||||
(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
|
||||
(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
|
||||
(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
|
||||
(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
|
||||
writel(val, &phy0_ctrl->phy_con12);
|
||||
writel(val, &phy1_ctrl->phy_con12);
|
||||
writel(0x00030000, &drex0->directcmd);
|
||||
writel(0x00130000, &drex0->directcmd);
|
||||
writel(0x00030000, &drex1->directcmd);
|
||||
writel(0x00130000, &drex1->directcmd);
|
||||
|
||||
update_reset_dll(dmc, DDR_MODE_DDR3);
|
||||
/* Set Read DQ Calibration */
|
||||
writel(0x00030004, &drex0->directcmd);
|
||||
writel(0x00130004, &drex0->directcmd);
|
||||
writel(0x00030004, &drex1->directcmd);
|
||||
writel(0x00130004, &drex1->directcmd);
|
||||
|
||||
val = readl(&phy0_ctrl->phy_con1);
|
||||
val |= READ_LEVELLING_DDR3;
|
||||
writel(val, &phy0_ctrl->phy_con1);
|
||||
val = readl(&phy1_ctrl->phy_con1);
|
||||
val |= READ_LEVELLING_DDR3;
|
||||
writel(val, &phy1_ctrl->phy_con1);
|
||||
|
||||
val = readl(&phy0_ctrl->phy_con2);
|
||||
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
|
||||
writel(val, &phy0_ctrl->phy_con2);
|
||||
val = readl(&phy1_ctrl->phy_con2);
|
||||
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
|
||||
writel(val, &phy1_ctrl->phy_con2);
|
||||
|
||||
setbits_le32(&drex0->rdlvl_config, CTRL_RDLVL_DATA_ENABLE);
|
||||
i = TIMEOUT;
|
||||
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
|
||||
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
* TODO(waihong): Comment on how long this take to
|
||||
* timeout
|
||||
*/
|
||||
udelay(1);
|
||||
i--;
|
||||
}
|
||||
if (!i)
|
||||
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
||||
clrbits_le32(&drex0->rdlvl_config, CTRL_RDLVL_DATA_ENABLE);
|
||||
|
||||
setbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE);
|
||||
i = TIMEOUT;
|
||||
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
|
||||
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
* TODO(waihong): Comment on how long this take to
|
||||
* timeout
|
||||
*/
|
||||
udelay(1);
|
||||
i--;
|
||||
}
|
||||
if (!i)
|
||||
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
||||
clrbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE);
|
||||
|
||||
writel(0x00030000, &drex0->directcmd);
|
||||
writel(0x00130000, &drex0->directcmd);
|
||||
writel(0x00030000, &drex1->directcmd);
|
||||
writel(0x00130000, &drex1->directcmd);
|
||||
|
||||
update_reset_dll(drex0, DDR_MODE_DDR3);
|
||||
update_reset_dll(drex1, DDR_MODE_DDR3);
|
||||
|
||||
/* Common Settings for Leveling */
|
||||
val = PHY_CON12_RESET_VAL;
|
||||
writel((val + nLockW_phy0), &phy0_ctrl->phy_con12);
|
||||
writel((val + nLockW_phy1), &phy1_ctrl->phy_con12);
|
||||
|
||||
setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
|
||||
setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
|
||||
|
||||
update_reset_dll(drex0, DDR_MODE_DDR3);
|
||||
update_reset_dll(drex1, DDR_MODE_DDR3);
|
||||
}
|
||||
|
||||
/* Send PALL command */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n");
|
||||
dmc_config_prech(mem, dmc);
|
||||
dmc_config_prech(mem, drex0);
|
||||
dmc_config_prech(mem, drex1);
|
||||
|
||||
writel(mem->memcontrol, &dmc->memcontrol);
|
||||
writel(mem->memcontrol, &drex0->memcontrol);
|
||||
writel(mem->memcontrol, &drex1->memcontrol);
|
||||
|
||||
/* Set DMC Concontrol and enable auto-refresh counter */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"Set DMC Concontrol and enable auto-refresh counter\n");
|
||||
writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
|
||||
| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
|
||||
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
|
||||
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
|
||||
&drex0->concontrol);
|
||||
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
|
||||
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
|
||||
&drex1->concontrol);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -23,6 +23,7 @@
|
||||
#include <arch/io.h>
|
||||
#include <arch/hlt.h>
|
||||
#include "cpu.h"
|
||||
#include "dmc.h"
|
||||
#include "power.h"
|
||||
#include "setup.h"
|
||||
#include "sysreg.h"
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/*
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
@@ -27,6 +27,11 @@ enum ddr_mode;
|
||||
struct exynos5_phy_control;
|
||||
|
||||
#define NOT_AVAILABLE 0
|
||||
#define DATA_MASK 0xFFFFF
|
||||
|
||||
#define ENABLE_BIT 0x1
|
||||
#define DISABLE_BIT 0x0
|
||||
#define CA_SWAP_EN (1 << 0)
|
||||
|
||||
/* TZPC : Register Offsets */
|
||||
#define TZPC0_BASE 0x10100000
|
||||
@@ -122,6 +127,7 @@ struct exynos5_phy_control;
|
||||
|
||||
/* MEMCONFIG0 register bit fields */
|
||||
#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
|
||||
#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
|
||||
#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
|
||||
#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
|
||||
#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
|
||||
@@ -201,6 +207,10 @@ struct exynos5_phy_control;
|
||||
|
||||
/* CLK_SRC_CDREX */
|
||||
#define CLK_SRC_CDREX_VAL 0x00000001
|
||||
#define MUX_MCLK_CDR_MSPLL (1 << 4)
|
||||
#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
|
||||
#define BPLL_SEL_MASK 0x7
|
||||
#define FOUTBPLL 2
|
||||
|
||||
/* CLK_DIV_CDREX */
|
||||
#define CLK_DIV_CDREX0_VAL 0x30010100
|
||||
@@ -620,39 +630,177 @@ struct exynos5_phy_control;
|
||||
#define CTRL_SHGATE (1 << 8)
|
||||
|
||||
#define PHY_CON1_RESET_VAL 0x09210100
|
||||
#define RDLVL_PASS_ADJ_VAL 0x6
|
||||
#define RDLVL_PASS_ADJ_OFFSET 16
|
||||
#define CTRL_GATEDURADJ_MASK (0xf << 20)
|
||||
#define READ_LEVELLING_DDR3 0x0100
|
||||
|
||||
#define PHY_CON2_RESET_VAL 0x00010004
|
||||
#define INIT_DESKEW_EN (1 << 6)
|
||||
#define DLL_DESKEW_EN (1 << 12)
|
||||
#define RDLVL_GATE_EN (1 << 24)
|
||||
#define RDLVL_EN (1 << 25)
|
||||
#define RDLVL_INCR_ADJ (0x1 << 16)
|
||||
|
||||
/* DREX_PAUSE */
|
||||
#define DREX_PAUSE_EN (1 << 0)
|
||||
|
||||
#define BYPASS_EN (1 << 22)
|
||||
|
||||
/********-----MEMMORY VAL----------***/
|
||||
#define PHY_CON0_VAL 0x17021A00
|
||||
|
||||
#define PHY_CON12_RESET_VAL 0x10100070
|
||||
#define PHY_CON12_VAL 0x10107F50
|
||||
#define CTRL_START (1 << 6)
|
||||
#define CTRL_DLL_ON (1 << 5)
|
||||
#define CTRL_FORCE_MASK (0x7F << 8)
|
||||
#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
|
||||
|
||||
|
||||
#define CTRL_OFFSETD_RESET_VAL 0x8
|
||||
#define CTRL_OFFSETD_VAL 0x7F
|
||||
|
||||
#define CTRL_OFFSETR0 0x7F
|
||||
#define CTRL_OFFSETR1 0x7F
|
||||
#define CTRL_OFFSETR2 0x7F
|
||||
#define CTRL_OFFSETR3 0x7F
|
||||
#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
|
||||
CTRL_OFFSETR1 << 8 | \
|
||||
CTRL_OFFSETR2 << 16 | \
|
||||
CTRL_OFFSETR3 << 24)
|
||||
#define PHY_CON4_RESET_VAL 0x08080808
|
||||
|
||||
#define CTRL_OFFSETW0 0x7F
|
||||
#define CTRL_OFFSETW1 0x7F
|
||||
#define CTRL_OFFSETW2 0x7F
|
||||
#define CTRL_OFFSETW3 0x7F
|
||||
#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
|
||||
CTRL_OFFSETW1 << 8 | \
|
||||
CTRL_OFFSETW2 << 16 | \
|
||||
CTRL_OFFSETW3 << 24)
|
||||
#define PHY_CON6_RESET_VAL 0x08080808
|
||||
|
||||
#define PHY_CON14_RESET_VAL 0x001F0000
|
||||
#define CTRL_PULLD_DQS 0xF
|
||||
#define CTRL_PULLD_DQS_OFFSET 0
|
||||
|
||||
/*ZQ Configurations */
|
||||
#define PHY_CON16_RESET_VAL 0x08000304
|
||||
|
||||
#define ZQ_CLK_EN (1 << 27)
|
||||
#define ZQ_CLK_DIV_EN (1 << 18)
|
||||
#define ZQ_MANUAL_MODE_OFFSET 2
|
||||
#define ZQ_LONG_CALIBRATION 0x1
|
||||
#define ZQ_MANUAL_STR (1 << 1)
|
||||
#define ZQ_DONE (1 << 0)
|
||||
#define ZQ_MODE_DDS_OFFSET 24
|
||||
|
||||
#define LONG_CALIBRATION (ZQ_LONG_CALIBRATION << ZQ_MANUAL_MODE_OFFSET)
|
||||
|
||||
#define CTRL_RDLVL_GATE_ENABLE 1
|
||||
#define CTRL_RDLVL_GATE_DISABLE 1
|
||||
#define CTRL_RDLVL_GATE_DISABLE 0
|
||||
|
||||
#define CTRL_RDLVL_DATA_ENABLE (1 << 1)
|
||||
/* Direct Command */
|
||||
#define DIRECT_CMD_NOP 0x07000000
|
||||
#define DIRECT_CMD_PALL 0x01000000
|
||||
#define DIRECT_CMD_ZQINIT 0x0a000000
|
||||
#define DIRECT_CMD_CHANNEL_SHIFT 28
|
||||
#define DIRECT_CMD_CHIP_SHIFT 20
|
||||
#define DIRECT_CMD_REFA (5 << 24)
|
||||
#define DIRECT_CMD_MRS1 0x71C00
|
||||
#define DIRECT_CMD_MRS2 0x10BFC
|
||||
#define DIRECT_CMD_MRS3 0x0050C
|
||||
#define DIRECT_CMD_MRS4 0x00868
|
||||
#define DIRECT_CMD_MRS5 0x00C04
|
||||
|
||||
/* Drive Strength */
|
||||
#define IMPEDANCE_48_OHM 4
|
||||
#define IMPEDANCE_40_OHM 5
|
||||
#define IMPEDANCE_34_OHM 6
|
||||
#define IMPEDANCE_30_OHM 7
|
||||
#define PHY_CON39_VAL_48_OHM 0x09240924
|
||||
#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
|
||||
#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
|
||||
#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
|
||||
|
||||
|
||||
#define CTRL_BSTLEN_OFFSET 8
|
||||
#define CTRL_RDLAT_OFFSET 0
|
||||
|
||||
#define CMD_DEFAULT_LPDDR3 0xF
|
||||
#define CMD_DEFUALT_OFFSET 0
|
||||
#define T_WRDATA_EN 0x7
|
||||
#define T_WRDATA_EN_DDR3 0x8
|
||||
#define T_WRDATA_EN_OFFSET 16
|
||||
#define T_WRDATA_EN_MASK 0x1f
|
||||
|
||||
#define PHY_CON31_VAL 0x0C183060
|
||||
#define PHY_CON32_VAL 0x60C18306
|
||||
#define PHY_CON33_VAL 0x00000030
|
||||
|
||||
#define PHY_CON31_RESET_VAL 0x0
|
||||
#define PHY_CON32_RESET_VAL 0x0
|
||||
#define PHY_CON33_RESET_VAL 0x0
|
||||
|
||||
#define SL_DLL_DYN_CON_EN (1 << 1)
|
||||
#define FP_RESYNC (1 << 3)
|
||||
#define CTRL_START (1 << 6)
|
||||
|
||||
#define DMC_AREF_EN (1 << 5)
|
||||
#define DMC_CONCONTROL_EMPTY (1 << 8)
|
||||
#define DFI_INIT_START (1 << 28)
|
||||
|
||||
#define DMC_MEMCONTROL_VAL 0x00312700
|
||||
#define CLK_STOP_EN (1 << 0)
|
||||
#define DPWRDN_EN (1 << 1)
|
||||
#define DSREF_EN (1 << 5)
|
||||
|
||||
/* As we use channel interleaving, therefore value of the base address
|
||||
* register must be set as half of the bus base address
|
||||
* RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
|
||||
* we need to set half 0x10 to the membaseconfigx registers
|
||||
* see exynos5420 UM section 17.17.3.21 for more
|
||||
*/
|
||||
#define DMC_CHIP_BASE_0 0x10
|
||||
#define DMC_CHIP_BASE_1 0x50
|
||||
#define DMC_CHIP_MASK 0x7C0
|
||||
|
||||
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
|
||||
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
|
||||
#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
|
||||
#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
|
||||
#define CHIP_BASE_OFFSET 16
|
||||
|
||||
#define MEMCONFIG_VAL 0x1323
|
||||
#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
|
||||
#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
|
||||
|
||||
#define TIMINGAREF_VAL 0x5d
|
||||
#define TIMINGROW_VAL 0x345A8692
|
||||
#define TIMINGDATA_VAL 0x3630065C
|
||||
#define TIMINGPOWER_VAL 0x50380336
|
||||
#define DFI_INIT_COMPLETE (1 << 3)
|
||||
|
||||
#define BRBRSVCONTROL_VAL 0x00000033
|
||||
#define BRBRSVCONFIG_VAL 0x88778877
|
||||
|
||||
/* DMC PHY Control0 register */
|
||||
#define PHY_CONTROL0_RESET_VAL 0x0
|
||||
#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
|
||||
#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
|
||||
#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
|
||||
#define CTRL_ATGATE (1 << 6)
|
||||
#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
|
||||
|
||||
/* Driver strength for CK, CKE, CS & CA */
|
||||
#define IMP_OUTPUT_DRV_40_OHM 0x5
|
||||
#define IMP_OUTPUT_DRV_30_OHM 0x7
|
||||
#define DA_3_DS_OFFSET 25
|
||||
#define DA_2_DS_OFFSET 22
|
||||
#define DA_1_DS_OFFSET 19
|
||||
#define DA_0_DS_OFFSET 16
|
||||
#define CA_CK_DRVR_DS_OFFSET 9
|
||||
#define CA_CKE_DRVR_DS_OFFSET 6
|
||||
#define CA_CS_DRVR_DS_OFFSET 3
|
||||
@@ -687,8 +835,10 @@ void mem_ctrl_init(void);
|
||||
* @param mem_reset Reset memory during initialization.
|
||||
* @return 0 if ok, SETUP_ERR_... if there is a problem
|
||||
*/
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
||||
int mem_reset);
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset);
|
||||
|
||||
/* Memory variant specific initialization code for LPDDR3 */
|
||||
int lpddr3_mem_ctrl_init(int reset);
|
||||
|
||||
/*
|
||||
* Configure ZQ I/O interface
|
||||
|
||||
Reference in New Issue
Block a user