soc/intel: add IS_ENABLED() around Kconfig symbol references

Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/baytrail/acpi.c

@@ -85,15 +85,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = nc_read_top_of_low_memory();
 
-#if CONFIG_CONSOLE_CBMEM
+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
 
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
 	/* Initialize Verified Boot data */
 	chromeos_init_vboot(&(gnvs->chromeos));
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 #endif

src/soc/intel/baytrail/include/soc/pmc.h

@@ -282,7 +282,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
 void southcluster_log_state(void);
 #else
 static inline void southcluster_log_state(void) {}

src/soc/intel/baytrail/include/soc/ramstage.h

@@ -25,7 +25,7 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
 void baytrail_init_cpus(device_t dev);
 void set_max_freq(void);
 void southcluster_enable_dev(device_t dev);
-#if CONFIG_HAVE_REFCODE_BLOB
+#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
 void baytrail_run_reference_code(void);
 #else
 static inline void baytrail_run_reference_code(void) {}

src/soc/intel/baytrail/include/soc/romstage.h

@@ -41,7 +41,7 @@ void punit_init(void);
 void set_max_freq(void);
 int early_spi_read_wpsr(u8 *sr);
 
-#if CONFIG_ENABLE_BUILTIN_COM1
+#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)
 void byt_config_com1_and_enable(void);
 #else
 static inline void byt_config_com1_and_enable(void) { }

src/soc/intel/baytrail/romstage/raminit.c

@@ -137,7 +137,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 		reset_system();
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 		if (prev_sleep_state == ACPI_S0) {
 			/* Ensure EC is running RO firmware. */
 			google_chromeec_check_ec_image(EC_IMAGE_RO);
@@ -168,7 +168,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	if (prev_sleep_state != ACPI_S3) {
 		cbmem_initialize_empty();
 	} else if (cbmem_initialize()) {
-	#if CONFIG_HAVE_ACPI_RESUME
+	#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
 		/* Failed S3 resume, reset to come up cleanly */
 		reset_system();

src/soc/intel/baytrail/romstage/romstage.c

@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
 #include <elog.h>
@@ -128,7 +128,7 @@ void * asmlinkage romstage_main(unsigned long bist,
 
 	gfx_init();
 
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 	/* Ensure the EC is in the right mode for recovery */
 	google_chromeec_early_init();
 #endif
@@ -221,7 +221,7 @@ void romstage_common(struct romstage_params *params)
 
 	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
 	if (prev_sleep_state != ACPI_S3)
 		boot_count_increment();
 #endif

src/soc/intel/baytrail/smihandler.c

@@ -112,7 +112,7 @@ static void southbridge_smi_sleep(void)
 	/* Do any mainboard sleep handling */
 	mainboard_smi_sleep(slp_typ);
 
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
 	/* Log S3, S4, and S5 entry */
 	if (slp_typ >= ACPI_S3)
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -208,7 +208,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 	return NULL;
 }
 
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
 static void southbridge_smi_gsmi(void)
 {
 	u32 *ret, *param;
@@ -241,7 +241,7 @@ static void finalize(void)
 	}
 	finalize_done = 1;
 
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
 	/* Re-init SPI driver to handle locked BAR */
 	spi_init();
 #endif
@@ -346,7 +346,7 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
 	case ELOG_GSMI_APM_CNT:
 		southbridge_smi_gsmi();
 		break;
@@ -372,7 +372,7 @@ static void southbridge_smi_pm1(void)
 	 */
 	if (pm1_sts & PWRBTN_STS) {
 		// power button pressed
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON);
 #endif
 		disable_pm1_control(-1UL);

src/soc/intel/baytrail/spi.c

@@ -163,7 +163,7 @@ enum {
 	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =	3
 };
 
-#if CONFIG_DEBUG_SPI_FLASH
+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
 
 static u8 readb_(const void *addr)
 {