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intel/i82801ix: new southbridge, ICH9

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Add support for ICH9 southbridge

Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Patrick Georgi
2012-11-06 11:05:09 +01:00
committed by Patrick Georgi
parent 2efc8808b8
commit e72a8a3047
34 changed files with 5954 additions and 0 deletions
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85
src/southbridge/intel/i82801ix/thermal.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 secunet Security Networks AG
* (Written by Nico Huber <nico.huber@secunet.com> for secunet)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801ix.h"
static void thermal_init(struct device *dev)
{
if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0))))
return;
u8 reg8;
u32 reg32;
pci_write_config32(dev, 0x10, DEFAULT_TBAR);
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 | (1 << 1));
write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
write32(DEFAULT_TBAR + 0x44, 0);
write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
write8(DEFAULT_TBAR + 0x41, 0xba);
reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
reg8 = read8(DEFAULT_TBAR + 0x48);
write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
pci_write_config32(dev, 0x10, 0);
}
static void thermal_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations thermal_pci_ops = {
.set_subsystem = thermal_set_subsystem,
};
static struct device_operations device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = thermal_init,
.scan_bus = 0,
.ops_pci = &thermal_pci_ops,
};
static const struct pci_driver ich9_thermal __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x2932,
};