soc/intel/broadwell: Move romstage.c to Haswell

Broadwell no longer has CPU code.

Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/Makefile.inc

@@ -1,4 +1,6 @@
 ramstage-y += haswell_init.c
+
+romstage-y += romstage.c
 romstage-y += ../car/romstage.c
 
 ramstage-y += acpi.c

src/cpu/intel/haswell/romstage.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <cpu/x86/msr.h>
+
+void set_max_freq(void)
+{
+	msr_t msr, perf_ctl, platform_info;
+
+	/* Check for configurable TDP option */
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+
+	if ((platform_info.hi >> 1) & 3) {
+		/* Set to nominal TDP ratio */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = rdmsr(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+
+	perf_ctl.hi = 0;
+	wrmsr(IA32_PERF_CTL, perf_ctl);
+
+	printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
+	       ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}