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soc/intel: skl,cnl,icl: consolidate ebda and memmap

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As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus
move them to common code.

Tested successfully on X11SSM-F

Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2019-10-19 15:17:06 +02:00 committed by Nico Huber
parent 68da45479f
commit e75a64f822
9 changed files with 80 additions and 391 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/cannonlake/Makefile.inc
View File

@ -16,7 +16,6 @@ bootblock-y += pmutil.c
bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/report_platform.c
bootblock-y += gspi.c bootblock-y += gspi.c
bootblock-y += i2c.c bootblock-y += i2c.c
bootblock-y += memmap.c
bootblock-y += spi.c bootblock-y += spi.c
bootblock-y += lpc.c bootblock-y += lpc.c
bootblock-y += p2sb.c bootblock-y += p2sb.c
@ -26,7 +25,6 @@ romstage-y += cnl_memcfg_init.c
romstage-y += gspi.c romstage-y += gspi.c
romstage-y += i2c.c romstage-y += i2c.c
romstage-y += lpc.c romstage-y += lpc.c
romstage-y += memmap.c
romstage-y += pmutil.c romstage-y += pmutil.c
romstage-y += reset.c romstage-y += reset.c
romstage-y += spi.c romstage-y += spi.c
@ -44,7 +42,6 @@ ramstage-y += i2c.c
ramstage-y += lockdown.c ramstage-y += lockdown.c
ramstage-y += lpc.c ramstage-y += lpc.c
ramstage-y += me.c ramstage-y += me.c
ramstage-y += memmap.c
ramstage-y += nhlt.c ramstage-y += nhlt.c
ramstage-y += p2sb.c ramstage-y += p2sb.c
ramstage-y += pmc.c ramstage-y += pmc.c
@ -66,7 +63,6 @@ smm-y += smihandler.c
smm-y += uart.c smm-y += uart.c
smm-y += xhci.c smm-y += xhci.c
postcar-y += memmap.c
postcar-y += pmutil.c postcar-y += pmutil.c
postcar-y += i2c.c postcar-y += i2c.c
postcar-y += gspi.c postcar-y += gspi.c

106
src/soc/intel/cannonlake/memmap.c
View File

@ -1,106 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/romstage.h>
#include <cbmem.h>
#include <fsp/util.h>
#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h>
#include <stdlib.h>
/*
* Fill up memory layout information
*
* Host Memory Map:
*
* +--------------------------+ TOUUD
* | |
* +--------------------------+ 4GiB
* | PCI Address Space |
* +--------------------------+ TOLUD (also maps into MC address space)
* | iGD |
* +--------------------------+ BDSM
* | GTT |
* +--------------------------+ BGSM
* | TSEG |
* +--------------------------+ TSEGMB
* | DMA Protected Region |
* +--------------------------+ DPR
* | PRM (C6DRAM/SGX) |
* +--------------------------+ PRMRR
* | ME Stolen Memory |
* +--------------------------+ ME Stolen
* | PTT |
* +--------------------------+ top_of_ram
* | Reserved - FSP/CBMEM |
* +--------------------------+ TOLUM
* | Usage DRAM |
* +--------------------------+ 0
*
* Some of the base registers above can be equal making the size of those
* regions 0. The reason is because the memory controller internally subtracts
* the base registers from each other to determine sizes of the regions. In
* other words, the memory map is in a fixed order no matter what.
*/
void fill_soc_memmap_ebda(struct ebda_config *cfg)
{
struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum);
cfg->cbmem_top = range_entry_end(&tolum);
}
void cbmem_top_init(void)
{
/* Fill up EBDA area */
fill_ebda_area();
}
/*
* +-------------------------+ Top of RAM (aligned)
* | System Management Mode |
* | code and data | Length: CONFIG_TSEG_SIZE
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
* | Chipset Reserved Memory |
* | |
* +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
* | FSP Reserved Memory |
* | |
* +-------------------------+
* | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
* | |
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
*/
void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
retrieve_ebda_object(&ebda_cfg);
return (void *)(uintptr_t)ebda_cfg.cbmem_top;
}

26
src/soc/intel/common/block/ebda/ebda.c
View File

@ -17,34 +17,14 @@
#include <intelblocks/ebda.h> #include <intelblocks/ebda.h>
#include <string.h> #include <string.h>
/* void initialize_ebda_area(void)
* Mainboard Override function
*
* Mainboard directory may implement below functionality for romstage.
*/
/* Fill up EBDA structure inside Mainboard directory */
__weak void create_mainboard_ebda(struct ebda_config *cfg)
{
/* no-op */
}
static void create_soc_ebda(struct ebda_config *cfg)
{
/* Create EBDA header */
cfg->signature = EBDA_SIGNATURE;
/* Fill up memory layout information */
fill_soc_memmap_ebda(cfg);
}
void fill_ebda_area(void)
{ {
struct ebda_config ebda_cfg; struct ebda_config ebda_cfg;
/* Initialize EBDA area early during romstage. */ /* Initialize EBDA area early during romstage. */
setup_default_ebda(); setup_default_ebda();
create_soc_ebda(&ebda_cfg); ebda_cfg.signature = EBDA_SIGNATURE;
create_mainboard_ebda(&ebda_cfg); fill_memmap_ebda(&ebda_cfg);
write_ebda_data(&ebda_cfg, sizeof(ebda_cfg)); write_ebda_data(&ebda_cfg, sizeof(ebda_cfg));
} }

49
src/soc/intel/common/block/include/intelblocks/ebda.h
View File

@ -16,52 +16,23 @@
#ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H #ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H
#define SOC_INTEL_COMMON_BLOCK_EBDA_H #define SOC_INTEL_COMMON_BLOCK_EBDA_H
#include <soc/ebda.h>
#define EBDA_SIGNATURE 0xebdaebda #define EBDA_SIGNATURE 0xebdaebda
/* /* EBDA structure */
* Mainboard Override function struct ebda_config {
* uint32_t signature; /* EBDA signature */
* Mainboard directory may implement below functionality for romstage. uint32_t cbmem_top; /* coreboot memory start */
*/ };
/* Fill up EBDA structure inside Mainboard directory */ /* Initialize EBDA and store structure into EBDA area */
void create_mainboard_ebda(struct ebda_config *cfg); void initialize_ebda_area(void);
/* /*
* SoC overrides * Fill the ebda object pointed to by cfg. Object will be zero filled
*
* All new SoC must implement below functionality for romstage.
*/
void fill_soc_memmap_ebda(struct ebda_config *cfg);
/*
* API to perform below operation
* 1. Initialize EBDA area
* 2. Fill up EBDA structure inside SOC directory
* 3. Fill up EBDA structure inside Mainboard directory
* 4. Store EBDA structure into EBDA area
*/
void fill_ebda_area(void);
/* Fill the ebda object pointed to by cfg. Object will be zero filled
* if signature check fails. */ * if signature check fails. */
void retrieve_ebda_object(struct ebda_config *cfg); void retrieve_ebda_object(struct ebda_config *cfg);
/* /* API for filling ebda with data in romstage */
* EBDA structure void fill_memmap_ebda(struct ebda_config *cfg);
*
* SOC should implement EBDA structure as per need
* as below.
*
* Note: First 4 bytes should be reserved for signature as
* 0xEBDA
*
* struct ebda_config {
* uint32_t signature;
* <Required variables..>
* };
*/
#endif #endif

67
src/soc/intel/common/block/systemagent/memmap.c
View File

@ -19,15 +19,82 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <fsp/util.h>
#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h> #include <intelblocks/systemagent.h>
#include <stdlib.h> #include <stdlib.h>
/*
* Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs):
*
* +---------------------------+ TOUUD
* | |
* +---------------------------+ TOM (if mem > 4GB)
* | CSME UMA (if mem > 4 GiB) |
* +---------------------------+ TOUUD
* | |
* +---------------------------+ 4GiB
* | PCI Address Space |
* +---------------------------+ TOM (if mem < 4GB)
* | CSME UMA (if mem < 4 GiB) |
* +---------------------------+ TOLUD (also maps into MC address space)
* | iGD / DSM |
* +---------------------------+ BDSM
* | GTT / GSM |
* +---------------------------+ TOLM
* | TSEG |
* +---------------------------+ TSEGMB
* | DMA Protected Region |
* +---------------------------+ DPR
* | PRM (C6DRAM/SGX) |
* +---------------------------+ PRMRR
* | Probeless Trace |
* +---------------------------+ ME Stolen
* | PTT |
* +---------------------------+ TOLUM / top_of_ram / cbmem_top
* | CBMEM Root |
* +---------------------------+
* | FSP Reserved Memory |
* +---------------------------+
* | various CBMEM entries |
* +---------------------------+ top_of_stack (8 byte aligned)
* | stack (CBMEM entry) |
* +---------------------------+ FSP TOLUM
* | |
* +---------------------------+ 0
*/
void smm_region(uintptr_t *start, size_t *size) void smm_region(uintptr_t *start, size_t *size)
{ {
*start = sa_get_tseg_base(); *start = sa_get_tseg_base();
*size = sa_get_tseg_size(); *size = sa_get_tseg_size();
} }
#if CONFIG(SOC_INTEL_COMMON_BLOCK_EBDA)
void fill_memmap_ebda(struct ebda_config *cfg)
{
struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum);
cfg->cbmem_top = range_entry_end(&tolum);
}
void cbmem_top_init(void)
{
/* Initialize EBDA area */
initialize_ebda_area();
}
void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
retrieve_ebda_object(&ebda_cfg);
return (void *)(uintptr_t)ebda_cfg.cbmem_top;
}
#endif
void fill_postcar_frame(struct postcar_frame *pcf) void fill_postcar_frame(struct postcar_frame *pcf)
{ {
uintptr_t top_of_ram; uintptr_t top_of_ram;

5
src/soc/intel/icelake/Makefile.inc
View File

@ -21,12 +21,10 @@ bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/report_platform.c
bootblock-y += espi.c bootblock-y += espi.c
bootblock-y += gpio.c bootblock-y += gpio.c
bootblock-y += memmap.c
bootblock-y += p2sb.c bootblock-y += p2sb.c
romstage-y += espi.c romstage-y += espi.c
romstage-y += gpio.c romstage-y += gpio.c
romstage-y += memmap.c
romstage-y += reset.c romstage-y += reset.c
ramstage-y += acpi.c ramstage-y += acpi.c
@ -39,7 +37,6 @@ ramstage-y += fsp_params.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-y += graphics.c ramstage-y += graphics.c
ramstage-y += lockdown.c ramstage-y += lockdown.c
ramstage-y += memmap.c
ramstage-y += p2sb.c ramstage-y += p2sb.c
ramstage-y += pmc.c ramstage-y += pmc.c
ramstage-y += reset.c ramstage-y += reset.c
@ -54,8 +51,6 @@ smm-y += pmutil.c
smm-y += smihandler.c smm-y += smihandler.c
smm-y += uart.c smm-y += uart.c
postcar-y += memmap.c
CPPFLAGS_common += -I$(src)/soc/intel/icelake CPPFLAGS_common += -I$(src)/soc/intel/icelake
CPPFLAGS_common += -I$(src)/soc/intel/icelake/include CPPFLAGS_common += -I$(src)/soc/intel/icelake/include

105
src/soc/intel/icelake/memmap.c
View File

@ -1,105 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/romstage.h>
#include <cbmem.h>
#include <fsp/util.h>
#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h>
#include <stdlib.h>
/*
* Fill up memory layout information
*
* Host Memory Map:
*
* +--------------------------+ TOUUD
* | |
* +--------------------------+ 4GiB
* | PCI Address Space |
* +--------------------------+ TOLUD (also maps into MC address space)
* | iGD |
* +--------------------------+ BDSM
* | GTT |
* +--------------------------+ BGSM
* | TSEG |
* +--------------------------+ TSEGMB
* | DMA Protected Region |
* +--------------------------+ DPR
* | PRM (C6DRAM/SGX) |
* +--------------------------+ PRMRR
* | ME Stolen Memory |
* +--------------------------+ ME Stolen
* | PTT |
* +--------------------------+ top_of_ram
* | Reserved - FSP/CBMEM |
* +--------------------------+ TOLUM
* | Usage DRAM |
* +--------------------------+ 0
*
* Some of the base registers above can be equal making the size of those
* regions 0. The reason is because the memory controller internally subtracts
* the base registers from each other to determine sizes of the regions. In
* other words, the memory map is in a fixed order no matter what.
*/
void fill_soc_memmap_ebda(struct ebda_config *cfg)
{
struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum);
cfg->cbmem_top = range_entry_end(&tolum);
}
void cbmem_top_init(void)
{
/* Fill up EBDA area */
fill_ebda_area();
}
/*
* +-------------------------+ Top of RAM (aligned)
* | System Management Mode |
* | code and data | Length: CONFIG_TSEG_SIZE
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
* | Chipset Reserved Memory |
* | |
* +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
* | FSP Reserved Memory |
* | |
* +-------------------------+
* | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
* | |
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
*/
void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
retrieve_ebda_object(&ebda_cfg);
return (void *)(uintptr_t)ebda_cfg.cbmem_top;
}

3
src/soc/intel/skylake/Makefile.inc
View File

@ -33,7 +33,6 @@ verstage-y += uart.c
romstage-y += gpio.c romstage-y += gpio.c
romstage-y += gspi.c romstage-y += gspi.c
romstage-y += i2c.c romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += me.c romstage-y += me.c
romstage-y += pmc.c romstage-y += pmc.c
romstage-y += pmutil.c romstage-y += pmutil.c
@ -54,7 +53,6 @@ ramstage-y += irq.c
ramstage-y += lockdown.c ramstage-y += lockdown.c
ramstage-y += lpc.c ramstage-y += lpc.c
ramstage-y += me.c ramstage-y += me.c
ramstage-y += memmap.c
ramstage-y += p2sb.c ramstage-y += p2sb.c
ramstage-y += pmc.c ramstage-y += pmc.c
ramstage-y += pmutil.c ramstage-y += pmutil.c
@ -76,7 +74,6 @@ smm-y += smihandler.c
smm-y += uart.c smm-y += uart.c
smm-y += xhci.c smm-y += xhci.c
postcar-y += memmap.c
postcar-y += gspi.c postcar-y += gspi.c
postcar-y += spi.c postcar-y += spi.c
postcar-y += i2c.c postcar-y += i2c.c

106
src/soc/intel/skylake/memmap.c
View File

@ -1,106 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/romstage.h>
#include <cbmem.h>
#include <fsp/util.h>
#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h>
#include <stdlib.h>
/*
* Fill up memory layout information
*
* Host Memory Map:
*
* +--------------------------+ TOUUD
* | |
* +--------------------------+ 4GiB
* | PCI Address Space |
* +--------------------------+ TOLUD (also maps into MC address space)
* | iGD |
* +--------------------------+ BDSM
* | GTT |
* +--------------------------+ BGSM
* | TSEG |
* +--------------------------+ TSEGMB
* | DMA Protected Region |
* +--------------------------+ DPR
* | PRM (C6DRAM/SGX) |
* +--------------------------+ PRMRR
* | ME Stolen Memory |
* +--------------------------+ ME Stolen
* | PTT |
* +--------------------------+ top_of_ram
* | Reserved - FSP/CBMEM |
* +--------------------------+ TOLUM
* | Usage DRAM |
* +--------------------------+ 0
*
* Some of the base registers above can be equal making the size of those
* regions 0. The reason is because the memory controller internally subtracts
* the base registers from each other to determine sizes of the regions. In
* other words, the memory map is in a fixed order no matter what.
*/
void fill_soc_memmap_ebda(struct ebda_config *cfg)
{
struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum);
cfg->cbmem_top = range_entry_end(&tolum);
}
void cbmem_top_init(void)
{
/* Fill up EBDA area */
fill_ebda_area();
}
/*
* +-------------------------+ Top of RAM (aligned)
* | System Management Mode |
* | code and data | Length: CONFIG_TSEG_SIZE
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
* | Chipset Reserved Memory |
* | |
* +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
* | FSP Reserved Memory |
* | |
* +-------------------------+
* | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
* | |
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
*/
void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
retrieve_ebda_object(&ebda_cfg);
return (void *)(uintptr_t)ebda_cfg.cbmem_top;
}