mb/google/brya: Add new baseboard nissa with variants nivviks and nereid

Add a new baseboard for nissa, an Intel ADL-N based reference design.
Also, add variants for the two reference boards, nivviks and nereid.
This commit is a stub which only adds the minimum code needed for a
successful build.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
     abuild -a -x -c max -p none -t google/brya -b nereid

Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/mainboard/google/brya/Kconfig

@@ -53,12 +53,20 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SPD_CACHE_IN_FMAP
 
+config BOARD_GOOGLE_BASEBOARD_NISSA
+	def_bool n
+	select BOARD_GOOGLE_BRYA_COMMON
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SYSTEM_TYPE_LAPTOP
+
 if BOARD_GOOGLE_BRYA_COMMON
 
 config BASEBOARD_DIR
 	string
 	default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA
 	default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
+	default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -94,6 +102,8 @@ config DRIVER_TPM_I2C_BUS
 	default 0x3 if BOARD_GOOGLE_ANAHERA4ES
 	default 0x3 if BOARD_GOOGLE_VELL
 	default 0x3 if BOARD_GOOGLE_TANIKS
+	default 0x0 if BOARD_GOOGLE_NIVVIKS
+	default 0x0 if BOARD_GOOGLE_NEREID
 
 config DRIVER_TPM_I2C_ADDR
 	hex
@@ -113,6 +123,7 @@ config MAINBOARD_FAMILY
 	string
 	default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA
 	default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK
+	default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
 
 config MAINBOARD_PART_NUMBER
 	default "Brya" if BOARD_GOOGLE_BRYA0
@@ -132,6 +143,8 @@ config MAINBOARD_PART_NUMBER
 	default "Anahera4ES" if BOARD_GOOGLE_ANAHERA4ES
 	default "Vell" if BOARD_GOOGLE_VELL
 	default "Taniks" if BOARD_GOOGLE_TANIKS
+	default "Nivviks" if BOARD_GOOGLE_NIVVIKS
+	default "Nereid" if BOARD_GOOGLE_NEREID
 
 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
@@ -151,6 +164,8 @@ config VARIANT_DIR
 	default "anahera4es" if BOARD_GOOGLE_ANAHERA4ES
 	default "vell" if BOARD_GOOGLE_VELL
 	default "taniks" if BOARD_GOOGLE_TANIKS
+	default "nivviks" if BOARD_GOOGLE_NIVVIKS
+	default "nereid" if BOARD_GOOGLE_NEREID
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC

src/mainboard/google/brya/Kconfig.name

@@ -135,3 +135,11 @@ config BOARD_GOOGLE_TANIKS
 	bool "->  Taniks"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENESYSLOGIC_GL9763E
+
+config BOARD_GOOGLE_NIVVIKS
+	bool "->  Nivviks"
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+
+config BOARD_GOOGLE_NEREID
+	bool "->  Nereid"
+	select BOARD_GOOGLE_BASEBOARD_NISSA

src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc

@@ -0,0 +1,6 @@
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+romstage-y += gpio.c
+
+ramstage-y += gpio.c

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -0,0 +1,4 @@
+chip soc/intel/alderlake
+	device domain 0 on
+	end
+end

src/mainboard/google/brya/variants/baseboard/nissa/gpio.c

@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <types.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* TODO */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* TODO */
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* TODO */
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
+
+const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}

src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+/* TODO: Set the correct values */
+#define MAINBOARD_EC_SCI_EVENTS		0
+#define MAINBOARD_EC_SMI_EVENTS		0
+#define MAINBOARD_EC_S5_WAKE_EVENTS	0
+#define MAINBOARD_EC_S3_WAKE_EVENTS	0
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	0
+#define MAINBOARD_EC_LOG_EVENTS		0
+
+#endif /* __BASEBOARD_EC_H__ */

src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* TODO: Set the correct values */
+#define EC_SCI_GPI		0
+#define GPIO_PCH_WP		0
+#define GPIO_EC_IN_RW		0
+#define GPIO_SLP_S0_GATE	0
+
+#endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/google/brya/variants/baseboard/nissa/memory.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	/* TODO */
+	return NULL;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	/* TODO */
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	/* TODO */
+}

src/mainboard/google/brya/variants/nereid/include/variant/ec.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/brya/variants/nereid/include/variant/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif

src/mainboard/google/brya/variants/nereid/overridetree.cb

@@ -0,0 +1,4 @@
+chip soc/intel/alderlake
+        device domain 0 on
+        end
+end

src/mainboard/google/brya/variants/nivviks/include/variant/ec.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif

src/mainboard/google/brya/variants/nivviks/overridetree.cb

@@ -0,0 +1,4 @@
+chip soc/intel/alderlake
+        device domain 0 on
+        end
+end