soc/intel/meteorlake: Use common CAR API for cache reporting
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/rex platform. Change-Id: Id5ffcab54232294ffa101f975d0ec51ac63f1910 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
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@ -10,6 +10,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <intelblocks/car_lib.h>
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#include <soc/bootblock.h>
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#include <soc/pci_devs.h>
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@ -71,21 +72,6 @@ static inline uint16_t get_dev_id(pci_devfn_t dev)
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return pci_read_config16(dev, PCI_DEVICE_ID);
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}
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static void report_cache_info(void)
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{
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int cache_level = CACHE_L3;
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struct cpu_cache_info info;
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if (!fill_cpu_cache_info(cache_level, &info))
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return;
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printk(BIOS_INFO, "Cache: Level %d: ", cache_level);
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printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n",
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info.num_ways, info.physical_partitions, info.line_size, info.num_sets);
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printk(BIOS_INFO, "Cache size = %zu MiB\n", get_cache_size(&info)/MiB);
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}
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static void report_cpu_info(void)
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{
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u32 i, cpu_id, cpu_feature_flag;
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@ -117,7 +103,7 @@ static void report_cpu_info(void)
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"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
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mode[aes], mode[txt], mode[vt]);
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report_cache_info();
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car_report_cache_info();
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}
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static void report_mch_info(void)
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