soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support

New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.

BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/skylake/chip.h

@@ -199,6 +199,11 @@ struct soc_intel_skylake_config {
 	 */
 	u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
 
+	/*
+	 * Clk source number for Root Port
+	 */
+	u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS];
+
 	/*
 	 * Enable/Disable AER (Advanced Error Reporting) for Root Port
 	 * 0: Disable AER