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soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support

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New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.

BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Divya Chellap
2017-12-19 20:16:50 +05:30
committed by Martin Roth
parent 361d197d77
commit e7fb7ce065
10 changed files with 63 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/intel/skylake/chip_fsp20.c
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@@ -166,6 +166,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(params->PcieRpLtrEnable));
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
* all the enabled PCIe root ports, invalid(0x1F) is set for
* disabled PCIe root ports.
*/
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
if (config->PcieRpClkReqSupport[i])
params->PcieRpClkSrcNumber[i] =
config->PcieRpClkSrcNumber[i];
else
params->PcieRpClkSrcNumber[i] = 0x1F;
}
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));