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soc/intel/baytrail: Retype some pointers

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This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-07-07 17:25:38 +02:00
parent e4109ff54f
commit e80d17f602
4 changed files with 14 additions and 14 deletions
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4
src/soc/intel/baytrail/bootblock/bootblock.c
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@@ -58,8 +58,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */

8
src/soc/intel/baytrail/pmutil.c
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@@ -338,12 +338,12 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}
int rtc_failure(void)

2
src/soc/intel/baytrail/smm.c
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@@ -47,7 +47,7 @@ void smm_southbridge_clear_state(void)
static void smm_southcluster_route_gpios(void)
{
u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];

14
src/soc/intel/baytrail/southcluster.c
View File

@@ -198,8 +198,8 @@ static void sc_init(struct device *dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(struct device *dev)
{
u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t mask = 0;
uint32_t mask2 = 0;
@@ -323,7 +323,7 @@ static inline void set_d3hot_bits(struct device *dev, int offset)
*/
static void hda_work_around(struct device *dev)
{
u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
@@ -542,10 +542,10 @@ int __weak mainboard_get_spi_config(struct spi_config *cfg)
static void finalize_chipset(void *unused)
{
u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS);
u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2);
u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR);
void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS);
void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
u8 *spi = (u8 *)SPI_BASE_ADDRESS;
struct spi_config cfg;