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Enable smbus and fix m.2 clkreqs

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Change-Id: I521a30570efafb528e4d77688677307507f97742
This commit is contained in:
Jeremy Soller
2020-11-10 09:18:47 -07:00
parent 0ecb18229e
commit e82bbc5f2f
2 changed files with 14 additions and 8 deletions
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3
src/mainboard/system76/galp5/devicetree.cb
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@@ -69,6 +69,9 @@ chip soc/intel/tigerlake
# System Agent dynamic frequency support
register "SaGv" = "SaGv_Enabled"
# Enable SMBus
register "SmbusEnable" = "1"
# TCSS USB3
register "TcssXhciEn" = "1"

19
src/mainboard/system76/lemp10/devicetree.cb
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@@ -69,6 +69,9 @@ chip soc/intel/tigerlake
# System Agent dynamic frequency support
register "SaGv" = "SaGv_Enabled"
# Enable SMBus
register "SmbusEnable" = "1"
# TCSS USB3
register "TcssXhciEn" = "1"
@@ -134,14 +137,14 @@ chip soc/intel/tigerlake
# 9 x4 - SSD2
# PCIe clocks:
# 0 - SSD1
# 0 - SSD2 - lines mislabeled SSD1
# 1 - WLAN
# 2 - CARD
# 3 - SSD2
# 3 - SSD1 - lines mislabeled SSD2
# PCIe PEG0 x4, Clock 0 (SSD1)
register "PcieClkSrcUsage[0]" = "0x40"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe PEG0 x4, Clock 3 (SSD1)
register "PcieClkSrcUsage[3]" = "0x40"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port #3 x1, Clock 1 (WLAN)
register "PcieRpEnable[2]" = "1"
@@ -155,11 +158,11 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe root port #9 x4, Clock 3 (SSD2)
# PCIe root port #9 x4, Clock 0 (SSD2)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
# Thermal
# rdmsr --bitfield 31:24 --decimal 0x1A2