soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17

This patch ensures to have Type 17 SMBIOS table for CannonLake Platform.

TEST=Enable to get correct SMBIOS DIMM type information as per
SMBIOS spec 3.1

Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/romstage/romstage.c

@@ -24,14 +24,95 @@
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
+#include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
+#include <string.h>
 #include <timestamp.h>
 
 static struct chipset_power_state power_state CAR_GLOBAL;
 
+#define FSP_SMBIOS_MEMORY_INFO_GUID	\
+{	\
+	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
+	0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
+}
+
+/* Memory Channel Present Status */
+enum {
+	CHANNEL_NOT_PRESENT,
+	CHANNEL_DISABLED,
+	CHANNEL_PRESENT
+};
+
+/* Save the DIMM information for SMBIOS table 17 */
+static void save_dimm_info(void)
+{
+	int channel, dimm, dimm_max, index;
+	size_t hob_size;
+	const CONTROLLER_INFO *ctrlr_info;
+	const CHANNEL_INFO *channel_info;
+	const DIMM_INFO *src_dimm;
+	struct dimm_info *dest_dimm;
+	struct memory_info *mem_info;
+	const MEMORY_INFO_DATA_HOB *memory_info_hob;
+	const uint8_t smbios_memory_info_guid[16] =
+			FSP_SMBIOS_MEMORY_INFO_GUID;
+
+	/* Locate the memory info HOB, presence validated by raminit */
+	memory_info_hob = fsp_find_extension_hob_by_guid(
+						smbios_memory_info_guid,
+						&hob_size);
+	if (memory_info_hob == NULL || hob_size == 0) {
+		printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
+		return;
+	}
+
+	/*
+	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
+	 * table 17
+	 */
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	if (mem_info == NULL) {
+		printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+		return;
+	}
+	memset(mem_info, 0, sizeof(*mem_info));
+
+	/* Describe the first N DIMMs in the system */
+	index = 0;
+	dimm_max = ARRAY_SIZE(mem_info->dimm);
+	ctrlr_info = &memory_info_hob->Controller[0];
+	for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
+		channel_info = &ctrlr_info->ChannelInfo[channel];
+		if (channel_info->Status != CHANNEL_PRESENT)
+			continue;
+		for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
+			src_dimm = &channel_info->DimmInfo[dimm];
+			dest_dimm = &mem_info->dimm[index];
+
+			if (src_dimm->Status != DIMM_PRESENT)
+				continue;
+
+			/* Populate the DIMM information */
+			dimm_info_fill(dest_dimm,
+				src_dimm->DimmCapacity,
+				memory_info_hob->MemoryType,
+				memory_info_hob->ConfiguredMemoryClockSpeed,
+				channel_info->ChannelId,
+				src_dimm->DimmId,
+				(const char *)src_dimm->ModulePartNum,
+				sizeof(src_dimm->ModulePartNum),
+				memory_info_hob->DataWidth);
+			index++;
+		}
+	}
+	mem_info->dimm_cnt = index;
+	printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
 asmlinkage void car_stage_entry(void)
 {
 	bool s3wake;
@@ -49,6 +130,8 @@ asmlinkage void car_stage_entry(void)
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
+	if (!s3wake)
+		save_dimm_info();
 	if (postcar_frame_init(&pcf, 1 * KiB))
 		die("Unable to initialize postcar frame.\n");