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mb/google/dragonegg: Enable trackpad

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BUG=b:112282079
BRANCH=None
TEST=1. run evtest and make sure trackpad shows up in list
2. Able to wake system from S3 using trackpad

Change-Id: I86d6b7815147d558065611604363bb607119c154
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29752
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2018-11-06 15:00:08 +05:30
committed by Patrick Georgi
parent 4f22f2f0e8
commit e911158d3e
2 changed files with 13 additions and 1 deletions
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10
src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
View File

@@ -227,7 +227,15 @@ chip soc/intel/icelake
end end
device pci 14.5 on end # SDCard device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0 device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1 device pci 15.1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)"
register "wake" = "GPE0_DW1_00"
device i2c 15 on end
end
end # I2C #1
device pci 15.2 on end # I2C #2 device pci 15.2 on end # I2C #2
device pci 15.3 on end # I2C #3 device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1

4
src/mainboard/google/dragonegg/variants/baseboard/gpio.c
View File

@@ -37,6 +37,10 @@ static const struct pad_config gpio_table[] = {
/* HP_INT_L */ PAD_CFG_GPI(GPP_C15, NONE, PLTRST), /* HP_INT_L */ PAD_CFG_GPI(GPP_C15, NONE, PLTRST),
/* PCH_DEV_INT_ODL */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* PCH_DEV_INT_ODL */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST),
/* PCH_DEV_RESET_L */ PAD_CFG_GPO(GPP_C23, 0, PLTRST), /* PCH_DEV_RESET_L */ PAD_CFG_GPO(GPP_C23, 0, PLTRST),
/* TRACKPAD_WAKE */ PAD_CFG_GPI_SCI(GPP_D0, NONE, DEEP, EDGE_SINGLE,
INVERT),
/* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D1, NONE, DEEP, EDGE_SINGLE,
INVERT),
/* PCI_NVME_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1), /* PCI_NVME_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1),
/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL, /* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,
INVERT), INVERT),