diff --git a/src/mainboard/system76/adl/ramstage.c b/src/mainboard/system76/adl/ramstage.c
index 86ce82119e..5f829b351e 100644
--- a/src/mainboard/system76/adl/ramstage.c
+++ b/src/mainboard/system76/adl/ramstage.c
@@ -23,6 +23,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
 
 	params->SataPortsSolidStateDrive[1] = 1;
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
 
 static void mainboard_init(void *chip_info)
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
index 9d985630d0..b4106dfb00 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
@@ -18,4 +18,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	// Remap PEG2 as PEG1
 	params->CpuPcieRpFunctionSwap = 1;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
index 0f83461ae4..1623225b3a 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
@@ -15,4 +15,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CpuPcieRpAdvancedErrorReporting[1] = 0;
 	params->CpuPcieRpLtrEnable[1] = 1;
 	params->CpuPcieRpPtmEnabled[1] = 0;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
index 72ad3fc5e7..a4d4b40c87 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
@@ -21,4 +21,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	// Low latency legacy I/O
 	params->PchLegacyIoLowLatency = 1;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }