sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/apollolake: Enable LPC bus interface

Browse Source 
This adds early LPC setup in bootblock (for Chrome EC) as well as
late (ramstage) IO decode/sirq enable.

Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14469
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov
2016-02-05 11:27:44 -08:00
committed by Aaron Durbin
parent f748f83ecb
commit e976bd4469
5 changed files with 123 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
src/soc/intel/apollolake/lpc.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* Copyright (C) 2015-2016 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@ -20,6 +20,46 @@
#include <device/pci_ids.h>
#include <soc/acpi.h>
#include <soc/pci_ids.h>
#include <reg_script.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/lpc.h>
#include "chip.h"
static const struct reg_script lpc_serirq_enable[] = {
/* Setup SERIRQ, enable continuous mode */
REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
#endif
REG_SCRIPT_END
};
static void enable_lpc_decode(struct device *lpc)
{
const struct soc_intel_apollolake_config *config;
if (!lpc || !lpc->chip_info)
return;
config = lpc->chip_info;
/* Enable requested fixed IO decode ranges */
pci_write_config16(lpc, LPC_EN, config->lpc_dec);
/* Enable generic IO decode ranges */
pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec);
}
static void lpc_init(struct device *dev)
{
enable_lpc_decode(dev);
reg_script_run_on_dev(dev, lpc_serirq_enable);
}
static void soc_lpc_add_io_resources(device_t dev)
{
@ -46,6 +86,7 @@ static struct device_operations device_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.write_acpi_tables = southbridge_write_acpi_tables,
.init = &lpc_init
};
static const struct pci_driver soc_lpc __pci_driver = {