apollolake boards: Enable CSE in devicetree

Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.

Calling me_read_config32(offset) function from ramstage:

Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!

With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

src/mainboard/intel/apollolake_rvp/devicetree.cb

@@ -22,6 +22,7 @@ chip soc/intel/apollolake
 		device pci 0d.2 on end	# - SPI
 		device pci 0d.3 on end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
+		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 0

src/mainboard/intel/leafhill/devicetree.cb

@@ -22,6 +22,7 @@ chip soc/intel/apollolake
 		device pci 0d.2 on end	# - SPI
 		device pci 0d.3 on end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
+		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 0

src/mainboard/intel/minnow3/devicetree.cb

@@ -22,6 +22,7 @@ chip soc/intel/apollolake
 		device pci 0d.2 on end	# - SPI
 		device pci 0d.3 on end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
+		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 0