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amdfam10 boards: Use PCI_DEVFN()

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Change-Id: I7b9aeaaa1cfa20efc9d187d91ece4eb9ee659c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2019-01-03 11:38:57 +02:00
parent 646edd18e6
commit e9fc8fd9b6
5 changed files with 30 additions and 30 deletions
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20
src/mainboard/asus/kfsn4-dre/irq_tables.c
View File

@@ -83,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_ck804[0]; pirq->rtr_bus = bus_ck804[0];
pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; pirq->rtr_devfn = PCI_DEVFN(sbdn + 9, 0);
pirq->exclusive_irqs = 0x828; pirq->exclusive_irqs = 0x828;
pirq->rtr_vendor = 0x10de; pirq->rtr_vendor = 0x10de;
pirq->rtr_device = 0x005c; pirq->rtr_device = 0x005c;
@@ -95,26 +95,26 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* Slot1 PCIE 16x */ /* Slot1 PCIE 16x */
write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, write_pirq_info(pirq_info, bus_ck804[1], PCI_DEVFN(0, 0), 0x3, 0xdeb8, 0x4,
0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* Slot2 PCIE 1x */ /* Slot2 PCIE 1x */
write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, write_pirq_info(pirq_info, bus_ck804[2], PCI_DEVFN(0, 0), 0x4, 0xdeb8, 0x1,
0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* Slot3 PCIE 1x */ /* Slot3 PCIE 1x */
write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, write_pirq_info(pirq_info, bus_ck804[3], PCI_DEVFN(0, 0), 0x1, 0xdeb8, 0x2,
0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* Slot4 PCIE 4x */ /* Slot4 PCIE 4x */
write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, write_pirq_info(pirq_info, bus_ck804[4], PCI_DEVFN(0x4, 0), 0x2,
0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
@@ -131,31 +131,31 @@ unsigned long write_pirq_routing_table(unsigned long addr)
} }
/* PCI bridge */ /* PCI bridge */
write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 9, 0), 0x1,
0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* SMBus */ /* SMBus */
write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 1, 0), 0x2,
0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* USB */ /* USB */
write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 2, 0), 0x1,
0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* SATA */ /* SATA */
write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 7, 0), 0x1,
0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
/* SATA */ /* SATA */
write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 8, 0), 0x1,
0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;

10
src/mainboard/msi/ms9652_fam10/irq_tables.c
View File

@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_bus = m->bus_mcp55[0];
pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1); pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0; slot_num = 0;
//pci bridge //pci bridge
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
@@ -99,19 +99,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8,
0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
} }
#if CONFIG_CBB #if CONFIG_CBB
write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2,
0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
if (sysconf.nodes > 32) { if (sysconf.nodes > 32) {
write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8,
0, 0); 0, 0);
pirq_info++; pirq_info++;

10
src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
View File

@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_bus = m->bus_mcp55[0];
pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1); pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0; slot_num = 0;
//pci bridge //pci bridge
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
@@ -99,19 +99,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8,
0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
} }
#if CONFIG_CBB #if CONFIG_CBB
write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2,
0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
if (sysconf.nodes > 32) { if (sysconf.nodes > 32) {
write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8,
0, 0); 0, 0);
pirq_info++; pirq_info++;

10
src/mainboard/supermicro/h8qme_fam10/irq_tables.c
View File

@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_bus = m->bus_mcp55[0];
pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1); pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0; slot_num = 0;
//pci bridge //pci bridge
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
@@ -99,19 +99,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0x4ca0, write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0x4ca0,
0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
} }
#if CONFIG_CBB #if CONFIG_CBB
write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0x4ca0, 0x2, write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0x4ca0, 0x2,
0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
if (sysconf.nodes > 32) { if (sysconf.nodes > 32) {
write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0,
0, 0); 0, 0);
pirq_info++; pirq_info++;

10
src/mainboard/tyan/s2912_fam10/irq_tables.c
View File

@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_bus = m->bus_mcp55[0];
pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1); pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0; slot_num = 0;
//pci bridge //pci bridge
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
@@ -99,19 +99,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8,
0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
} }
#if CONFIG_CBB #if CONFIG_CBB
write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2,
0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; pirq_info++;
slot_num++; slot_num++;
if (sysconf.nodes > 32) { if (sysconf.nodes > 32) {
write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8,
0, 0); 0, 0);
pirq_info++; pirq_info++;