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mb/google/brya/variants/primus: To fine tune WWAN power sequencing

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Follow the spec to correct the WWAN poweron and powerdown sequences. 

BUG=b:195625346
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I232d283a9d6093f5da64fcdce44e5cb640e3df0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58319
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ariel Fang
2021-10-14 14:25:42 +08:00
committed by Felix Held
parent 4afdd693fa
commit e9fcc97697
4 changed files with 26 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/brya/Kconfig.name
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@@ -20,6 +20,7 @@ config BOARD_GOOGLE_PRIMUS
select BOARD_GOOGLE_BASEBOARD_BRYA select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GENESYSLOGIC_GL9755
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select HAVE_WWAN_POWER_SEQUENCE
config BOARD_GOOGLE_GIMBLE config BOARD_GOOGLE_GIMBLE
bool "-> Gimble" bool "-> Gimble"

2
src/mainboard/google/brya/variants/primus/Makefile.inc
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@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

21
src/mainboard/google/brya/variants/primus/gpio.c
View File

@@ -77,6 +77,8 @@ static const struct pad_config override_gpio_table[] = {
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
@@ -98,14 +100,16 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_D11, 1, DEEP), PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* D18 : UART1_TXD ==> SD_PE_RST_L */ /* D18 : UART1_TXD ==> SD_PE_RST_L */
PAD_CFG_GPO(GPP_D18, 0, PLTRST), PAD_CFG_GPO(GPP_D18, 0, PLTRST),
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/
PAD_CFG_GPO(GPP_E0, 0, DEEP), PAD_CFG_GPO(GPP_E0, 0, DEEP),
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_E13, NONE, DEEP), PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E16 : RSVD_TP ==> WWAN_RST_L */ /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/
PAD_CFG_GPO(GPP_E16, 0, DEEP), PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */ /* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_F21, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP), PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
@@ -121,6 +125,13 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_B4, 1, DEEP), PAD_CFG_GPO(GPP_B4, 1, DEEP),
}; };
static const struct pad_config romstage_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
PAD_CFG_GPO(GPP_F21, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)
{ {
*num = ARRAY_SIZE(override_gpio_table); *num = ARRAY_SIZE(override_gpio_table);
@@ -132,3 +143,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table); *num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table; return early_gpio_table;
} }
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

5
src/mainboard/google/brya/variants/primus/include/variant/gpio.h
View File

@@ -4,5 +4,10 @@
#define VARIANT_GPIO_H #define VARIANT_GPIO_H
#include <baseboard/gpio.h> #include <baseboard/gpio.h>
#define WWAN_FCPO GPP_F21
#define WWAN_RST GPP_E16
#define WWAN_PERST GPP_E0
#define T1_OFF_MS 16
#define T2_OFF_MS 2
#endif #endif