soc/amd/cezanne: add partial data fabric setup

I'm not 100% sure yet if this code will be common for all AMD SoCs, so
I'll add a copy for Cezanne for now. This part of the code should
probably be reworked after the initial bringup of Cezanne anyway.

DF MMIO register configuration at the beginning of
data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3       a0        0        0
  4       a3     fed0     fed0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

DF MMIO register configuration at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3     10a3     fed0     fedf
  4       a0        0        0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/chip.c

@@ -2,6 +2,7 @@
 
 #include <device/device.h>
 #include <fsp/api.h>
+#include <soc/data_fabric.h>
 #include <soc/southbridge.h>
 #include <types.h>
 #include "chip.h"
@@ -53,6 +54,8 @@ static void soc_init(void *chip_info)
 {
 	fsp_silicon_init();
 
+	data_fabric_set_mmio_np();
+
 	fch_init(chip_info);
 }