soc/intel/common/acpi: Correct IPC sub command for reading LPM requirement

Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC.

Reference:
https://github.com/otcshare/CCG-ADL-Generic-Full
ClientOneSiliconPkg\Include\Register\PmcRegs.h
#define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2

It is consumed in below.
ClientOneSiliconPkg\IpBlock\Pmc\Library\PeiDxeSmmPmcLib\PmcLib.c

Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Ethan Tsao
2021-10-13 12:37:05 -07:00
committed by Felix Held
parent a1b299cd69
commit eaf71b0778
2 changed files with 3 additions and 1 deletions

View File

@@ -47,7 +47,8 @@ static void read_pmc_lpm_requirements(const struct soc_pmc_lpm *lpm,
const uint32_t offset = lpm->lpm_ipc_offset + const uint32_t offset = lpm->lpm_ipc_offset +
i * lpm->req_reg_stride + i * lpm->req_reg_stride +
j * sizeof(uint32_t); j * sizeof(uint32_t);
const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_RD_PMC_REG, 0, 0); const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_RD_PMC_REG,
PMC_IPC_CMD_SUBCMD_RD_PMC_REG, 0);
struct pmc_ipc_buffer req = {.buf[0] = offset}; struct pmc_ipc_buffer req = {.buf[0] = offset};
struct pmc_ipc_buffer res = {}; struct pmc_ipc_buffer res = {};

View File

@@ -40,6 +40,7 @@
/* IPC command for reading PMC registers */ /* IPC command for reading PMC registers */
#define PMC_IPC_CMD_RD_PMC_REG 0xA0 #define PMC_IPC_CMD_RD_PMC_REG 0xA0
#define PMC_IPC_CMD_SUBCMD_RD_PMC_REG 0x02
/* IPC command to enable/disable PCIe SRCCLK */ /* IPC command to enable/disable PCIe SRCCLK */
#define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC #define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC