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mb/google/brya/var/gimble: Configure Acoustic noise mitigation

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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 16

BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59535
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mark Hsieh
2021-11-22 15:26:15 +08:00
committed by Tim Wawrzynczak
parent ad31061e66
commit eb3260b971
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/google/brya/variants/gimble/overridetree.cb
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@@ -34,6 +34,13 @@ chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"
register "PsysPmax" = "143"
register "TcssAuxOri" = "1"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_16"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_16"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2