mb/*/*: Drop FSP_BAYTRAIL support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Arthur Heymans
committed by
Kyösti Mälkki
Kyösti Mälkki
parent
c2c634a089
commit
eb5147027e
@@ -1,16 +0,0 @@
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if VENDOR_ESD
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choice
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prompt "Mainboard model"
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source "src/mainboard/esd/*/Kconfig.name"
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endchoice
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source "src/mainboard/esd/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "esd"
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endif # VENDOR_ESD
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@@ -1,2 +0,0 @@
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config VENDOR_ESD
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bool "electronic system design"
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@@ -1,64 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_ESD_ATOM15
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_FSP_BAYTRAIL
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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config MAINBOARD_DIR
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string
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default "esd/atom15"
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config MAINBOARD_PART_NUMBER
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string
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default "esd atom15"
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config MAX_CPUS
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int
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default 16
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config FSP_FILE
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string
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default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
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config CBFS_SIZE
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hex
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default 0x00300000
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config ENABLE_FSP_FAST_BOOT
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bool
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depends on HAVE_FSP_BIN
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default y
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config VIRTUAL_ROM_SIZE
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hex
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depends on ENABLE_FSP_FAST_BOOT
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default 0x800000
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config POST_DEVICE
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bool
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default n
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config VGA_BIOS
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bool
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default y if FSP_PACKAGE_DEFAULT
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endif # BOARD_ESD_ATOM15
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@@ -1,2 +0,0 @@
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config BOARD_ESD_ATOM15
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bool "Atom15"
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@@ -1,17 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-y += gpio.c
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ramstage-y += irqroute.c
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@@ -1,20 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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@@ -1,48 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/acpi.h>
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#include <soc/nvs.h>
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#include <soc/iomap.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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acpi_init_gnvs(gnvs);
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/* No TPM Present */
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gnvs->tpmp = 0;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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current = acpi_madt_irq_overrides(current);
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return current;
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}
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@@ -1,4 +0,0 @@
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Category: sbc
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ROM protocol: SPI
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Flashrom support: y
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Release year: 2015
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@@ -1,108 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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411 2 e 8 use_xhci_over_ehci
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#413 3 r 0 unused
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# MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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#save timestamps in pre-ram boot areas
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1720 64 h 0 timestamp_value1
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1784 64 h 0 timestamp_value2
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1848 64 h 0 timestamp_value3
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1912 64 h 0 timestamp_value4
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1976 64 h 0 timestamp_value5
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 EHCI
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8 1 XHCI
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8 2 Default
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@@ -1,93 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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|
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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|
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/fsp_baytrail
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#### ACPI Register Settings ####
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register "fadt_pm_profile" = "PM_UNSPECIFIED"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
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#### FSP register settings ####
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register "PcdSataMode" = "SATA_MODE_AHCI"
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register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
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register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
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register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
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register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
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register "PcdGttSize" = "GTT_SIZE_DEFAULT"
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
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register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
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register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
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register "DRAMType" = "DRAM_TYPE_DDR3L"
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register "DIMM0Enable" = "DIMM0_ENABLE"
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register "DIMM1Enable" = "DIMM1_DISABLE"
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register "DIMMDWidth" = "DIMM_DWIDTH_X16"
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register "DIMMDensity" = "DIMM_DENSITY_4G_BIT"
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register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
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||||||
register "DIMMSides" = "DIMM_SIDES_1RANK"
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||||||
register "DIMMtCL" = "8"
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|
||||||
register "DIMMtRPtRCD" = "8"
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|
||||||
register "DIMMtWR" = "8"
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|
||||||
register "DIMMtWTR" = "4"
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|
||||||
register "DIMMtRRD" = "6"
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|
||||||
register "DIMMtRTP" = "4"
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|
||||||
register "DIMMtFAW" = "27"
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|
||||||
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|
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device cpu_cluster 0 on
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|
||||||
device lapic 0 on end
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|
||||||
end
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|
||||||
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|
||||||
device domain 0 on
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|
||||||
device pci 00.0 on end # 8086 0F00 - SoC router -
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|
||||||
device pci 02.0 off end # 8086 0F31 - GFX -
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|
||||||
device pci 03.0 off end # 8086 0F38 - MIPI -
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|
||||||
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|
||||||
device pci 10.0 off end # 8086 0F14 - EMMC Port -
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|
||||||
device pci 11.0 off end # 8086 0F15 - SDIO Port -
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|
||||||
device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
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|
||||||
device pci 13.0 off end # 8086 0F23 - SATA AHCI -
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|
||||||
device pci 14.0 off end # 8086 0F35 - USB XHCI -
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|
||||||
device pci 15.0 off end # 8086 0F28 - LP Engine Audio -
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|
||||||
device pci 17.0 off end # 8086 0F50 - MMC Port -
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|
||||||
device pci 18.0 on end # 8086 0F40 - SIO - DMA -
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|
||||||
device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) -
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|
||||||
device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) -
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|
||||||
device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) -
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|
||||||
device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) -
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|
||||||
device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) -
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|
||||||
device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) EEPROM
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|
||||||
device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) -
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|
||||||
device pci 1a.0 off end # 8086 0F18 - TXE -
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|
||||||
device pci 1b.0 off end # 8086 0F04 - HD Audio -
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|
||||||
device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) -
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|
||||||
device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) -
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|
||||||
device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET
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|
||||||
device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN
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|
||||||
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI -
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|
||||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
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|
||||||
device pci 1e.1 on end # 8086 0F08 - PWM 1 -
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|
||||||
device pci 1e.2 on end # 8086 0F09 - PWM 2 -
|
|
||||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart
|
|
||||||
device pci 1e.4 off end # 8086 0F0C - HSUART 2 -
|
|
||||||
device pci 1e.5 off end # 8086 0F0E - SPI -
|
|
||||||
device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
|
|
||||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,54 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INCLUDE_LPE 1
|
|
||||||
#define INCLUDE_SCC 1
|
|
||||||
#define INCLUDE_EHCI 1
|
|
||||||
#define INCLUDE_XHCI 1
|
|
||||||
#define INCLUDE_LPSS 1
|
|
||||||
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20110725 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Some generic macros
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
|
||||||
|
|
||||||
// global NVS and variables
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
|
||||||
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Chipset specific sleep states */
|
|
||||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
|
|
||||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
|
||||||
{
|
|
||||||
acpi_header_t *header = &(fadt->header);
|
|
||||||
|
|
||||||
acpi_fill_in_fadt(fadt,facs,dsdt);
|
|
||||||
|
|
||||||
/* Platform specific customizations go here */
|
|
||||||
|
|
||||||
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
|
||||||
}
|
|
||||||
@@ -1,231 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For multiplexed functions, look in EDS:
|
|
||||||
* 10.3 Ball Name and Function by Location
|
|
||||||
*
|
|
||||||
* The pads list is in the BWG_VOL2 Rev1p2:
|
|
||||||
* Note that Pad # is not the same as GPIO#
|
|
||||||
* 37 GPIO Handling:
|
|
||||||
* Table 37-1. SCORE Pads List
|
|
||||||
* Table 37-2. SSUSORE Pads List
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* NCORE GPIOs */
|
|
||||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[03] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[04] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[05] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[06] - No Connect */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[08] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[09] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[10] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[11] - No Connect */
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[13] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[14] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[15] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[16] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[17] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[18] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[19] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[20] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[21] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[22] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[23] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[24] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[25] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_NC[26] - No Connect */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SCORE GPIOs (GPIO_S0_SC_XX)*/
|
|
||||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[008] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[009] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[010] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[011] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[012] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[013] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[014] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[015] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[016] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[017] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[018] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[019] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[020] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[021] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[022] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[023] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[024] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[025] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[026] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[027] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[028] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[029] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[030] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[031] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[032] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[040] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[041] - /SD3_PWREN */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[042] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[043] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[044] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[045] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[046] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[047] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[048] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[049] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[050] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[055] - No Connect */
|
|
||||||
GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[058] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[059] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[060] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[072] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[073] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[074] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[075] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[076] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[077] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[078] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[079] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[080] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[081] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[082] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[083] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[084] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[085] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[086] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[087] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[088] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[089] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[096] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[097] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[098] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[099] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[100] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[101] - No Connect */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SSUS GPIOs (GPIO_S5) */
|
|
||||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
|
||||||
GPIO_NC, /* GPIO_S5[00] - No Connect */
|
|
||||||
GPIO_FUNC6, /* GPIO_S5[01] - PMC_WAKE_PCIE[1] */
|
|
||||||
GPIO_FUNC6, /* GPIO_S5[02] - PMC_WAKE_PCIE[2] */
|
|
||||||
GPIO_FUNC6, /* GPIO_S5[03] - PMC_WAKE_PCIE[3] */
|
|
||||||
GPIO_NC, /* GPIO_S5[04] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[05] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[06] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[07] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[08] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[09] - No Connect */
|
|
||||||
GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */
|
|
||||||
GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK */
|
|
||||||
GPIO_NC, /* GPIO_S5[12] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[13] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */
|
|
||||||
GPIO_FUNC0, /* GPIO_S5[15] - PMC_WAKE_PCIE[0] */
|
|
||||||
GPIO_FUNC(1, PULL_UP, 2K), /* GPIO_S5[16] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[17] - No Connect */
|
|
||||||
GPIO_FUNC1, /* GPIO_S5[18] - T360 */
|
|
||||||
GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */
|
|
||||||
GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */
|
|
||||||
GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */
|
|
||||||
GPIO_NC, /* GPIO_S5[22] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[23] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[24] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[25] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[26] - No Connect */
|
|
||||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - SW450-1 */
|
|
||||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - SW450-2 */
|
|
||||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - SW450-3 */
|
|
||||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - SW450-4 */
|
|
||||||
GPIO_NC, /* GPIO_S5[31] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[32] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[33] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[34] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[35] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[36] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[37] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[38] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[39] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[40] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[41] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[42] - No Connect */
|
|
||||||
GPIO_NC, /* GPIO_S5[43] - No Connect */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct soc_gpio_config gpio_config = {
|
|
||||||
.ncore = gpncore_gpio_map,
|
|
||||||
.score = gpscore_gpio_map,
|
|
||||||
.ssus = gpssus_gpio_map,
|
|
||||||
.core_dirq = NULL,
|
|
||||||
.sus_dirq = NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct soc_gpio_config* mainboard_get_gpios(void)
|
|
||||||
{
|
|
||||||
return &gpio_config;
|
|
||||||
}
|
|
||||||
@@ -1,18 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
DEFINE_IRQ_ROUTES;
|
|
||||||
@@ -1,82 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef IRQROUTE_H
|
|
||||||
#define IRQROUTE_H
|
|
||||||
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/irq.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
*IR02h GFX INT(A) - PIRQ A
|
|
||||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
|
||||||
*IR11h SDIO INT(A) - PIRQ B
|
|
||||||
*IR12h SD INT(A) - PIRQ C
|
|
||||||
*IR13h SATA INT(A) - PIRQ D
|
|
||||||
*IR14h XHCI INT(A) - PIRQ E
|
|
||||||
*IR15h LP Audio INT(A) - PIRQ F
|
|
||||||
*IR17h MMC INT(A) - PIRQ F
|
|
||||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
|
||||||
*IR1Ah TXE INT(A) - PIRQ F
|
|
||||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
|
||||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
|
||||||
*IR1Dh EHCI INT(A) - PIRQ D
|
|
||||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
|
||||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCIe bridge routing */
|
|
||||||
#define BRIDGE1_DEV PCIE_DEV
|
|
||||||
|
|
||||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
|
||||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
|
||||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
|
||||||
|
|
||||||
#define PCI_DEV_PIRQ_ROUTES \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
|
||||||
* Reserved: 0, 1, 2, 8, 13
|
|
||||||
* PS2 keyboard: 12
|
|
||||||
* ACPI/SCI: 9
|
|
||||||
* Floppy: 6
|
|
||||||
*/
|
|
||||||
#define PIRQ_PIC_ROUTES \
|
|
||||||
PIRQ_PIC(A, 3), \
|
|
||||||
PIRQ_PIC(B, 5), \
|
|
||||||
PIRQ_PIC(C, 7), \
|
|
||||||
PIRQ_PIC(D, 10), \
|
|
||||||
PIRQ_PIC(E, 11), \
|
|
||||||
PIRQ_PIC(F, 12), \
|
|
||||||
PIRQ_PIC(G, 14), \
|
|
||||||
PIRQ_PIC(H, 15)
|
|
||||||
|
|
||||||
#endif /* IRQROUTE_H */
|
|
||||||
@@ -1,41 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/device.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
|
||||||
* This is the earliest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_final is executed as one of the last items before loading the
|
|
||||||
* payload.
|
|
||||||
*
|
|
||||||
* This is the latest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_final(void *chip_info)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
.final = mainboard_final,
|
|
||||||
};
|
|
||||||
@@ -1,78 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2014 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
|
||||||
#include <pc80/mc146818rtc.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/chip.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done before fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void early_mainboard_romstage_entry()
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get function disables - most of these will be done automatically
|
|
||||||
* @param fd_mask
|
|
||||||
* @param fd2_mask
|
|
||||||
*/
|
|
||||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done after fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void late_mainboard_romstage_entry()
|
|
||||||
{
|
|
||||||
|
|
||||||
configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
|
||||||
configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
|
||||||
configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
|
||||||
configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
|
||||||
|
|
||||||
printk(0, "SW450: %d %d %d %d\n",
|
|
||||||
read_ssus_gpio(27),
|
|
||||||
read_ssus_gpio(28),
|
|
||||||
read_ssus_gpio(29),
|
|
||||||
read_ssus_gpio(30));
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
|
||||||
{
|
|
||||||
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
|
|
||||||
u8 use_xhci = UpdData->PcdEnableXhci;
|
|
||||||
|
|
||||||
/* Update XHCI UPD value if required */
|
|
||||||
get_option(&use_xhci, "use_xhci_over_ehci");
|
|
||||||
if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
|
|
||||||
UpdData->PcdEnableXhci = use_xhci;
|
|
||||||
printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
|
|
||||||
UpdData->PcdEnableXhci?"Enabled":"Disabled");
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
@@ -1,67 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
if BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP
|
|
||||||
|
|
||||||
config BOARD_SPECIFIC_OPTIONS
|
|
||||||
def_bool y
|
|
||||||
select SOC_INTEL_FSP_BAYTRAIL
|
|
||||||
select BOARD_ROMSIZE_KB_2048
|
|
||||||
select HAVE_ACPI_TABLES
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
|
|
||||||
select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default "intel/bayleybay_fsp"
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "Bakersport CRB (FSP)" if BOARD_INTEL_BAKERSPORT_FSP
|
|
||||||
default "Bayley Bay CRB (FSP)"
|
|
||||||
|
|
||||||
config MAX_CPUS
|
|
||||||
int
|
|
||||||
default 16
|
|
||||||
|
|
||||||
config FSP_FILE
|
|
||||||
string
|
|
||||||
default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
|
|
||||||
default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
|
|
||||||
|
|
||||||
config CBFS_SIZE
|
|
||||||
hex
|
|
||||||
default 0x00200000
|
|
||||||
|
|
||||||
config ENABLE_FSP_FAST_BOOT
|
|
||||||
bool
|
|
||||||
depends on HAVE_FSP_BIN
|
|
||||||
default y
|
|
||||||
|
|
||||||
config VIRTUAL_ROM_SIZE
|
|
||||||
hex
|
|
||||||
depends on ENABLE_FSP_FAST_BOOT
|
|
||||||
default 0x800000
|
|
||||||
|
|
||||||
config FSP_PACKAGE_DEFAULT
|
|
||||||
bool "Configure defaults for the Intel FSP package"
|
|
||||||
default n
|
|
||||||
|
|
||||||
config VGA_BIOS
|
|
||||||
bool
|
|
||||||
default y if FSP_PACKAGE_DEFAULT
|
|
||||||
|
|
||||||
endif # BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP
|
|
||||||
@@ -1,5 +0,0 @@
|
|||||||
config BOARD_INTEL_BAKERSPORT_FSP
|
|
||||||
bool "Bakersport FSP-based CRB"
|
|
||||||
|
|
||||||
config BOARD_INTEL_BAYLEYBAY_FSP
|
|
||||||
bool "Bayley Bay FSP-based CRB"
|
|
||||||
@@ -1,17 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013 Google Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
ramstage-y += gpio.c
|
|
||||||
ramstage-y += irqroute.c
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; version 2 of
|
|
||||||
* the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
Device (PWRB)
|
|
||||||
{
|
|
||||||
Name(_HID, EisaId("PNP0C0C"))
|
|
||||||
}
|
|
||||||
@@ -1,58 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Google Inc.
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <types.h>
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <arch/ioapic.h>
|
|
||||||
#include <arch/smp/mpspec.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
#include <soc/nvs.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
|
|
||||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
|
||||||
{
|
|
||||||
acpi_init_gnvs(gnvs);
|
|
||||||
|
|
||||||
/* Enable USB ports in S3 */
|
|
||||||
gnvs->s3u0 = 1;
|
|
||||||
gnvs->s3u1 = 1;
|
|
||||||
|
|
||||||
/* Disable USB ports in S5 */
|
|
||||||
gnvs->s5u0 = 0;
|
|
||||||
gnvs->s5u1 = 0;
|
|
||||||
|
|
||||||
/* TPM Present */
|
|
||||||
gnvs->tpmp = 0;
|
|
||||||
|
|
||||||
/* Enable DPTF */
|
|
||||||
gnvs->dpte = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long acpi_fill_madt(unsigned long current)
|
|
||||||
{
|
|
||||||
/* Local APICs */
|
|
||||||
current = acpi_create_madt_lapics(current);
|
|
||||||
|
|
||||||
/* IOAPIC */
|
|
||||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
|
||||||
2, IO_APIC_ADDR, 0);
|
|
||||||
|
|
||||||
current = acpi_madt_irq_overrides(current);
|
|
||||||
|
|
||||||
return current;
|
|
||||||
}
|
|
||||||
@@ -1,5 +0,0 @@
|
|||||||
Board name: Bayley Bay
|
|
||||||
Category: eval
|
|
||||||
ROM protocol: SPI
|
|
||||||
ROM socketed: n
|
|
||||||
Release year: 2014
|
|
||||||
@@ -1,37 +0,0 @@
|
|||||||
FLASH@0xff800000 0x800000 {
|
|
||||||
SI_ALL@0x0 0x300000 {
|
|
||||||
SI_DESC@0x0 0x1000
|
|
||||||
SI_ME@0x1000 0x2ff000
|
|
||||||
}
|
|
||||||
SI_BIOS@0x300000 0x500000 {
|
|
||||||
RW_SECTION_A@0x0 0xf0000 {
|
|
||||||
VBLOCK_A@0x0 0x10000
|
|
||||||
FW_MAIN_A(CBFS)@0x10000 0xc0000
|
|
||||||
RW_FWID_A@0xeffc0 0x40
|
|
||||||
}
|
|
||||||
RW_SECTION_B@0xf0000 0xf0000 {
|
|
||||||
VBLOCK_B@0x0 0x10000
|
|
||||||
FW_MAIN_B(CBFS)@0x10000 0xc0000
|
|
||||||
RW_FWID_B@0xeffc0 0x40
|
|
||||||
}
|
|
||||||
RW_MRC_CACHE@0x1e0000 0x10000
|
|
||||||
RW_ELOG(PRESERVE)@0x1f0000 0x4000
|
|
||||||
RW_SHARED@0x1f4000 0x4000 {
|
|
||||||
SHARED_DATA@0x0 0x2000
|
|
||||||
VBLOCK_DEV@0x2000 0x2000
|
|
||||||
}
|
|
||||||
RW_VPD(PRESERVE)@0x1f8000 0x2000
|
|
||||||
RW_UNUSED@0x1fa000 0x106000
|
|
||||||
WP_RO@0x300000 0x200000 {
|
|
||||||
RO_VPD(PRESERVE)@0x0 0x4000
|
|
||||||
RO_UNUSED@0x4000 0xc000
|
|
||||||
RO_SECTION@0x10000 0x1f0000 {
|
|
||||||
FMAP@0x0 0x800
|
|
||||||
RO_FRID@0x800 0x40
|
|
||||||
RO_FRID_PAD@0x840 0x7c0
|
|
||||||
GBB@0x1000 0xef000
|
|
||||||
COREBOOT(CBFS)@0xf0000 0x100000
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,97 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2007-2008 coresystems GmbH
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
entries
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register A
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register B
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register C
|
|
||||||
#96 4 r 0 status_c_rsvd
|
|
||||||
#100 1 r 0 uf_flag
|
|
||||||
#101 1 r 0 af_flag
|
|
||||||
#102 1 r 0 pf_flag
|
|
||||||
#103 1 r 0 irqf_flag
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register D
|
|
||||||
#104 7 r 0 status_d_rsvd
|
|
||||||
#111 1 r 0 valid_cmos_ram
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Diagnostic Status Register
|
|
||||||
#112 8 r 0 diag_rsvd1
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
0 120 r 0 reserved_memory
|
|
||||||
#120 264 r 0 unused
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
388 4 h 0 reboot_counter
|
|
||||||
#390 2 r 0 unused?
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# coreboot config options: console
|
|
||||||
#392 3 r 0 unused
|
|
||||||
395 4 e 6 debug_level
|
|
||||||
#399 1 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: cpu
|
|
||||||
400 1 e 2 hyper_threading
|
|
||||||
#401 7 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
|
||||||
408 1 e 1 nmi
|
|
||||||
409 2 e 7 power_on_after_fail
|
|
||||||
#411 5 r 0 unused
|
|
||||||
|
|
||||||
# MRC Scrambler Seed values
|
|
||||||
896 32 r 0 mrc_scrambler_seed
|
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
#1000 24 r 0 amd_reserved
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 0 Emergency
|
|
||||||
6 1 Alert
|
|
||||||
6 2 Critical
|
|
||||||
6 3 Error
|
|
||||||
6 4 Warning
|
|
||||||
6 5 Notice
|
|
||||||
6 6 Info
|
|
||||||
6 7 Debug
|
|
||||||
6 8 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 415 984
|
|
||||||
@@ -1,76 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
chip soc/intel/fsp_baytrail
|
|
||||||
|
|
||||||
#### ACPI Register Settings ####
|
|
||||||
register "fadt_pm_profile" = "PM_MOBILE"
|
|
||||||
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
|
|
||||||
|
|
||||||
#### FSP register settings ####
|
|
||||||
register "PcdSataMode" = "SATA_MODE_AHCI"
|
|
||||||
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
|
|
||||||
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
|
|
||||||
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
|
|
||||||
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
|
|
||||||
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
|
|
||||||
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
|
|
||||||
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
|
|
||||||
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
|
|
||||||
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
|
|
||||||
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
|
|
||||||
|
|
||||||
device cpu_cluster 0 on
|
|
||||||
device lapic 0 on end
|
|
||||||
end
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
device pci 00.0 on end # 8086 0F00 - SoC router
|
|
||||||
device pci 02.0 on end # 8086 0F31 - GFX
|
|
||||||
device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
|
|
||||||
|
|
||||||
device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
|
|
||||||
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
|
|
||||||
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
|
|
||||||
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
|
|
||||||
device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
|
|
||||||
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
|
|
||||||
device pci 16.0 off end # 8086 0F37 - OTG controller
|
|
||||||
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
|
|
||||||
device pci 18.0 on end # 8086 0F40 - SIO - DMA
|
|
||||||
device pci 18.1 on end # 8086 0F41 - I2C Port 1
|
|
||||||
device pci 18.2 on end # 8086 0F42 - I2C Port 2
|
|
||||||
device pci 18.3 on end # 8086 0F43 - I2C Port 3
|
|
||||||
device pci 18.4 on end # 8086 0F44 - I2C Port 4
|
|
||||||
device pci 18.5 on end # 8086 0F45 - I2C Port 5
|
|
||||||
device pci 18.6 on end # 8086 0F46 - I2C Port 6
|
|
||||||
device pci 18.7 on end # 8086 0F47 - I2C Port 7
|
|
||||||
device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
|
|
||||||
device pci 1b.0 on end # 8086 0F04 - HD Audio
|
|
||||||
device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot)
|
|
||||||
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
|
|
||||||
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
|
|
||||||
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
|
|
||||||
device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
|
|
||||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
|
|
||||||
device pci 1e.1 on end # 8086 0F08 - PWM 1
|
|
||||||
device pci 1e.2 on end # 8086 0F09 - PWM 2
|
|
||||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1
|
|
||||||
device pci 1e.4 on end # 8086 0F0C - HSUART 2
|
|
||||||
device pci 1e.5 on end # 8086 0F0E - SPI
|
|
||||||
device pci 1f.0 on end # 8086 0F1C - LPC bridge
|
|
||||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,54 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INCLUDE_LPE 1
|
|
||||||
#define INCLUDE_SCC 1
|
|
||||||
#define INCLUDE_EHCI 1
|
|
||||||
#define INCLUDE_XHCI 1
|
|
||||||
#define INCLUDE_LPSS 1
|
|
||||||
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20110725 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Some generic macros
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
|
||||||
|
|
||||||
// global NVS and variables
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
|
||||||
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Chipset specific sleep states */
|
|
||||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
|
|
||||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
|
||||||
{
|
|
||||||
acpi_header_t *header = &(fadt->header);
|
|
||||||
|
|
||||||
acpi_fill_in_fadt(fadt,facs,dsdt);
|
|
||||||
|
|
||||||
/* Platform specific customizations go here */
|
|
||||||
|
|
||||||
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
|
||||||
}
|
|
||||||
@@ -1,220 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
/* NCORE GPIOs */
|
|
||||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
|
||||||
GPIO_FUNC2, /* GPIO 0 */
|
|
||||||
GPIO_FUNC2, /* GPIO 1 */
|
|
||||||
GPIO_FUNC2, /* GPIO 2 */
|
|
||||||
GPIO_FUNC2, /* GPIO 3 */
|
|
||||||
GPIO_FUNC2, /* GPIO 4 */
|
|
||||||
GPIO_FUNC2, /* GPIO 5 */
|
|
||||||
GPIO_FUNC2, /* GPIO 6 */
|
|
||||||
GPIO_FUNC2, /* GPIO 7 */
|
|
||||||
GPIO_FUNC2, /* GPIO 8 */
|
|
||||||
GPIO_FUNC2, /* GPIO 9 */
|
|
||||||
GPIO_FUNC2, /* GPIO 10 */
|
|
||||||
GPIO_FUNC2, /* GPIO 11 */
|
|
||||||
GPIO_FUNC2, /* GPIO 12 */
|
|
||||||
GPIO_FUNC2, /* GPIO 13 */
|
|
||||||
GPIO_FUNC2, /* GPIO 14 */
|
|
||||||
GPIO_FUNC2, /* GPIO 15 */
|
|
||||||
GPIO_FUNC2, /* GPIO 16 */
|
|
||||||
GPIO_FUNC2, /* GPIO 17 */
|
|
||||||
GPIO_FUNC2, /* GPIO 18 */
|
|
||||||
GPIO_FUNC2, /* GPIO 19 */
|
|
||||||
GPIO_FUNC2, /* GPIO 20 */
|
|
||||||
GPIO_FUNC2, /* GPIO 21 */
|
|
||||||
GPIO_FUNC2, /* GPIO 22 */
|
|
||||||
GPIO_FUNC2, /* GPIO 23 */
|
|
||||||
GPIO_FUNC2, /* GPIO 24 */
|
|
||||||
GPIO_FUNC2, /* GPIO 25 */
|
|
||||||
GPIO_FUNC2, /* GPIO 26 */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SCORE GPIOs (GPIO_S0_SC_XX)*/
|
|
||||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[000] SATA_GP[0] - - - */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[007] RESERVED SD3_WP - - */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# - - */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC - - */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK - - */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO - - */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[016] MMC1_CLK - MMC1_45_CLK - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[017] MMC1_D[0] - MMC1_45_D[0] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[018] MMC1_D[1] - MMC1_45_D[1] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[019] MMC1_D[2] - MMC1_45_D[2] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[020] MMC1_D[3] - MMC1_45_D[3] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[021] MMC1_D[4] - MMC1_45_D[4] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[022] MMC1_D[5] - MMC1_45_D[5] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[023] MMC1_D[6] - MMC1_45_D[6] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[024] MMC1_D[7] - MMC1_45_D[7] - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[025] MMC1_CMD - MMC1_45_CMD - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[027] SD2_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[028] SD2_D[0] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[029] SD2_D[1] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[030] SD2_D[2] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[031] SD2_D[3]_CD# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[032] SD2_CMD - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[040] SD3_1P8EN - - - */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[041] SD3_PWREN# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[055] RESERVED - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[056] RESERVED - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[058] RESERVED - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[059] RESERVED - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[060] RESERVED - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[066] SIO_SPI_CS# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[067] SIO_SPI_MISO - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[068] SIO_SPI_MOSI - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[069] SIO_SPI_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[075] SIO_UART2_TXD - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[080] SIO_I2C1_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[084] SIO_I2C3_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[085] SIO_I2C3_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[086] SIO_I2C4_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[087] SIO_I2C4_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[088] SIO_I2C5_DATA - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[089] SIO_I2C5_CLK - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP - - */
|
|
||||||
GPIO_FUNC1, /* RESERVED GPIO_S0_SC[092] - - - */
|
|
||||||
GPIO_FUNC1, /* RESERVED GPIO_S0_SC[093] - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[094] SIO_PWM[0] - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[095] SIO_PWM[1] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] - - - */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] - - - */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SSUS GPIOs (GPIO_S5) */
|
|
||||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[00] RESERVED - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC, /* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC, /* GPIO_S5[10] RESERVED RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - - */
|
|
||||||
GPIO_FUNC0, /* PMC_SUSCLK[0] GPIO_S5[12] - - - */
|
|
||||||
GPIO_FUNC1, /* RESERVED GPIO_S5[13] - - - */
|
|
||||||
GPIO_FUNC1, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - - */
|
|
||||||
GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - - */
|
|
||||||
GPIO_FUNC0, /* PMC_PWRBTN# GPIO_S5[16] - - - */
|
|
||||||
GPIO_DEFAULT, /* RESERVED GPIO_S5[17] - - - */
|
|
||||||
GPIO_FUNC1, /* PMC_SUS_STAT# GPIO_S5[18] - - - */
|
|
||||||
GPIO_FUNC0, /* USB_OC[0]# GPIO_S5[19] - - - */
|
|
||||||
GPIO_FUNC0, /* USB_OC[1]# GPIO_S5[20] - - - */
|
|
||||||
GPIO_FUNC0, /* PCU_SPI_CS[1]# GPIO_S5[21] - - - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED - */
|
|
||||||
GPIO_NC, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED - */
|
|
||||||
GPIO_NC, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED - */
|
|
||||||
GPIO_NC, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED - */
|
|
||||||
GPIO_NC, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED - */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct soc_gpio_config gpio_config = {
|
|
||||||
.ncore = gpncore_gpio_map,
|
|
||||||
.score = gpscore_gpio_map,
|
|
||||||
.ssus = gpssus_gpio_map,
|
|
||||||
.core_dirq = NULL,
|
|
||||||
.sus_dirq = NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct soc_gpio_config* mainboard_get_gpios(void)
|
|
||||||
{
|
|
||||||
return &gpio_config;
|
|
||||||
}
|
|
||||||
@@ -1,18 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
DEFINE_IRQ_ROUTES;
|
|
||||||
@@ -1,82 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef IRQROUTE_H
|
|
||||||
#define IRQROUTE_H
|
|
||||||
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/irq.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
*IR02h GFX INT(A) - PIRQ A
|
|
||||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
|
||||||
*IR11h SDIO INT(A) - PIRQ B
|
|
||||||
*IR12h SD INT(A) - PIRQ C
|
|
||||||
*IR13h SATA INT(A) - PIRQ D
|
|
||||||
*IR14h XHCI INT(A) - PIRQ E
|
|
||||||
*IR15h LP Audio INT(A) - PIRQ F
|
|
||||||
*IR17h MMC INT(A) - PIRQ F
|
|
||||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
|
||||||
*IR1Ah TXE INT(A) - PIRQ F
|
|
||||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
|
||||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
|
||||||
*IR1Dh EHCI INT(A) - PIRQ D
|
|
||||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
|
||||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCIe bridge routing */
|
|
||||||
#define BRIDGE1_DEV PCIE_DEV
|
|
||||||
|
|
||||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
|
||||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
|
||||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
|
||||||
|
|
||||||
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
|
|
||||||
#define PCI_DEV_PIRQ_ROUTES \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
|
||||||
* Reserved: 0, 1, 2, 8, 13
|
|
||||||
* PS2 keyboard: 12
|
|
||||||
* ACPI/SCI: 9
|
|
||||||
* Floppy: 6
|
|
||||||
*/
|
|
||||||
#define PIRQ_PIC_ROUTES \
|
|
||||||
PIRQ_PIC(A, 4), \
|
|
||||||
PIRQ_PIC(B, 5), \
|
|
||||||
PIRQ_PIC(C, 7), \
|
|
||||||
PIRQ_PIC(D, 10), \
|
|
||||||
PIRQ_PIC(E, 11), \
|
|
||||||
PIRQ_PIC(F, 12), \
|
|
||||||
PIRQ_PIC(G, 14), \
|
|
||||||
PIRQ_PIC(H, 15)
|
|
||||||
|
|
||||||
#endif /* IRQROUTE_H */
|
|
||||||
@@ -1,35 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <types.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#if CONFIG(VGA_ROM_RUN)
|
|
||||||
#include <x86emu/x86emu.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
|
||||||
* This is the earliest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
};
|
|
||||||
@@ -1,168 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stddef.h>
|
|
||||||
#include <arch/cbfs.h>
|
|
||||||
#include <cpu/x86/mtrr.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
#include <soc/lpc.h>
|
|
||||||
#include <soc/pci_devs.h>
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include <soc/baytrail.h>
|
|
||||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done before fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void early_mainboard_romstage_entry()
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get function disables - most of these will be done automatically
|
|
||||||
* @param fd_mask
|
|
||||||
* @param fd2_mask
|
|
||||||
*/
|
|
||||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done after fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void late_mainboard_romstage_entry()
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
const uint32_t mAzaliaVerbTableData13[] = {
|
|
||||||
/*
|
|
||||||
*ALC262 Verb Table - 10EC0262
|
|
||||||
*/
|
|
||||||
/* Pin Complex (NID 0x11) */
|
|
||||||
0x01171CF0,
|
|
||||||
0x01171D11,
|
|
||||||
0x01171E11,
|
|
||||||
0x01171F41,
|
|
||||||
/* Pin Complex (NID 0x12) */
|
|
||||||
0x01271CF0,
|
|
||||||
0x01271D11,
|
|
||||||
0x01271E11,
|
|
||||||
0x01271F41,
|
|
||||||
/* Pin Complex (NID 0x14) */
|
|
||||||
0x01471C10,
|
|
||||||
0x01471D40,
|
|
||||||
0x01471E01,
|
|
||||||
0x01471F01,
|
|
||||||
/* Pin Complex (NID 0x15) */
|
|
||||||
0x01571CF0,
|
|
||||||
0x01571D11,
|
|
||||||
0x01571E11,
|
|
||||||
0x01571F41,
|
|
||||||
/* Pin Complex (NID 0x16) */
|
|
||||||
0x01671CF0,
|
|
||||||
0x01671D11,
|
|
||||||
0x01671E11,
|
|
||||||
0x01671F41,
|
|
||||||
/* Pin Complex (NID 0x18) */
|
|
||||||
0x01871C20,
|
|
||||||
0x01871D98,
|
|
||||||
0x01871EA1,
|
|
||||||
0x01871F01,
|
|
||||||
/* Pin Complex (NID 0x19) */
|
|
||||||
0x01971C21,
|
|
||||||
0x01971D98,
|
|
||||||
0x01971EA1,
|
|
||||||
0x01971F02,
|
|
||||||
/* Pin Complex (NID 0x1A) */
|
|
||||||
0x01A71C2F,
|
|
||||||
0x01A71D30,
|
|
||||||
0x01A71E81,
|
|
||||||
0x01A71F01,
|
|
||||||
/* Pin Complex (NID 0x1B) */
|
|
||||||
0x01B71C1F,
|
|
||||||
0x01B71D40,
|
|
||||||
0x01B71E21,
|
|
||||||
0x01B71F02,
|
|
||||||
/* Pin Complex (NID 0x1C) */
|
|
||||||
0x01C71CF0,
|
|
||||||
0x01C71D11,
|
|
||||||
0x01C71E11,
|
|
||||||
0x01C71F41,
|
|
||||||
/* Pin Complex (NID 0x1D) */
|
|
||||||
0x01D71C01,
|
|
||||||
0x01D71DC6,
|
|
||||||
0x01D71E14,
|
|
||||||
0x01D71F40,
|
|
||||||
/* Pin Complex (NID 0x1E) */
|
|
||||||
0x01E71CF0,
|
|
||||||
0x01E71D11,
|
|
||||||
0x01E71E11,
|
|
||||||
0x01E71F41,
|
|
||||||
/* Pin Complex (NID 0x1F) */
|
|
||||||
0x01F71CF0,
|
|
||||||
0x01F71D11,
|
|
||||||
0x01F71E11,
|
|
||||||
0x01F71F41 };
|
|
||||||
|
|
||||||
const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { {
|
|
||||||
/*
|
|
||||||
* VerbTable: (RealTek ALC262)
|
|
||||||
* Revision ID = 0xFF, support all steps
|
|
||||||
* Codec Verb Table For AZALIA
|
|
||||||
* Codec Address: CAd value (0/1/2)
|
|
||||||
* Codec Vendor: 0x10EC0262
|
|
||||||
*/
|
|
||||||
{
|
|
||||||
0x10EC0262, /* Vendor ID/Device IDA */
|
|
||||||
0x0000, /* SubSystem ID */
|
|
||||||
0xFF, /* Revision IDA */
|
|
||||||
0x01, /* Front panel support (1=yes, 2=no) */
|
|
||||||
0x000B, /* Number of Rear Jacks = 11 */
|
|
||||||
0x0002 /* Number of Front Jacks = 2 */
|
|
||||||
},
|
|
||||||
(uint32_t *)mAzaliaVerbTableData13 } };
|
|
||||||
|
|
||||||
const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = {
|
|
||||||
.Pme = 1,
|
|
||||||
.DS = 1,
|
|
||||||
.DA = 0,
|
|
||||||
.HdmiCodec = 1,
|
|
||||||
.AzaliaVCi = 1,
|
|
||||||
.Rsvdbits = 0,
|
|
||||||
.AzaliaVerbTableNum = 1,
|
|
||||||
.AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable,
|
|
||||||
.ResetWaitTimer = 300 };
|
|
||||||
|
|
||||||
/** /brief customize fsp parameters here if needed
|
|
||||||
*/
|
|
||||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
|
||||||
{
|
|
||||||
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
|
|
||||||
|
|
||||||
/* Initialize the Azalia Verb Tables to mainboard specific version */
|
|
||||||
UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig;
|
|
||||||
|
|
||||||
/* Disable 2nd DIMM on Bakersport*/
|
|
||||||
#if CONFIG(BOARD_INTEL_BAKERSPORT_FSP)
|
|
||||||
UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MAINBOARD_THERMAL_H
|
|
||||||
#define MAINBOARD_THERMAL_H
|
|
||||||
|
|
||||||
|
|
||||||
/* Temperature which OS will shutdown at */
|
|
||||||
#define CRITICAL_TEMPERATURE 100
|
|
||||||
|
|
||||||
/* Temperature which OS will throttle CPU */
|
|
||||||
#define PASSIVE_TEMPERATURE 90
|
|
||||||
|
|
||||||
/* Tj_max value for calculating PECI CPU temperature */
|
|
||||||
#define MAX_TEMPERATURE 100
|
|
||||||
|
|
||||||
#endif /* MAINBOARD_THERMAL_H */
|
|
||||||
@@ -1,64 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
## Copyright (C) 2014 Intel Corporation
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
if BOARD_INTEL_MINNOWMAX
|
|
||||||
|
|
||||||
config BOARD_SPECIFIC_OPTIONS
|
|
||||||
def_bool y
|
|
||||||
select SOC_INTEL_FSP_BAYTRAIL
|
|
||||||
select BOARD_ROMSIZE_KB_8192
|
|
||||||
select HAVE_ACPI_TABLES
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default "intel/minnowmax"
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "Minnow Max"
|
|
||||||
|
|
||||||
config MAX_CPUS
|
|
||||||
int
|
|
||||||
default 16
|
|
||||||
|
|
||||||
config FSP_FILE
|
|
||||||
string
|
|
||||||
default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
|
|
||||||
|
|
||||||
config CBFS_SIZE
|
|
||||||
hex
|
|
||||||
default 0x00300000
|
|
||||||
|
|
||||||
config ENABLE_FSP_FAST_BOOT
|
|
||||||
bool
|
|
||||||
depends on HAVE_FSP_BIN
|
|
||||||
default y
|
|
||||||
|
|
||||||
config VIRTUAL_ROM_SIZE
|
|
||||||
hex
|
|
||||||
depends on ENABLE_FSP_FAST_BOOT
|
|
||||||
default 0x800000
|
|
||||||
|
|
||||||
config POST_DEVICE
|
|
||||||
bool
|
|
||||||
default n
|
|
||||||
|
|
||||||
config VGA_BIOS
|
|
||||||
bool
|
|
||||||
default y if FSP_PACKAGE_DEFAULT
|
|
||||||
|
|
||||||
endif # BOARD_INTEL_MINNOWMAX
|
|
||||||
@@ -1,2 +0,0 @@
|
|||||||
config BOARD_INTEL_MINNOWMAX
|
|
||||||
bool "Minnow Max"
|
|
||||||
@@ -1,17 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013 Google Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
ramstage-y += gpio.c
|
|
||||||
ramstage-y += irqroute.c
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; version 2 of
|
|
||||||
* the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
Device (PWRB)
|
|
||||||
{
|
|
||||||
Name(_HID, EisaId("PNP0C0C"))
|
|
||||||
}
|
|
||||||
@@ -1,48 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Google Inc.
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <types.h>
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <arch/ioapic.h>
|
|
||||||
#include <arch/smp/mpspec.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
#include <soc/nvs.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
|
|
||||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
|
||||||
{
|
|
||||||
acpi_init_gnvs(gnvs);
|
|
||||||
|
|
||||||
/* No TPM Present */
|
|
||||||
gnvs->tpmp = 0;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long acpi_fill_madt(unsigned long current)
|
|
||||||
{
|
|
||||||
/* Local APICs */
|
|
||||||
current = acpi_create_madt_lapics(current);
|
|
||||||
|
|
||||||
/* IOAPIC */
|
|
||||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
|
||||||
2, IO_APIC_ADDR, 0);
|
|
||||||
|
|
||||||
current = acpi_madt_irq_overrides(current);
|
|
||||||
|
|
||||||
return current;
|
|
||||||
}
|
|
||||||
@@ -1,4 +0,0 @@
|
|||||||
Category: sbc
|
|
||||||
ROM protocol: SPI
|
|
||||||
Flashrom support: y
|
|
||||||
Release year: 2014
|
|
||||||
@@ -1,108 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2007-2008 coresystems GmbH
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
entries
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register A
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register B
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register C
|
|
||||||
#96 4 r 0 status_c_rsvd
|
|
||||||
#100 1 r 0 uf_flag
|
|
||||||
#101 1 r 0 af_flag
|
|
||||||
#102 1 r 0 pf_flag
|
|
||||||
#103 1 r 0 irqf_flag
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register D
|
|
||||||
#104 7 r 0 status_d_rsvd
|
|
||||||
#111 1 r 0 valid_cmos_ram
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Diagnostic Status Register
|
|
||||||
#112 8 r 0 diag_rsvd1
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
0 120 r 0 reserved_memory
|
|
||||||
#120 264 r 0 unused
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
388 4 h 0 reboot_counter
|
|
||||||
#390 2 r 0 unused?
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# coreboot config options: console
|
|
||||||
#392 3 r 0 unused
|
|
||||||
395 4 e 6 debug_level
|
|
||||||
#399 1 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: cpu
|
|
||||||
400 1 e 2 hyper_threading
|
|
||||||
#401 7 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
|
||||||
408 1 e 1 nmi
|
|
||||||
409 2 e 7 power_on_after_fail
|
|
||||||
411 2 e 8 use_xhci_over_ehci
|
|
||||||
#413 3 r 0 unused
|
|
||||||
|
|
||||||
# MRC Scrambler Seed values
|
|
||||||
896 32 r 0 mrc_scrambler_seed
|
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
#1000 24 r 0 amd_reserved
|
|
||||||
|
|
||||||
#save timestamps in pre-ram boot areas
|
|
||||||
1720 64 h 0 timestamp_value1
|
|
||||||
1784 64 h 0 timestamp_value2
|
|
||||||
1848 64 h 0 timestamp_value3
|
|
||||||
1912 64 h 0 timestamp_value4
|
|
||||||
1976 64 h 0 timestamp_value5
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 0 Emergency
|
|
||||||
6 1 Alert
|
|
||||||
6 2 Critical
|
|
||||||
6 3 Error
|
|
||||||
6 4 Warning
|
|
||||||
6 5 Notice
|
|
||||||
6 6 Info
|
|
||||||
6 7 Debug
|
|
||||||
6 8 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
8 0 EHCI
|
|
||||||
8 1 XHCI
|
|
||||||
8 2 Default
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 415 984
|
|
||||||
@@ -1,93 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
## Copyright (C) 2014 Intel Corporation
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
chip soc/intel/fsp_baytrail
|
|
||||||
|
|
||||||
#### ACPI Register Settings ####
|
|
||||||
register "fadt_pm_profile" = "PM_UNSPECIFIED"
|
|
||||||
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
|
|
||||||
|
|
||||||
#### FSP register settings ####
|
|
||||||
register "PcdSataMode" = "SATA_MODE_AHCI"
|
|
||||||
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
|
|
||||||
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
|
|
||||||
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
|
|
||||||
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
|
|
||||||
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
|
|
||||||
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
|
|
||||||
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
|
|
||||||
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
|
|
||||||
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
|
|
||||||
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
|
|
||||||
register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
|
|
||||||
register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
|
|
||||||
register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
|
|
||||||
register "DRAMType" = "DRAM_TYPE_DDR3L"
|
|
||||||
register "DIMM0Enable" = "DIMM0_ENABLE"
|
|
||||||
register "DIMM1Enable" = "DIMM1_DISABLE"
|
|
||||||
register "DIMMDWidth" = "DIMM_DWIDTH_X16"
|
|
||||||
register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT
|
|
||||||
register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
|
|
||||||
register "DIMMSides" = "DIMM_SIDES_1RANK"
|
|
||||||
register "DIMMtCL" = "11"
|
|
||||||
register "DIMMtRPtRCD" = "11"
|
|
||||||
register "DIMMtWR" = "12"
|
|
||||||
register "DIMMtWTR" = "6"
|
|
||||||
register "DIMMtRRD" = "6"
|
|
||||||
register "DIMMtRTP" = "6"
|
|
||||||
register "DIMMtFAW" = "20"
|
|
||||||
|
|
||||||
device cpu_cluster 0 on
|
|
||||||
device lapic 0 on end
|
|
||||||
end
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
device pci 00.0 on end # 8086 0F00 - SoC router -
|
|
||||||
device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
|
|
||||||
device pci 03.0 off end # 8086 0F38 - MIPI -
|
|
||||||
|
|
||||||
device pci 10.0 off end # 8086 0F14 - EMMC Port -
|
|
||||||
device pci 11.0 off end # 8086 0F15 - SDIO Port -
|
|
||||||
device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
|
|
||||||
device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
|
|
||||||
device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
|
|
||||||
device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
|
|
||||||
device pci 17.0 off end # 8086 0F50 - MMC Port -
|
|
||||||
device pci 18.0 on end # 8086 0F40 - SIO - DMA -
|
|
||||||
device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
|
|
||||||
device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
|
|
||||||
device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) -
|
|
||||||
device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) -
|
|
||||||
device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) -
|
|
||||||
device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC
|
|
||||||
device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
|
|
||||||
device pci 1a.0 on end # 8086 0F18 - TXE -
|
|
||||||
device pci 1b.0 off end # 8086 0F04 - HD Audio -
|
|
||||||
device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on
|
|
||||||
device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models)
|
|
||||||
device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
|
|
||||||
device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
|
|
||||||
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
|
|
||||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
|
|
||||||
device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC
|
|
||||||
device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC
|
|
||||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC
|
|
||||||
device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC
|
|
||||||
device pci 1e.5 on end # 8086 0F0E - SPI LSEC
|
|
||||||
device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
|
|
||||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,54 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INCLUDE_LPE 1
|
|
||||||
#define INCLUDE_SCC 1
|
|
||||||
#define INCLUDE_EHCI 1
|
|
||||||
#define INCLUDE_XHCI 1
|
|
||||||
#define INCLUDE_LPSS 1
|
|
||||||
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20110725 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Some generic macros
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
|
||||||
|
|
||||||
// global NVS and variables
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
|
||||||
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Chipset specific sleep states */
|
|
||||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
|
|
||||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
|
||||||
{
|
|
||||||
acpi_header_t *header = &(fadt->header);
|
|
||||||
|
|
||||||
acpi_fill_in_fadt(fadt, facs, dsdt);
|
|
||||||
|
|
||||||
/* Platform specific customizations go here */
|
|
||||||
|
|
||||||
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
|
||||||
}
|
|
||||||
@@ -1,232 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For multiplexed functions, look in EDS:
|
|
||||||
* 10.3 Ball Name and Function by Location
|
|
||||||
*
|
|
||||||
* The pads list is in the BWG_VOL2 Rev1p2:
|
|
||||||
* Note that Pad # is not the same as GPIO#
|
|
||||||
* 37 GPIO Handling:
|
|
||||||
* Table 37-1. SCORE Pads List
|
|
||||||
* Table 37-2. SSUSORE Pads List
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* NCORE GPIOs */
|
|
||||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
|
||||||
GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD
|
|
||||||
GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT
|
|
||||||
GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK
|
|
||||||
GPIO_NC, // GPIO_S0_NC[03] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[04] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[05] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[06] - No Connect
|
|
||||||
GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT
|
|
||||||
GPIO_NC, // GPIO_S0_NC[08] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[09] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[10] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[11] - No Connect
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15
|
|
||||||
GPIO_NC, // GPIO_S0_NC[13] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[14] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[15] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[16] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[17] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[18] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[19] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[20] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[21] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[22] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[23] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[24] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[25] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_NC[26] - No Connect
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SCORE GPIOs (GPIO_S0_SC_XX) */
|
|
||||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3
|
|
||||||
GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP
|
|
||||||
GPIO_NC, // GPIO_S0_SC[008] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[009] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[010] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[011] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[012] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[013] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[014] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[015] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[016] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[017] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[018] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[019] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[020] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[021] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[022] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[023] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[024] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[025] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[026] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[027] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[028] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[029] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[030] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[031] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[032] - No Connect
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD#
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN)
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN)
|
|
||||||
GPIO_NC, // GPIO_S0_SC[042] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[043] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[044] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[045] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[046] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[047] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[048] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[049] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[050] - No Connect
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55)
|
|
||||||
GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58)
|
|
||||||
GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB
|
|
||||||
GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD
|
|
||||||
GPIO_NC, // GPIO_S0_SC[076] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[077] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[078] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[079] - No Connect
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA)
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL)
|
|
||||||
GPIO_NC, // GPIO_S0_SC[082] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[083] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[084] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[085] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[086] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[087] - No Connect
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL
|
|
||||||
GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13
|
|
||||||
GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0
|
|
||||||
GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1
|
|
||||||
GPIO_NC, // GPIO_S0_SC[096] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[097] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[098] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[099] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[100] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S0_SC[101] - No Connect
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SSUS GPIOs (GPIO_S5) */
|
|
||||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2
|
|
||||||
GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB
|
|
||||||
GPIO_NC, // GPIO_S5[04] - No Connect
|
|
||||||
GPIO_INPUT, // GPIO_S5[05] - BOM_OP1
|
|
||||||
// Memory: 0=1GB 1=2GB or 4GB
|
|
||||||
GPIO_INPUT, // GPIO_S5[06] - BOM_OP2
|
|
||||||
GPIO_INPUT, // GPIO_S5[07] - BOM_OP3
|
|
||||||
GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0
|
|
||||||
GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1
|
|
||||||
GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK
|
|
||||||
GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14)
|
|
||||||
GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0
|
|
||||||
GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10)
|
|
||||||
GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20
|
|
||||||
GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R
|
|
||||||
GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN
|
|
||||||
GPIO_NC, // GPIO_S5[17] - No Connect
|
|
||||||
GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7)
|
|
||||||
GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0
|
|
||||||
GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1
|
|
||||||
GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B
|
|
||||||
GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3
|
|
||||||
GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4
|
|
||||||
GPIO_NC, // GPIO_S5[31] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[32] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[33] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[34] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[35] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[36] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[37] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[38] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[39] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[40] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[41] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[42] - No Connect
|
|
||||||
GPIO_NC, // GPIO_S5[43] - No Connect
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct soc_gpio_config gpio_config = {
|
|
||||||
.ncore = gpncore_gpio_map,
|
|
||||||
.score = gpscore_gpio_map,
|
|
||||||
.ssus = gpssus_gpio_map,
|
|
||||||
.core_dirq = NULL,
|
|
||||||
.sus_dirq = NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct soc_gpio_config *mainboard_get_gpios(void)
|
|
||||||
{
|
|
||||||
return &gpio_config;
|
|
||||||
}
|
|
||||||
@@ -1,18 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
DEFINE_IRQ_ROUTES;
|
|
||||||
@@ -1,83 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef IRQROUTE_H
|
|
||||||
#define IRQROUTE_H
|
|
||||||
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/irq.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
*IR02h GFX INT(A) - PIRQ A
|
|
||||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
|
||||||
*IR11h SDIO INT(A) - PIRQ B
|
|
||||||
*IR12h SD INT(A) - PIRQ C
|
|
||||||
*IR13h SATA INT(A) - PIRQ D
|
|
||||||
*IR14h XHCI INT(A) - PIRQ E
|
|
||||||
*IR15h LP Audio INT(A) - PIRQ F
|
|
||||||
*IR17h MMC INT(A) - PIRQ F
|
|
||||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
|
||||||
*IR1Ah TXE INT(A) - PIRQ F
|
|
||||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
|
||||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
|
||||||
*IR1Dh EHCI INT(A) - PIRQ D
|
|
||||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
|
||||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCIe bridge routing */
|
|
||||||
#define BRIDGE1_DEV PCIE_DEV
|
|
||||||
|
|
||||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
|
||||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
|
||||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
|
||||||
|
|
||||||
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
|
|
||||||
#define PCI_DEV_PIRQ_ROUTES \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
|
||||||
* Reserved: 0, 1, 2, 8, 13
|
|
||||||
* PS2 keyboard: 12
|
|
||||||
* ACPI/SCI: 9
|
|
||||||
* Floppy: 6
|
|
||||||
*/
|
|
||||||
#define PIRQ_PIC_ROUTES \
|
|
||||||
PIRQ_PIC(A, 3), \
|
|
||||||
PIRQ_PIC(B, 5), \
|
|
||||||
PIRQ_PIC(C, 7), \
|
|
||||||
PIRQ_PIC(D, 10), \
|
|
||||||
PIRQ_PIC(E, 11), \
|
|
||||||
PIRQ_PIC(F, 12), \
|
|
||||||
PIRQ_PIC(G, 14), \
|
|
||||||
PIRQ_PIC(H, 15)
|
|
||||||
|
|
||||||
#endif /* IRQROUTE_H */
|
|
||||||
@@ -1,41 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/device.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
|
||||||
* This is the earliest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_final is executed as one of the last items before loading the
|
|
||||||
* payload.
|
|
||||||
*
|
|
||||||
* This is the latest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_final(void *chip_info)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
.final = mainboard_final,
|
|
||||||
};
|
|
||||||
@@ -1,140 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2014 Intel Corporation
|
|
||||||
* Copyright (C) 2018 CMR Surgical Limited
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
|
||||||
#include <pc80/mc146818rtc.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/chip.h>
|
|
||||||
#include <cpu/x86/tsc.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done before fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void early_mainboard_romstage_entry(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get function disables - most of these will be done automatically
|
|
||||||
* @param fd_mask
|
|
||||||
* @param fd2_mask
|
|
||||||
*/
|
|
||||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done after fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void late_mainboard_romstage_entry(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set up the default soldered down memory config for 1GB */
|
|
||||||
static const MEMORY_DOWN_DATA minnowmax_memory_config[] = {
|
|
||||||
/* 1066 */
|
|
||||||
{
|
|
||||||
.EnableMemoryDown = 1,
|
|
||||||
.DRAMSpeed = 1, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/
|
|
||||||
.DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
|
|
||||||
.DIMM0Enable = 1, /* DIMM 0 Enable */
|
|
||||||
.DIMM1Enable = 0, /* DIMM 1 Enable */
|
|
||||||
.DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/
|
|
||||||
.DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
|
|
||||||
.DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
|
|
||||||
.DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */
|
|
||||||
.DIMMtCL = 11, /* tCL */
|
|
||||||
.DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
|
|
||||||
.DIMMtWR = 12, /* tWR in DRAM clk */
|
|
||||||
.DIMMtWTR = 6, /* tWTR in DRAM clk */
|
|
||||||
.DIMMtRRD = 6, /* tRRD in DRAM clk */
|
|
||||||
.DIMMtRTP = 6, /* tRTP in DRAM clk */
|
|
||||||
.DIMMtFAW = 20, /* tFAW in DRAM clk */
|
|
||||||
},
|
|
||||||
/* 1333 */
|
|
||||||
{
|
|
||||||
.EnableMemoryDown = 1,
|
|
||||||
.DRAMSpeed = 2, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/
|
|
||||||
.DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
|
|
||||||
.DIMM0Enable = 1, /* DIMM 0 Enable */
|
|
||||||
.DIMM1Enable = 0, /* DIMM 1 Enable */
|
|
||||||
.DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/
|
|
||||||
.DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
|
|
||||||
.DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
|
|
||||||
.DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */
|
|
||||||
.DIMMtCL = 9, /* tCL */
|
|
||||||
.DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
|
|
||||||
.DIMMtWR = 10, /* tWR in DRAM clk */
|
|
||||||
.DIMMtWTR = 5, /* tWTR in DRAM clk */
|
|
||||||
.DIMMtRRD = 4, /* tRRD in DRAM clk */
|
|
||||||
.DIMMtRTP = 5, /* tRTP in DRAM clk */
|
|
||||||
.DIMMtFAW = 30, /* tFAW in DRAM clk */
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
|
||||||
{
|
|
||||||
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
|
|
||||||
u8 use_xhci = UpdData->PcdEnableXhci;
|
|
||||||
u8 gpio5 = 0;
|
|
||||||
int is_1333_sku;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's
|
|
||||||
* no good way of knowing the SKU'ing so frequency is used as a proxy.
|
|
||||||
* The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the
|
|
||||||
* E3827 and E3845 are 1750MHz and 1910MHz, respectively.
|
|
||||||
*/
|
|
||||||
is_1333_sku = !!(tsc_freq_mhz() >= 1700);
|
|
||||||
|
|
||||||
printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n",
|
|
||||||
is_1333_sku ? 1333 : 1066);
|
|
||||||
|
|
||||||
/* Set up soldered down memory parameters for 1GB */
|
|
||||||
UpdData->PcdMemoryParameters = minnowmax_memory_config[is_1333_sku];
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Minnow Max Board
|
|
||||||
* Read SSUS gpio 5 to determine memory type
|
|
||||||
* 0 : 1GB SKU uses 2Gb density memory
|
|
||||||
* 1 : 2GB SKU uses 4Gb density memory
|
|
||||||
*
|
|
||||||
* devicetree.cb assumes 1GB SKU board
|
|
||||||
*/
|
|
||||||
configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
|
||||||
gpio5 = read_ssus_gpio(5);
|
|
||||||
if (gpio5)
|
|
||||||
UpdData->PcdMemoryParameters.DIMMDensity
|
|
||||||
+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
|
|
||||||
printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n",
|
|
||||||
gpio5 ? "2 / 4" : "1");
|
|
||||||
/* Update XHCI UPD value if required */
|
|
||||||
get_option(&use_xhci, "use_xhci_over_ehci");
|
|
||||||
if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
|
|
||||||
UpdData->PcdEnableXhci = use_xhci;
|
|
||||||
printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
|
|
||||||
UpdData->PcdEnableXhci?"Enabled":"Disabled");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,106 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
## Copyright (C) 2014 Intel Corporation
|
|
||||||
## Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
|
|
||||||
def_bool n
|
|
||||||
select SOC_INTEL_FSP_BAYTRAIL
|
|
||||||
select BOARD_ROMSIZE_KB_8192
|
|
||||||
select HAVE_ACPI_TABLES
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
select ENABLE_BUILTIN_COM1
|
|
||||||
select ENABLE_FSP_FAST_BOOT
|
|
||||||
select USE_BLOBS
|
|
||||||
select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
|
|
||||||
select MAINBOARD_HAS_LPC_TPM
|
|
||||||
select MAINBOARD_HAS_TPM1
|
|
||||||
|
|
||||||
if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
|
|
||||||
|
|
||||||
config VBOOT
|
|
||||||
select MRC_CACHE_FMAP
|
|
||||||
select VBOOT_VBNV_CMOS
|
|
||||||
select VBOOT_NO_BOARD_SUPPORT
|
|
||||||
select GBB_FLAG_DISABLE_LID_SHUTDOWN
|
|
||||||
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
|
|
||||||
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
|
|
||||||
select GBB_FLAG_DISABLE_FWMP
|
|
||||||
|
|
||||||
config GBB_HWID
|
|
||||||
string
|
|
||||||
depends on VBOOT
|
|
||||||
default "ROTUNDU" if BOARD_OPENCELLULAR_ROTUNDU
|
|
||||||
default "SUPABRCKV1" if BOARD_OPENCELLULAR_SUPABRCKV1
|
|
||||||
|
|
||||||
config VARIANT_DIR
|
|
||||||
string
|
|
||||||
default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU
|
|
||||||
default "supabrckv1" if BOARD_OPENCELLULAR_SUPABRCKV1
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "Rotundu" if BOARD_OPENCELLULAR_ROTUNDU
|
|
||||||
default "Supabrck v1" if BOARD_OPENCELLULAR_SUPABRCKV1
|
|
||||||
|
|
||||||
config DEVICETREE
|
|
||||||
string
|
|
||||||
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default "opencellular/rotundu"
|
|
||||||
|
|
||||||
config MAINBOARD_VENDOR
|
|
||||||
string
|
|
||||||
default "OpenCellular"
|
|
||||||
|
|
||||||
config MAX_CPUS
|
|
||||||
int
|
|
||||||
default 16
|
|
||||||
|
|
||||||
config FSP_LOC
|
|
||||||
hex
|
|
||||||
default 0xfffb0000
|
|
||||||
|
|
||||||
config FMDFILE
|
|
||||||
string
|
|
||||||
depends on VBOOT
|
|
||||||
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-8M.fmd" if BOARD_ROMSIZE_KB_8192
|
|
||||||
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-16M.fmd" if BOARD_ROMSIZE_KB_16384
|
|
||||||
|
|
||||||
config CBFS_SIZE
|
|
||||||
hex
|
|
||||||
default 0x00140000 if BOARD_ROMSIZE_KB_8192
|
|
||||||
default 0x003effc0 if BOARD_ROMSIZE_KB_16384
|
|
||||||
|
|
||||||
config VIRTUAL_ROM_SIZE
|
|
||||||
hex
|
|
||||||
depends on ENABLE_FSP_FAST_BOOT
|
|
||||||
default 0x800000
|
|
||||||
|
|
||||||
config FSP_PACKAGE_DEFAULT
|
|
||||||
bool "Configure defaults for the Intel FSP package"
|
|
||||||
default n
|
|
||||||
|
|
||||||
config VGA_BIOS
|
|
||||||
bool
|
|
||||||
default y if FSP_PACKAGE_DEFAULT
|
|
||||||
|
|
||||||
config VGA_BIOS_ID
|
|
||||||
string
|
|
||||||
default "8086,0f31"
|
|
||||||
|
|
||||||
endif # BOARD_OPENCELLULAR_ROTUNDU
|
|
||||||
@@ -1,7 +0,0 @@
|
|||||||
config BOARD_OPENCELLULAR_ROTUNDU
|
|
||||||
bool "OpenCellular Rotundu (GBCv1)"
|
|
||||||
select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
|
|
||||||
|
|
||||||
config BOARD_OPENCELLULAR_SUPABRCKV1
|
|
||||||
bool "OpenCellular Supabrck V1 (BRCK)"
|
|
||||||
select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
|
|
||||||
@@ -1,19 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013 Google Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
|
|
||||||
ramstage-y += irqroute.c
|
|
||||||
|
|
||||||
subdirs-y += variants/$(VARIANT_DIR)
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; version 2 of
|
|
||||||
* the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
Device (PWRB)
|
|
||||||
{
|
|
||||||
Name(_HID, EisaId("PNP0C0C"))
|
|
||||||
}
|
|
||||||
@@ -1,56 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Google Inc.
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <arch/ioapic.h>
|
|
||||||
#include <arch/smp/mpspec.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
#include <soc/nvs.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
|
|
||||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
|
||||||
{
|
|
||||||
acpi_init_gnvs(gnvs);
|
|
||||||
|
|
||||||
/* Enable USB ports in S3 */
|
|
||||||
gnvs->s3u0 = 1;
|
|
||||||
gnvs->s3u1 = 1;
|
|
||||||
|
|
||||||
/* Disable USB ports in S5 */
|
|
||||||
gnvs->s5u0 = 0;
|
|
||||||
gnvs->s5u1 = 0;
|
|
||||||
|
|
||||||
/* TPM Present */
|
|
||||||
gnvs->tpmp = 1;
|
|
||||||
|
|
||||||
/* Enable DPTF */
|
|
||||||
gnvs->dpte = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long acpi_fill_madt(unsigned long current)
|
|
||||||
{
|
|
||||||
/* Local APICs */
|
|
||||||
current = acpi_create_madt_lapics(current);
|
|
||||||
|
|
||||||
/* IOAPIC */
|
|
||||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
|
||||||
2, IO_APIC_ADDR, 0);
|
|
||||||
|
|
||||||
current = acpi_madt_irq_overrides(current);
|
|
||||||
|
|
||||||
return current;
|
|
||||||
}
|
|
||||||
@@ -1,4 +0,0 @@
|
|||||||
Board name: Rotundu
|
|
||||||
Category: sbc
|
|
||||||
ROM protocol: SPI
|
|
||||||
ROM socketed: n
|
|
||||||
@@ -1,37 +0,0 @@
|
|||||||
FLASH@0xff800000 0x800000 {
|
|
||||||
SI_ALL@0x0 0x300000 {
|
|
||||||
SI_DESC@0x0 0x1000
|
|
||||||
SI_ME@0x1000 0x2ff000
|
|
||||||
}
|
|
||||||
SI_BIOS@0x300000 0x500000 {
|
|
||||||
RW_SECTION_A@0x0 0xf0000 {
|
|
||||||
VBLOCK_A@0x0 0x10000
|
|
||||||
FW_MAIN_A(CBFS)@0x10000 0xc0000
|
|
||||||
RW_FWID_A@0xeffc0 0x40
|
|
||||||
}
|
|
||||||
RW_SECTION_B@0xf0000 0xf0000 {
|
|
||||||
VBLOCK_B@0x0 0x10000
|
|
||||||
FW_MAIN_B(CBFS)@0x10000 0xc0000
|
|
||||||
RW_FWID_B@0xeffc0 0x40
|
|
||||||
}
|
|
||||||
RW_MRC_CACHE@0x1e0000 0x10000
|
|
||||||
RW_ELOG(PRESERVE)@0x1f0000 0x4000
|
|
||||||
RW_SHARED@0x1f4000 0x4000 {
|
|
||||||
SHARED_DATA@0x0 0x2000
|
|
||||||
VBLOCK_DEV@0x2000 0x2000
|
|
||||||
}
|
|
||||||
RW_VPD(PRESERVE)@0x1f8000 0x2000
|
|
||||||
RW_UNUSED@0x1fa000 0x106000
|
|
||||||
WP_RO@0x300000 0x200000 {
|
|
||||||
RO_VPD(PRESERVE)@0x0 0x4000
|
|
||||||
RO_UNUSED@0x4000 0xc000
|
|
||||||
RO_SECTION@0x10000 0x1f0000 {
|
|
||||||
FMAP@0x0 0x800
|
|
||||||
RO_FRID@0x800 0x40
|
|
||||||
RO_FRID_PAD@0x840 0x7c0
|
|
||||||
GBB@0x1000 0xef000
|
|
||||||
COREBOOT(CBFS)@0xf0000 0x100000
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1 +0,0 @@
|
|||||||
debug_level=Error
|
|
||||||
@@ -1,97 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2007-2008 coresystems GmbH
|
|
||||||
## Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
entries
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register A
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register B
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register C
|
|
||||||
#96 4 r 0 status_c_rsvd
|
|
||||||
#100 1 r 0 uf_flag
|
|
||||||
#101 1 r 0 af_flag
|
|
||||||
#102 1 r 0 pf_flag
|
|
||||||
#103 1 r 0 irqf_flag
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register D
|
|
||||||
#104 7 r 0 status_d_rsvd
|
|
||||||
#111 1 r 0 valid_cmos_ram
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Diagnostic Status Register
|
|
||||||
#112 8 r 0 diag_rsvd1
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
0 120 r 0 reserved_memory
|
|
||||||
#120 264 r 0 unused
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
#390 2 r 0 unused?
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# coreboot config options: console
|
|
||||||
395 4 e 6 debug_level
|
|
||||||
#399 1 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: cpu
|
|
||||||
#401 7 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
|
||||||
408 1 e 1 nmi
|
|
||||||
411 2 e 8 use_xhci_over_ehci
|
|
||||||
#413 3 r 0 unused
|
|
||||||
|
|
||||||
# MRC Scrambler Seed values
|
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
#1000 24 r 0 amd_reserved
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 1 Emergency
|
|
||||||
6 2 Alert
|
|
||||||
6 3 Critical
|
|
||||||
6 4 Error
|
|
||||||
6 5 Warning
|
|
||||||
6 6 Notice
|
|
||||||
6 7 Info
|
|
||||||
6 8 Debug
|
|
||||||
6 9 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
8 0 EHCI
|
|
||||||
8 1 XHCI
|
|
||||||
8 2 Default
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 415 984
|
|
||||||
@@ -1,54 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INCLUDE_LPE 1
|
|
||||||
#define INCLUDE_SCC 1
|
|
||||||
#define INCLUDE_EHCI 1
|
|
||||||
#define INCLUDE_XHCI 1
|
|
||||||
#define INCLUDE_LPSS 1
|
|
||||||
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20110725 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Some generic macros
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
|
||||||
|
|
||||||
// global NVS and variables
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
|
||||||
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Chipset specific sleep states */
|
|
||||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
|
|
||||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
|
||||||
{
|
|
||||||
acpi_header_t *header = &(fadt->header);
|
|
||||||
|
|
||||||
acpi_fill_in_fadt(fadt, facs, dsdt);
|
|
||||||
|
|
||||||
/* Platform specific customizations go here */
|
|
||||||
|
|
||||||
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
|
||||||
}
|
|
||||||
@@ -1,18 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
DEFINE_IRQ_ROUTES;
|
|
||||||
@@ -1,84 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef IRQROUTE_H
|
|
||||||
#define IRQROUTE_H
|
|
||||||
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/irq.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
*IR02h GFX INT(A) - PIRQ A
|
|
||||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
|
||||||
*IR11h SDIO INT(A) - PIRQ B
|
|
||||||
*IR12h SD INT(A) - PIRQ C
|
|
||||||
*IR13h SATA INT(A) - PIRQ D
|
|
||||||
*IR14h XHCI INT(A) - PIRQ E
|
|
||||||
*IR15h LP Audio INT(A) - PIRQ F
|
|
||||||
*IR17h MMC INT(A) - PIRQ F
|
|
||||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
|
||||||
*IR1Ah TXE INT(A) - PIRQ F
|
|
||||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
|
||||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
|
||||||
*IR1Dh EHCI INT(A) - PIRQ D
|
|
||||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
|
||||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCIe bridge routing */
|
|
||||||
#define BRIDGE1_DEV PCIE_DEV
|
|
||||||
|
|
||||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
|
||||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
|
||||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
|
||||||
|
|
||||||
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
|
|
||||||
#define PCI_DEV_PIRQ_ROUTES \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
|
||||||
* Reserved: 0, 1, 2, 8, 13
|
|
||||||
* PS2 keyboard: 12
|
|
||||||
* ACPI/SCI: 9
|
|
||||||
* Floppy: 6
|
|
||||||
*/
|
|
||||||
#define PIRQ_PIC_ROUTES \
|
|
||||||
PIRQ_PIC(A, 4), \
|
|
||||||
PIRQ_PIC(B, 5), \
|
|
||||||
PIRQ_PIC(C, 7), \
|
|
||||||
PIRQ_PIC(D, 10), \
|
|
||||||
PIRQ_PIC(E, 11), \
|
|
||||||
PIRQ_PIC(F, 12), \
|
|
||||||
PIRQ_PIC(G, 14), \
|
|
||||||
PIRQ_PIC(H, 15)
|
|
||||||
|
|
||||||
#endif /* IRQROUTE_H */
|
|
||||||
@@ -1,42 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
|
||||||
* Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/device.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
|
||||||
* This is the earliest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_final is executed as one of the last items before loading the
|
|
||||||
* payload.
|
|
||||||
*
|
|
||||||
* This is the latest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_final(void *chip_info)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
.final = mainboard_final,
|
|
||||||
};
|
|
||||||
@@ -1,56 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2014 Intel Corporation
|
|
||||||
* Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/chip.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done before fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void early_mainboard_romstage_entry(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get function disables - most of these will be done automatically
|
|
||||||
* @param fd_mask
|
|
||||||
* @param fd2_mask
|
|
||||||
*/
|
|
||||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done after fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void late_mainboard_romstage_entry(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
|
||||||
{
|
|
||||||
printk(BIOS_NOTICE, "This is the OpenCellular Rotundu GBC board.\n");
|
|
||||||
}
|
|
||||||
@@ -1,85 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
## Copyright (C) 2014 Intel Corporation
|
|
||||||
## Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
chip soc/intel/fsp_baytrail
|
|
||||||
|
|
||||||
#### ACPI Register Settings ####
|
|
||||||
register "fadt_pm_profile" = "PM_UNSPECIFIED"
|
|
||||||
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
|
|
||||||
|
|
||||||
#### FSP register settings ####
|
|
||||||
register "PcdSataMode" = "SATA_MODE_AHCI"
|
|
||||||
register "PcdMrcInitSPDAddr1" = "0xa0"
|
|
||||||
register "PcdMrcInitSPDAddr2" = "0xa2"
|
|
||||||
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
|
|
||||||
register "PcdeMMCBootMode" = "EMMC_DISABLED"
|
|
||||||
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
|
|
||||||
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
|
|
||||||
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
|
|
||||||
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
|
|
||||||
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
|
|
||||||
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
|
|
||||||
register "EnableMemoryDown" = "MEMORY_DOWN_DISABLE"
|
|
||||||
register "DIMM0Enable" = "DIMM0_ENABLE"
|
|
||||||
register "DIMM1Enable" = "DIMM1_DISABLE"
|
|
||||||
|
|
||||||
device cpu_cluster 0 on
|
|
||||||
device lapic 0 on end
|
|
||||||
end
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
device pci 00.0 on end # 8086 0F00 - SoC router
|
|
||||||
device pci 02.0 on end # 8086 0F31 - GFX
|
|
||||||
device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
|
|
||||||
|
|
||||||
device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
|
|
||||||
device pci 11.0 off end # 8086 0F15 - SDIO Port (SD2 pins)
|
|
||||||
device pci 12.0 off end # 8086 0F16 - SD Port (SD3 pins)
|
|
||||||
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
|
|
||||||
device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
|
|
||||||
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
|
|
||||||
device pci 16.0 off end # 8086 0F37 - OTG controller
|
|
||||||
device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
|
|
||||||
device pci 18.0 on end # 8086 0F40 - SIO - DMA
|
|
||||||
device pci 18.1 on end # 8086 0F41 - I2C Port 1
|
|
||||||
device pci 18.2 off end # 8086 0F42 - I2C Port 2
|
|
||||||
device pci 18.3 on end # 8086 0F43 - I2C Port 3
|
|
||||||
device pci 18.4 off end # 8086 0F44 - I2C Port 4
|
|
||||||
device pci 18.5 off end # 8086 0F45 - I2C Port 5
|
|
||||||
device pci 18.6 off end # 8086 0F46 - I2C Port 6
|
|
||||||
device pci 18.7 off end # 8086 0F47 - I2C Port 7
|
|
||||||
device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
|
|
||||||
device pci 1b.0 off end # 8086 0F04 - HD Audio
|
|
||||||
device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (RADIO CARD)
|
|
||||||
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (GBE PHY 1)
|
|
||||||
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (GBE PHY 2)
|
|
||||||
device pci 1c.3 off end # 8086 0F4E - PCIe Root Port 4 (NC)
|
|
||||||
device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
|
|
||||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
|
|
||||||
device pci 1e.1 off end # 8086 0F08 - PWM 1
|
|
||||||
device pci 1e.2 off end # 8086 0F09 - PWM 2
|
|
||||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1
|
|
||||||
device pci 1e.4 off end # 8086 0F0C - HSUART 2
|
|
||||||
device pci 1e.5 off end # 8086 0F0E - SPI
|
|
||||||
device pci 1f.0 on
|
|
||||||
chip drivers/pc80/tpm
|
|
||||||
device pnp 0c31.0 on end
|
|
||||||
end
|
|
||||||
end # 8086 0F1C - LPC bridge
|
|
||||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,362 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include "../../irqroute.h"
|
|
||||||
|
|
||||||
/* NCORE GPIOs */
|
|
||||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
|
||||||
|
|
||||||
GPIO_FUNC2, /* GPIO 0 */
|
|
||||||
GPIO_FUNC2, /* GPIO 1 */
|
|
||||||
GPIO_FUNC2, /* GPIO 2 */
|
|
||||||
GPIO_FUNC2, /* GPIO 3 */
|
|
||||||
GPIO_FUNC2, /* GPIO 4 */
|
|
||||||
GPIO_FUNC2, /* GPIO 5 */
|
|
||||||
GPIO_FUNC2, /* GPIO 6 */
|
|
||||||
GPIO_FUNC2, /* GPIO 7 */
|
|
||||||
GPIO_FUNC2, /* GPIO 8 */
|
|
||||||
GPIO_FUNC2, /* GPIO 9 */
|
|
||||||
GPIO_FUNC2, /* GPIO 10 */
|
|
||||||
GPIO_FUNC2, /* GPIO 11 */
|
|
||||||
GPIO_FUNC2, /* GPIO 12 */
|
|
||||||
GPIO_FUNC2, /* GPIO 13 */
|
|
||||||
GPIO_FUNC2, /* GPIO 14 */
|
|
||||||
GPIO_FUNC2, /* GPIO 15 */
|
|
||||||
GPIO_FUNC2, /* GPIO 16 */
|
|
||||||
GPIO_FUNC2, /* GPIO 17 */
|
|
||||||
GPIO_FUNC2, /* GPIO 18 */
|
|
||||||
GPIO_FUNC2, /* GPIO 19 */
|
|
||||||
GPIO_FUNC2, /* GPIO 20 */
|
|
||||||
GPIO_FUNC2, /* GPIO 21 */
|
|
||||||
GPIO_FUNC2, /* GPIO 22 */
|
|
||||||
GPIO_FUNC2, /* GPIO 23 */
|
|
||||||
GPIO_FUNC2, /* GPIO 24 */
|
|
||||||
GPIO_FUNC2, /* GPIO 25 */
|
|
||||||
GPIO_FUNC2, /* GPIO 26 */
|
|
||||||
GPIO_END};
|
|
||||||
|
|
||||||
/* SCORE GPIOs (GPIO_S0_SC_XX) */
|
|
||||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[000] SATA_GP[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[002] SATA_LED# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
|
|
||||||
GPIO_FUNC2,
|
|
||||||
/* GPIO_S0_SC[007] RESERVED SD3_WP */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[027] SD2_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[028] SD2_D[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[029] SD2_D[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[030] SD2_D[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[031] SD2_D[3]_CD# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[032] SD2_CMD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[033] SD3_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[034] SD3_D[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[035] SD3_D[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[036] SD3_D[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[037] SD3_D[3] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[038] SD3_CD# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[039] SD3_CMD */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[040] SD3_1P8EN */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[041] SD3_PWREN# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[042] ILB_LPC_AD[0] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[043] ILB_LPC_AD[1] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[044] ILB_LPC_AD[2] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[045] ILB_LPC_AD[3] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[046] ILB_LPC_FRAME# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[051] PCU_SMB_DATA */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[052] PCU_SMB_CLK */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[053] PCU_SMB_ALERT# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[055] RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[056] RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[057] PCU_UART_TXD */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[058] RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[059] RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[060] RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[061] PCU_UART_RXD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[066] SIO_SPI_CS# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[067] SIO_SPI_MISO */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[068] SIO_SPI_MOSI */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[069] SIO_SPI_CLK */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[072] SIO_UART1_RTS# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[073] SIO_UART1_CTS# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[074] SIO_UART2_RXD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[075] SIO_UART2_TXD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[076] SIO_UART2_RTS# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[077] SIO_UART2_CTS# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[078] SIO_I2C0_DATA */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[079] SIO_I2C0_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[080] SIO_I2C1_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[082] SIO_I2C2_DATA */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[083] SIO_I2C2_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[084] SIO_I2C3_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[085] SIO_I2C3_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[086] SIO_I2C4_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[087] SIO_I2C4_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[088] SIO_I2C5_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[089] SIO_I2C5_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
|
|
||||||
GPIO_NC,
|
|
||||||
/* RESERVED GPIO_S0_SC[092] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* RESERVED GPIO_S0_SC[093] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[094] SIO_PWM[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[095] SIO_PWM[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/
|
|
||||||
GPIO_END};
|
|
||||||
|
|
||||||
/* SSUS GPIOs (GPIO_S5) */
|
|
||||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[00] RESERVED- */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[10] RESERVED RESERVED RESERVED*/
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* PMC_SUSPWRDNACK GPIO_S5[11]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* PMC_SUSCLK[0] GPIO_S5[12]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* RESERVED GPIO_S5[13]*/
|
|
||||||
GPIO_FUNC2,
|
|
||||||
/* RESERVED GPIO_S5[14] USB_ULPI_RST#*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* PMC_PWRBTN# GPIO_S5[16]*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* RESERVED GPIO_S5[17]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* PMC_SUS_STAT# GPIO_S5[18]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* USB_OC[0]# GPIO_S5[19]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* USB_OC[1]# GPIO_S5[20]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* PCU_SPI_CS[1]# GPIO_S5[21]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/
|
|
||||||
GPIO_END};
|
|
||||||
|
|
||||||
static struct soc_gpio_config gpio_config = {
|
|
||||||
.ncore = gpncore_gpio_map,
|
|
||||||
.score = gpscore_gpio_map,
|
|
||||||
.ssus = gpssus_gpio_map,
|
|
||||||
.core_dirq = NULL,
|
|
||||||
.sus_dirq = NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; }
|
|
||||||
@@ -1,85 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
## Copyright (C) 2014 Intel Corporation
|
|
||||||
## Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
chip soc/intel/fsp_baytrail
|
|
||||||
|
|
||||||
#### ACPI Register Settings ####
|
|
||||||
register "fadt_pm_profile" = "PM_UNSPECIFIED"
|
|
||||||
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
|
|
||||||
|
|
||||||
#### FSP register settings ####
|
|
||||||
register "PcdSataMode" = "SATA_MODE_AHCI"
|
|
||||||
register "PcdMrcInitSPDAddr1" = "0xa0"
|
|
||||||
register "PcdMrcInitSPDAddr2" = "0xa2"
|
|
||||||
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
|
|
||||||
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
|
|
||||||
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
|
|
||||||
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
|
|
||||||
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
|
|
||||||
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
|
|
||||||
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
|
|
||||||
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
|
|
||||||
register "EnableMemoryDown" = "MEMORY_DOWN_DISABLE"
|
|
||||||
register "DIMM0Enable" = "DIMM0_ENABLE"
|
|
||||||
register "DIMM1Enable" = "DIMM1_DISABLE"
|
|
||||||
|
|
||||||
device cpu_cluster 0 on
|
|
||||||
device lapic 0 on end
|
|
||||||
end
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
device pci 00.0 on end # 8086 0F00 - SoC router
|
|
||||||
device pci 02.0 on end # 8086 0F31 - GFX
|
|
||||||
device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
|
|
||||||
|
|
||||||
device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
|
|
||||||
device pci 11.0 off end # 8086 0F15 - SDIO Port (SD2 pins)
|
|
||||||
device pci 12.0 off end # 8086 0F16 - SD Port (SD3 pins)
|
|
||||||
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
|
|
||||||
device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
|
|
||||||
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
|
|
||||||
device pci 16.0 off end # 8086 0F37 - OTG controller
|
|
||||||
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
|
|
||||||
device pci 18.0 on end # 8086 0F40 - SIO - DMA
|
|
||||||
device pci 18.1 on end # 8086 0F41 - I2C Port 1
|
|
||||||
device pci 18.2 off end # 8086 0F42 - I2C Port 2
|
|
||||||
device pci 18.3 on end # 8086 0F43 - I2C Port 3
|
|
||||||
device pci 18.4 off end # 8086 0F44 - I2C Port 4
|
|
||||||
device pci 18.5 off end # 8086 0F45 - I2C Port 5
|
|
||||||
device pci 18.6 off end # 8086 0F46 - I2C Port 6
|
|
||||||
device pci 18.7 off end # 8086 0F47 - I2C Port 7
|
|
||||||
device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
|
|
||||||
device pci 1b.0 off end # 8086 0F04 - HD Audio
|
|
||||||
device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (RADIO CARD)
|
|
||||||
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (GBE PHY 1)
|
|
||||||
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (GBE PHY 2)
|
|
||||||
device pci 1c.3 off end # 8086 0F4E - PCIe Root Port 4 (NC)
|
|
||||||
device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
|
|
||||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
|
|
||||||
device pci 1e.1 off end # 8086 0F08 - PWM 1
|
|
||||||
device pci 1e.2 off end # 8086 0F09 - PWM 2
|
|
||||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1
|
|
||||||
device pci 1e.4 off end # 8086 0F0C - HSUART 2
|
|
||||||
device pci 1e.5 off end # 8086 0F0E - SPI
|
|
||||||
device pci 1f.0 on
|
|
||||||
chip drivers/pc80/tpm
|
|
||||||
device pnp 0c31.0 on end
|
|
||||||
end
|
|
||||||
end # 8086 0F1C - LPC bridge
|
|
||||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,365 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
* Copyright (C) 2017-present Facebook, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include "../../irqroute.h"
|
|
||||||
|
|
||||||
#define GPIO_FUNC3_PULL_UP_20K GPIO_FUNC(3, PULL_UP, 20K)
|
|
||||||
#define GPIO_FUNC3_PULL_DOWN_20K GPIO_FUNC(3, PULL_DOWN, 20K)
|
|
||||||
|
|
||||||
/* NCORE GPIOs */
|
|
||||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
|
||||||
|
|
||||||
GPIO_FUNC2, /* GPIO 0 */
|
|
||||||
GPIO_FUNC2, /* GPIO 1 */
|
|
||||||
GPIO_FUNC2, /* GPIO 2 */
|
|
||||||
GPIO_FUNC2, /* GPIO 3 */
|
|
||||||
GPIO_FUNC2, /* GPIO 4 */
|
|
||||||
GPIO_FUNC2, /* GPIO 5 */
|
|
||||||
GPIO_FUNC2, /* GPIO 6 */
|
|
||||||
GPIO_FUNC2, /* GPIO 7 */
|
|
||||||
GPIO_FUNC2, /* GPIO 8 */
|
|
||||||
GPIO_FUNC2, /* GPIO 9 */
|
|
||||||
GPIO_FUNC2, /* GPIO 10 */
|
|
||||||
GPIO_FUNC2, /* GPIO 11 */
|
|
||||||
GPIO_FUNC2, /* GPIO 12 */
|
|
||||||
GPIO_FUNC2, /* GPIO 13 */
|
|
||||||
GPIO_FUNC2, /* GPIO 14 */
|
|
||||||
GPIO_FUNC2, /* GPIO 15 */
|
|
||||||
GPIO_FUNC2, /* GPIO 16 */
|
|
||||||
GPIO_FUNC2, /* GPIO 17 */
|
|
||||||
GPIO_FUNC2, /* GPIO 18 */
|
|
||||||
GPIO_FUNC2, /* GPIO 19 */
|
|
||||||
GPIO_FUNC2, /* GPIO 20 */
|
|
||||||
GPIO_FUNC2, /* GPIO 21 */
|
|
||||||
GPIO_FUNC2, /* GPIO 22 */
|
|
||||||
GPIO_FUNC2, /* GPIO 23 */
|
|
||||||
GPIO_FUNC2, /* GPIO 24 */
|
|
||||||
GPIO_FUNC2, /* GPIO 25 */
|
|
||||||
GPIO_FUNC2, /* GPIO 26 */
|
|
||||||
GPIO_END};
|
|
||||||
|
|
||||||
/* SCORE GPIOs (GPIO_S0_SC_XX) */
|
|
||||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[000] SATA_GP[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[002] SATA_LED# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
|
|
||||||
GPIO_FUNC2,
|
|
||||||
/* GPIO_S0_SC[007] RESERVED SD3_WP */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
|
|
||||||
GPIO_FUNC3_PULL_DOWN_20K,
|
|
||||||
/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
|
|
||||||
GPIO_FUNC3_PULL_UP_20K,
|
|
||||||
/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
|
|
||||||
GPIO_FUNC3_PULL_DOWN_20K,
|
|
||||||
/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[027] SD2_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[028] SD2_D[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[029] SD2_D[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[030] SD2_D[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[031] SD2_D[3]_CD# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[032] SD2_CMD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[033] SD3_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[034] SD3_D[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[035] SD3_D[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[036] SD3_D[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[037] SD3_D[3] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[038] SD3_CD# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[039] SD3_CMD */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[040] SD3_1P8EN */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[041] SD3_PWREN# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[042] ILB_LPC_AD[0] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[043] ILB_LPC_AD[1] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[044] ILB_LPC_AD[2] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[045] ILB_LPC_AD[3] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[046] ILB_LPC_FRAME# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[051] PCU_SMB_DATA */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[052] PCU_SMB_CLK */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[053] PCU_SMB_ALERT# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[055] RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[056] RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[057] PCU_UART_TXD */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[058] RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[059] RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[060] RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[061] PCU_UART_RXD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[066] SIO_SPI_CS# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[067] SIO_SPI_MISO */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[068] SIO_SPI_MOSI */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[069] SIO_SPI_CLK */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[072] SIO_UART1_RTS# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S0_SC[073] SIO_UART1_CTS# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[074] SIO_UART2_RXD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[075] SIO_UART2_TXD */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[076] SIO_UART2_RTS# */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[077] SIO_UART2_CTS# */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[078] SIO_I2C0_DATA */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[079] SIO_I2C0_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[080] SIO_I2C1_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[082] SIO_I2C2_DATA */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S0_SC[083] SIO_I2C2_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[084] SIO_I2C3_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[085] SIO_I2C3_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[086] SIO_I2C4_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[087] SIO_I2C4_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[088] SIO_I2C5_DATA */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[089] SIO_I2C5_CLK */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
|
|
||||||
GPIO_NC,
|
|
||||||
/* RESERVED GPIO_S0_SC[092] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* RESERVED GPIO_S0_SC[093] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[094] SIO_PWM[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[095] SIO_PWM[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/
|
|
||||||
GPIO_END};
|
|
||||||
|
|
||||||
/* SSUS GPIOs (GPIO_S5) */
|
|
||||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[00] RESERVED- */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[10] RESERVED RESERVED RESERVED*/
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* PMC_SUSPWRDNACK GPIO_S5[11]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* PMC_SUSCLK[0] GPIO_S5[12]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* RESERVED GPIO_S5[13]*/
|
|
||||||
GPIO_FUNC2,
|
|
||||||
/* RESERVED GPIO_S5[14] USB_ULPI_RST#*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* PMC_PWRBTN# GPIO_S5[16]*/
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* RESERVED GPIO_S5[17]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* PMC_SUS_STAT# GPIO_S5[18]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* USB_OC[0]# GPIO_S5[19]*/
|
|
||||||
GPIO_FUNC0,
|
|
||||||
/* USB_OC[1]# GPIO_S5[20]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* PCU_SPI_CS[1]# GPIO_S5[21]*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT,
|
|
||||||
/* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_FUNC1,
|
|
||||||
/* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/
|
|
||||||
GPIO_NC,
|
|
||||||
/* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/
|
|
||||||
GPIO_END};
|
|
||||||
|
|
||||||
static struct soc_gpio_config gpio_config = {
|
|
||||||
.ncore = gpncore_gpio_map,
|
|
||||||
.score = gpscore_gpio_map,
|
|
||||||
.ssus = gpssus_gpio_map,
|
|
||||||
.core_dirq = NULL,
|
|
||||||
.sus_dirq = NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; }
|
|
||||||
@@ -1,30 +0,0 @@
|
|||||||
FLASH 16M {
|
|
||||||
SI_ALL@0x0 0x300000 {
|
|
||||||
SI_DESC@0x0 0x1000
|
|
||||||
SI_ME@0x1000 0x2ff000
|
|
||||||
}
|
|
||||||
SI_BIOS@0x300000 0xd00000 {
|
|
||||||
RW_SECTION_B@0x0 0x400000 {
|
|
||||||
VBLOCK_B@0x0 0x10000
|
|
||||||
FW_MAIN_B(CBFS)@0x10000 0x3effc0
|
|
||||||
RW_FWID_B@0x3fffc0 0x40
|
|
||||||
}
|
|
||||||
RW_SECTION_A@0x400000 0x400000 {
|
|
||||||
VBLOCK_A@0x0 0x10000
|
|
||||||
FW_MAIN_A(CBFS)@0x10000 0x3effc0
|
|
||||||
RW_FWID_A@0x3fffc0 0x40
|
|
||||||
}
|
|
||||||
RW_MRC_CACHE@0x800000 0x10000
|
|
||||||
RW_VPD(PRESERVE)@0x810000 0x2000
|
|
||||||
WP_RO@0x812000 0x4ee000 {
|
|
||||||
RO_VPD(PRESERVE)@0x0 0x4000
|
|
||||||
RO_SECTION@0x4000 0x4ea000 {
|
|
||||||
FMAP@0x0 0x800
|
|
||||||
RO_FRID@0x800 0x40
|
|
||||||
RO_FRID_PAD@0x840 0x7c0
|
|
||||||
GBB@0x1000 0xef000
|
|
||||||
COREBOOT(CBFS)@0xf0000 0x3fa000
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,30 +0,0 @@
|
|||||||
FLASH 8M {
|
|
||||||
SI_ALL@0x0 0x300000 {
|
|
||||||
SI_DESC@0x0 0x1000
|
|
||||||
SI_ME@0x1000 0x2ff000
|
|
||||||
}
|
|
||||||
SI_BIOS@0x300000 0x500000 {
|
|
||||||
RW_SECTION_B@0x0 0x150040 {
|
|
||||||
VBLOCK_B@0x0 0x10000
|
|
||||||
FW_MAIN_B(CBFS)@0x10000 0x140000
|
|
||||||
RW_FWID_B@0x150000 0x40
|
|
||||||
}
|
|
||||||
RW_SECTION_A@0x150040 0x150040 {
|
|
||||||
VBLOCK_A@0x0 0x10000
|
|
||||||
FW_MAIN_A(CBFS)@0x10000 0x140000
|
|
||||||
RW_FWID_A@0x150000 0x40
|
|
||||||
}
|
|
||||||
RW_MRC_CACHE@0x2a0080 0x10000
|
|
||||||
RW_VPD(PRESERVE)@0x2b0080 0x2000
|
|
||||||
WP_RO@0x2b2080 0x24df80 {
|
|
||||||
RO_VPD(PRESERVE)@0x0 0x4000
|
|
||||||
RO_SECTION@0x4000 0x249f80 {
|
|
||||||
FMAP@0x0 0x800
|
|
||||||
RO_FRID@0x800 0x40
|
|
||||||
RO_FRID_PAD@0x840 0x7c0
|
|
||||||
GBB@0x1000 0xef000
|
|
||||||
COREBOOT(CBFS)@0xf0000 0x159f80
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,59 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
if BOARD_SIEMENS_MC_TCU3
|
|
||||||
|
|
||||||
config BOARD_SPECIFIC_OPTIONS
|
|
||||||
def_bool y
|
|
||||||
select SOC_INTEL_FSP_BAYTRAIL
|
|
||||||
select BOARD_ROMSIZE_KB_16384
|
|
||||||
select HAVE_ACPI_TABLES
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
select ENABLE_BUILTIN_COM1
|
|
||||||
select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
|
|
||||||
select ENABLE_FSP_FAST_BOOT
|
|
||||||
select DRIVER_INTEL_I210
|
|
||||||
select SOC_INTEL_FSP_BAYTRAIL_MD
|
|
||||||
select USE_BLOBS
|
|
||||||
select CBFS_AUTOGEN_ATTRIBUTES
|
|
||||||
select USE_SIEMENS_HWILIB
|
|
||||||
select DRIVERS_I2C_PTN3460
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default "siemens/mc_tcu3"
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "MC_TCU3 (FSP)"
|
|
||||||
|
|
||||||
|
|
||||||
config MAX_CPUS
|
|
||||||
int
|
|
||||||
default 16
|
|
||||||
|
|
||||||
config CBFS_SIZE
|
|
||||||
hex
|
|
||||||
default 0x00e00000
|
|
||||||
|
|
||||||
config FSP_PACKAGE_DEFAULT
|
|
||||||
bool "Configure defaults for the Intel FSP package"
|
|
||||||
default n
|
|
||||||
|
|
||||||
config VGA_BIOS
|
|
||||||
bool
|
|
||||||
default y if FSP_PACKAGE_DEFAULT
|
|
||||||
|
|
||||||
endif # BOARD_SIEMENS_MC_TCU3
|
|
||||||
@@ -1,2 +0,0 @@
|
|||||||
config BOARD_SIEMENS_MC_TCU3
|
|
||||||
bool "MB TCU3"
|
|
||||||
@@ -1,19 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013 Google Inc.
|
|
||||||
## Copyright (C) 2017 Siemens AG
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
ramstage-y += gpio.c
|
|
||||||
ramstage-y += irqroute.c
|
|
||||||
ramstage-y += lcd_panel.c
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; version 2 of
|
|
||||||
* the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
Device (PWRB)
|
|
||||||
{
|
|
||||||
Name(_HID, EisaId("PNP0C0C"))
|
|
||||||
}
|
|
||||||
@@ -1,58 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Google Inc.
|
|
||||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <types.h>
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <arch/ioapic.h>
|
|
||||||
#include <arch/smp/mpspec.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
#include <soc/nvs.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
|
|
||||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
|
||||||
{
|
|
||||||
acpi_init_gnvs(gnvs);
|
|
||||||
|
|
||||||
/* Enable USB ports in S3 */
|
|
||||||
gnvs->s3u0 = 1;
|
|
||||||
gnvs->s3u1 = 1;
|
|
||||||
|
|
||||||
/* Disable USB ports in S5 */
|
|
||||||
gnvs->s5u0 = 0;
|
|
||||||
gnvs->s5u1 = 0;
|
|
||||||
|
|
||||||
/* TPM Present */
|
|
||||||
gnvs->tpmp = 0;
|
|
||||||
|
|
||||||
/* Enable DPTF */
|
|
||||||
gnvs->dpte = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long acpi_fill_madt(unsigned long current)
|
|
||||||
{
|
|
||||||
/* Local APICs */
|
|
||||||
current = acpi_create_madt_lapics(current);
|
|
||||||
|
|
||||||
/* IOAPIC */
|
|
||||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
|
||||||
2, IO_APIC_ADDR, 0);
|
|
||||||
|
|
||||||
current = acpi_madt_irq_overrides(current);
|
|
||||||
|
|
||||||
return current;
|
|
||||||
}
|
|
||||||
@@ -1,4 +0,0 @@
|
|||||||
Board name: TCU3
|
|
||||||
Category: misc
|
|
||||||
ROM protocol: SPI
|
|
||||||
ROM socketed: n
|
|
||||||
@@ -1,119 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2007-2008 coresystems GmbH
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
entries
|
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
|
||||||
#0 8 r 0 seconds
|
|
||||||
#8 8 r 0 alarm_seconds
|
|
||||||
#16 8 r 0 minutes
|
|
||||||
#24 8 r 0 alarm_minutes
|
|
||||||
#32 8 r 0 hours
|
|
||||||
#40 8 r 0 alarm_hours
|
|
||||||
#48 8 r 0 day_of_week
|
|
||||||
#56 8 r 0 day_of_month
|
|
||||||
#64 8 r 0 month
|
|
||||||
#72 8 r 0 year
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register A
|
|
||||||
#80 4 r 0 rate_select
|
|
||||||
#84 3 r 0 REF_Clock
|
|
||||||
#87 1 r 0 UIP
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register B
|
|
||||||
#88 1 r 0 auto_switch_DST
|
|
||||||
#89 1 r 0 24_hour_mode
|
|
||||||
#90 1 r 0 binary_values_enable
|
|
||||||
#91 1 r 0 square-wave_out_enable
|
|
||||||
#92 1 r 0 update_finished_enable
|
|
||||||
#93 1 r 0 alarm_interrupt_enable
|
|
||||||
#94 1 r 0 periodic_interrupt_enable
|
|
||||||
#95 1 r 0 disable_clock_updates
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register C
|
|
||||||
#96 4 r 0 status_c_rsvd
|
|
||||||
#100 1 r 0 uf_flag
|
|
||||||
#101 1 r 0 af_flag
|
|
||||||
#102 1 r 0 pf_flag
|
|
||||||
#103 1 r 0 irqf_flag
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register D
|
|
||||||
#104 7 r 0 status_d_rsvd
|
|
||||||
#111 1 r 0 valid_cmos_ram
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Diagnostic Status Register
|
|
||||||
#112 8 r 0 diag_rsvd1
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
0 120 r 0 reserved_memory
|
|
||||||
#120 264 r 0 unused
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
388 4 h 0 reboot_counter
|
|
||||||
#390 2 r 0 unused?
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# coreboot config options: console
|
|
||||||
#392 3 r 0 unused
|
|
||||||
395 4 e 6 debug_level
|
|
||||||
#399 1 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: cpu
|
|
||||||
400 1 e 2 hyper_threading
|
|
||||||
#401 7 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
|
||||||
408 1 e 1 nmi
|
|
||||||
409 2 e 7 power_on_after_fail
|
|
||||||
#411 5 r 0 unused
|
|
||||||
|
|
||||||
# MRC Scrambler Seed values
|
|
||||||
896 32 r 0 mrc_scrambler_seed
|
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
#1000 24 r 0 amd_reserved
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 0 Emergency
|
|
||||||
6 1 Alert
|
|
||||||
6 2 Critical
|
|
||||||
6 3 Error
|
|
||||||
6 4 Warning
|
|
||||||
6 5 Notice
|
|
||||||
6 6 Info
|
|
||||||
6 7 Debug
|
|
||||||
6 8 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 415 984
|
|
||||||
@@ -1,83 +0,0 @@
|
|||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
chip soc/intel/fsp_baytrail
|
|
||||||
|
|
||||||
#### ACPI Register Settings ####
|
|
||||||
register "fadt_pm_profile" = "PM_MOBILE"
|
|
||||||
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
|
|
||||||
|
|
||||||
#### FSP register settings ####
|
|
||||||
register "PcdSataMode" = "SATA_MODE_AHCI"
|
|
||||||
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
|
|
||||||
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
|
|
||||||
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
|
|
||||||
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
|
|
||||||
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
|
|
||||||
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
|
|
||||||
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
|
|
||||||
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
|
|
||||||
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
|
|
||||||
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
|
|
||||||
|
|
||||||
device cpu_cluster 0 on
|
|
||||||
device lapic 0 on end
|
|
||||||
end
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
device pci 00.0 on end # 8086 0F00 - SoC router
|
|
||||||
device pci 02.0 on end # 8086 0F31 - GFX
|
|
||||||
device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
|
|
||||||
|
|
||||||
device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
|
|
||||||
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
|
|
||||||
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
|
|
||||||
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
|
|
||||||
device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
|
|
||||||
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
|
|
||||||
device pci 16.0 off end # 8086 0F37 - OTG controller
|
|
||||||
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
|
|
||||||
device pci 18.0 on end # 8086 0F40 - SIO - DMA
|
|
||||||
device pci 18.1 on # 8086 0F41 - I2C Port 1
|
|
||||||
# Enable external display bridge (eDP to LVDS)
|
|
||||||
chip drivers/i2c/ptn3460
|
|
||||||
device i2c 0x20 on end # PTN3460 DP2LVDS Bridge
|
|
||||||
end
|
|
||||||
end
|
|
||||||
device pci 18.2 on end # 8086 0F42 - I2C Port 2
|
|
||||||
device pci 18.3 on end # 8086 0F43 - I2C Port 3
|
|
||||||
device pci 18.4 on end # 8086 0F44 - I2C Port 4
|
|
||||||
device pci 18.5 on end # 8086 0F45 - I2C Port 5
|
|
||||||
device pci 18.6 on end # 8086 0F46 - I2C Port 6
|
|
||||||
device pci 18.7 on end # 8086 0F47 - I2C Port 7
|
|
||||||
device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
|
|
||||||
device pci 1b.0 on end # 8086 0F04 - HD Audio
|
|
||||||
device pci 1c.0 on # 8086 0F48 - PCIe Root Port 1 (x4 slot)
|
|
||||||
device pci 0.0 on end # 8086 1538 - Intel i210 MACPHY
|
|
||||||
end
|
|
||||||
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
|
|
||||||
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
|
|
||||||
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
|
|
||||||
device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
|
|
||||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
|
|
||||||
device pci 1e.1 on end # 8086 0F08 - PWM 1
|
|
||||||
device pci 1e.2 on end # 8086 0F09 - PWM 2
|
|
||||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1
|
|
||||||
device pci 1e.4 on end # 8086 0F0C - HSUART 2
|
|
||||||
device pci 1e.5 on end # 8086 0F0E - SPI
|
|
||||||
device pci 1f.0 on end # 8086 0F1C - LPC bridge
|
|
||||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,54 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INCLUDE_LPE 1
|
|
||||||
#define INCLUDE_SCC 1
|
|
||||||
#define INCLUDE_EHCI 1
|
|
||||||
#define INCLUDE_XHCI 1
|
|
||||||
#define INCLUDE_LPSS 1
|
|
||||||
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20110725 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Some generic macros
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
|
||||||
|
|
||||||
// global NVS and variables
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
|
||||||
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Chipset specific sleep states */
|
|
||||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
|
|
||||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
|
||||||
{
|
|
||||||
acpi_header_t *header = &(fadt->header);
|
|
||||||
|
|
||||||
acpi_fill_in_fadt(fadt,facs,dsdt);
|
|
||||||
|
|
||||||
/* Platform specific customizations go here */
|
|
||||||
|
|
||||||
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
|
||||||
}
|
|
||||||
@@ -1,220 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
/* NCORE GPIOs */
|
|
||||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
|
||||||
GPIO_FUNC2, /* GPIO 0 */
|
|
||||||
GPIO_FUNC2, /* GPIO 1 */
|
|
||||||
GPIO_FUNC2, /* GPIO 2 */
|
|
||||||
GPIO_FUNC2, /* GPIO 3 */
|
|
||||||
GPIO_FUNC2, /* GPIO 4 */
|
|
||||||
GPIO_FUNC2, /* GPIO 5 */
|
|
||||||
GPIO_FUNC2, /* GPIO 6 */
|
|
||||||
GPIO_FUNC2, /* GPIO 7 */
|
|
||||||
GPIO_FUNC2, /* GPIO 8 */
|
|
||||||
GPIO_FUNC2, /* GPIO 9 */
|
|
||||||
GPIO_FUNC2, /* GPIO 10 */
|
|
||||||
GPIO_FUNC2, /* GPIO 11 */
|
|
||||||
GPIO_FUNC2, /* GPIO 12 */
|
|
||||||
GPIO_FUNC2, /* GPIO 13 */
|
|
||||||
GPIO_FUNC2, /* GPIO 14 */
|
|
||||||
GPIO_FUNC2, /* GPIO 15 */
|
|
||||||
GPIO_FUNC2, /* GPIO 16 */
|
|
||||||
GPIO_FUNC2, /* GPIO 17 */
|
|
||||||
GPIO_FUNC2, /* GPIO 18 */
|
|
||||||
GPIO_FUNC2, /* GPIO 19 */
|
|
||||||
GPIO_FUNC2, /* GPIO 20 */
|
|
||||||
GPIO_FUNC2, /* GPIO 21 */
|
|
||||||
GPIO_FUNC2, /* GPIO 22 */
|
|
||||||
GPIO_FUNC2, /* GPIO 23 */
|
|
||||||
GPIO_FUNC2, /* GPIO 24 */
|
|
||||||
GPIO_FUNC2, /* GPIO 25 */
|
|
||||||
GPIO_FUNC2, /* GPIO 26 */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SCORE GPIOs (GPIO_S0_SC_XX)*/
|
|
||||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[000] SATA_GP[0] .*/
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] .*/
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[007] RESERVED SD3_WP */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
|
|
||||||
GPIO_FUNC2, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[027] SD2_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[028] SD2_D[0] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[029] SD2_D[1] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[030] SD2_D[2] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[031] SD2_D[3]_CD# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[032] SD2_CMD */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[040] SD3_1P8EN */
|
|
||||||
GPIO_NC, /* GPIO_S0_SC[041] SD3_PWREN# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED */
|
|
||||||
GPIO_OUT_HIGH, /* GPIO_S0_SC[055] RESERVED */
|
|
||||||
GPIO_FUNC0, /* GPIO_S0_SC[056] RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD */
|
|
||||||
GPIO_OUT_LOW, /* GPIO_S0_SC[058] RESERVED */
|
|
||||||
GPIO_OUT_LOW, /* GPIO_S0_SC[059] RESERVED */
|
|
||||||
GPIO_OUT_LOW, /* GPIO_S0_SC[060] RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[066] SIO_SPI_CS# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[067] SIO_SPI_MISO */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[068] SIO_SPI_MOSI */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[069] SIO_SPI_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD */
|
|
||||||
GPIO_OUT_LOW, /* GPIO_S0_SC[075] SIO_UART2_TXD */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[080] SIO_I2C1_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[084] SIO_I2C3_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[085] SIO_I2C3_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[086] SIO_I2C4_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[087] SIO_I2C4_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[088] SIO_I2C5_DATA */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[089] SIO_I2C5_CLK */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
|
|
||||||
GPIO_FUNC1, /* RESERVED GPIO_S0_SC[092] */
|
|
||||||
GPIO_FUNC1, /* RESERVED GPIO_S0_SC[093] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[094] SIO_PWM[0] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[095] SIO_PWM[1] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
|
|
||||||
GPIO_FUNC1, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SSUS GPIOs (GPIO_S5) */
|
|
||||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[00] RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */
|
|
||||||
GPIO_OUT_HIGH, /* GPIO_S5[10] RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */
|
|
||||||
GPIO_DEFAULT, /* PMC_SUSCLK[0] GPIO_S5[12] - - */
|
|
||||||
GPIO_DEFAULT, /* RESERVED GPIO_S5[13] - - */
|
|
||||||
GPIO_DEFAULT, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - */
|
|
||||||
GPIO_DEFAULT, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - */
|
|
||||||
GPIO_DEFAULT, /* PMC_PWRBTN# GPIO_S5[16] - - */
|
|
||||||
GPIO_DEFAULT, /* RESERVED GPIO_S5[17] - - */
|
|
||||||
GPIO_DEFAULT, /* PMC_SUS_STAT# GPIO_S5[18] - - */
|
|
||||||
GPIO_DEFAULT, /* USB_OC[0]# GPIO_S5[19] - - */
|
|
||||||
GPIO_DEFAULT, /* USB_OC[1]# GPIO_S5[20] - - */
|
|
||||||
GPIO_DEFAULT, /* PCU_SPI_CS[1]# GPIO_S5[21] - */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[27] RESERVED RESERVED ESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
|
|
||||||
GPIO_OUT_LOW, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_10K, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_20K, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_20K, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_20K, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED */
|
|
||||||
GPIO_INPUT_PD_20K, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED */
|
|
||||||
GPIO_END
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct soc_gpio_config gpio_config = {
|
|
||||||
.ncore = gpncore_gpio_map,
|
|
||||||
.score = gpscore_gpio_map,
|
|
||||||
.ssus = gpssus_gpio_map,
|
|
||||||
.core_dirq = NULL,
|
|
||||||
.sus_dirq = NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct soc_gpio_config* mainboard_get_gpios(void)
|
|
||||||
{
|
|
||||||
return &gpio_config;
|
|
||||||
}
|
|
||||||
@@ -1,18 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "irqroute.h"
|
|
||||||
|
|
||||||
DEFINE_IRQ_ROUTES;
|
|
||||||
@@ -1,82 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef IRQROUTE_H
|
|
||||||
#define IRQROUTE_H
|
|
||||||
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/irq.h>
|
|
||||||
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
*IR02h GFX INT(A) - PIRQ A
|
|
||||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
|
||||||
*IR11h SDIO INT(A) - PIRQ B
|
|
||||||
*IR12h SD INT(A) - PIRQ C
|
|
||||||
*IR13h SATA INT(A) - PIRQ D
|
|
||||||
*IR14h XHCI INT(A) - PIRQ E
|
|
||||||
*IR15h LP Audio INT(A) - PIRQ F
|
|
||||||
*IR17h MMC INT(A) - PIRQ F
|
|
||||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
|
||||||
*IR1Ah TXE INT(A) - PIRQ F
|
|
||||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
|
||||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
|
||||||
*IR1Dh EHCI INT(A) - PIRQ D
|
|
||||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
|
||||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCIe bridge routing */
|
|
||||||
#define BRIDGE1_DEV PCIE_DEV
|
|
||||||
|
|
||||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
|
||||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
|
||||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
|
||||||
|
|
||||||
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
|
|
||||||
#define PCI_DEV_PIRQ_ROUTES \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
|
||||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
|
||||||
* Reserved: 0, 1, 2, 8, 13
|
|
||||||
* PS2 keyboard: 12
|
|
||||||
* ACPI/SCI: 9
|
|
||||||
* Floppy: 6
|
|
||||||
*/
|
|
||||||
#define PIRQ_PIC_ROUTES \
|
|
||||||
PIRQ_PIC(A, 4), \
|
|
||||||
PIRQ_PIC(B, 5), \
|
|
||||||
PIRQ_PIC(C, 7), \
|
|
||||||
PIRQ_PIC(D, 10), \
|
|
||||||
PIRQ_PIC(E, 11), \
|
|
||||||
PIRQ_PIC(F, 12), \
|
|
||||||
PIRQ_PIC(G, 14), \
|
|
||||||
PIRQ_PIC(H, 15)
|
|
||||||
|
|
||||||
#endif /* IRQROUTE_H */
|
|
||||||
@@ -1,173 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2014-2019 Siemens AG
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <drivers/i2c/ptn3460/ptn3460.h>
|
|
||||||
#include <hwilib.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <types.h>
|
|
||||||
|
|
||||||
#include "soc/gpio.h"
|
|
||||||
#include "lcd_panel.h"
|
|
||||||
|
|
||||||
# define MAX_HWI_NAME_LENGTH 20
|
|
||||||
|
|
||||||
/** \brief Reads GPIOs used for LCD panel encoding and returns the 4 bit value
|
|
||||||
* @param no parameters
|
|
||||||
* @return LCD panel type encoded in 4 bits
|
|
||||||
*/
|
|
||||||
static u8 get_lcd_panel_type(void)
|
|
||||||
{
|
|
||||||
u8 lcd_type_gpio;
|
|
||||||
|
|
||||||
lcd_type_gpio = ((read_ssus_gpio(LCD_TYPE_GPIO_BIT3) << 3) |
|
|
||||||
(read_ssus_gpio(LCD_TYPE_GPIO_BIT2) << 2) |
|
|
||||||
(read_ssus_gpio(LCD_TYPE_GPIO_BIT1) << 1) |
|
|
||||||
(read_ssus_gpio(LCD_TYPE_GPIO_BIT0)));
|
|
||||||
/* There is an inverter in this signals so we need to invert them as well */
|
|
||||||
return ((~lcd_type_gpio) & 0x0f);
|
|
||||||
}
|
|
||||||
/** \brief This function checks which LCD panel type is used with the mainboard
|
|
||||||
* and provides the name of the matching EDID data set in CBFS.
|
|
||||||
* @param Pointer to the filename in CBFS where the EDID data is located
|
|
||||||
* @return CB_SUCCESS on success otherwise CB_ERR
|
|
||||||
*/
|
|
||||||
static enum cb_err get_hwi_filename(char *hwi_block)
|
|
||||||
{
|
|
||||||
u8 lcd_type;
|
|
||||||
enum cb_err ret = CB_SUCCESS;
|
|
||||||
|
|
||||||
lcd_type = get_lcd_panel_type();
|
|
||||||
printk(BIOS_INFO, "LCD: Found panel type %d\n", lcd_type);
|
|
||||||
|
|
||||||
switch (lcd_type) {
|
|
||||||
case LCD_PANEL_TYPE_10_INCH:
|
|
||||||
strcpy(hwi_block, "hwinfo10.hex");
|
|
||||||
break;
|
|
||||||
case LCD_PANEL_TYPE_12_INCH:
|
|
||||||
strcpy(hwi_block, "hwinfo12.hex");
|
|
||||||
break;
|
|
||||||
case LCD_PANEL_TYPE_15_INCH:
|
|
||||||
strcpy(hwi_block, "hwinfo15.hex");
|
|
||||||
break;
|
|
||||||
case LCD_PANEL_TYPE_19_INCH:
|
|
||||||
strcpy(hwi_block, "hwinfo19.hex");
|
|
||||||
break;
|
|
||||||
case LCD_PANEL_TYPE_EDID:
|
|
||||||
strcpy(hwi_block, "hwinfo.hex");
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printk(BIOS_ERR, "LCD: No supported panel found.\n");
|
|
||||||
ret = CB_ERR;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460)
|
|
||||||
* @param edid_data pointer to EDID data in driver
|
|
||||||
*/
|
|
||||||
enum cb_err mb_get_edid(uint8_t edid_data[0x80])
|
|
||||||
{
|
|
||||||
char hwi_block[MAX_HWI_NAME_LENGTH];
|
|
||||||
|
|
||||||
if (get_hwi_filename(hwi_block) != CB_SUCCESS)
|
|
||||||
return CB_ERR;
|
|
||||||
|
|
||||||
if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) {
|
|
||||||
printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block);
|
|
||||||
return CB_ERR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get EDID data from hwinfo block */
|
|
||||||
if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) {
|
|
||||||
printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block);
|
|
||||||
return CB_ERR;
|
|
||||||
}
|
|
||||||
return CB_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460)
|
|
||||||
* which has to be used.
|
|
||||||
*/
|
|
||||||
uint8_t mb_select_edid_table(void)
|
|
||||||
{
|
|
||||||
return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */
|
|
||||||
}
|
|
||||||
|
|
||||||
/** \brief Function to enable mainboard to adjust the config data of PTN3460.
|
|
||||||
* @param *cfg_ptr Pointer to the PTN config structure to modify.
|
|
||||||
* @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated.
|
|
||||||
*/
|
|
||||||
int mb_adjust_cfg(struct ptn_3460_config *cfg)
|
|
||||||
{
|
|
||||||
char hwi_block[MAX_HWI_NAME_LENGTH];
|
|
||||||
uint8_t disp_con = 0, color_depth = 0;
|
|
||||||
uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0};
|
|
||||||
|
|
||||||
if (get_hwi_filename(hwi_block) != CB_SUCCESS)
|
|
||||||
return -1;
|
|
||||||
if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) {
|
|
||||||
printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) {
|
|
||||||
printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
if (hwilib_get_field(PF_Color_Depth, &color_depth,
|
|
||||||
sizeof(color_depth)) != sizeof(color_depth)) {
|
|
||||||
printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
/* Set up configuration data according to the hwinfo block we got. */
|
|
||||||
cfg->dp_interface_ctrl = 0x00;
|
|
||||||
cfg->lvds_interface_ctrl1 = 0x00;
|
|
||||||
if (disp_con == PF_DISPLCON_LVDS_DUAL) {
|
|
||||||
/* Turn on dual LVDS lane and clock. */
|
|
||||||
cfg->lvds_interface_ctrl1 |= 0x0b;
|
|
||||||
}
|
|
||||||
if (color_depth == PF_COLOR_DEPTH_6BIT) {
|
|
||||||
/* Use 18 bits per pixel. */
|
|
||||||
cfg->lvds_interface_ctrl1 |= 0x20;
|
|
||||||
}
|
|
||||||
/* No clock spreading, 300 mV LVDS swing. */
|
|
||||||
cfg->lvds_interface_ctrl2 = 0x03;
|
|
||||||
/* Swap LVDS even and odd lanes for HW-ID 7.9.2.0 only. */
|
|
||||||
if (hwilib_get_field(HWID, hwid, sizeof(hwid)) == sizeof(hwid) &&
|
|
||||||
!(memcmp(hwid, tcu31_hwid, sizeof(hwid)))) {
|
|
||||||
/* Swap LVDS even and odd lane. */
|
|
||||||
cfg->lvds_interface_ctrl3 = 0x01;
|
|
||||||
} else {
|
|
||||||
/* no LVDS lane swap */
|
|
||||||
cfg->lvds_interface_ctrl3 = 0x00;
|
|
||||||
}
|
|
||||||
/* Delay T2 (VDD to LVDS active) by 16 ms. */
|
|
||||||
cfg->t2_delay = 1;
|
|
||||||
/* 500 ms from LVDS to backlight active. */
|
|
||||||
cfg->t3_timing = 10;
|
|
||||||
/* 1 second re-power delay. */
|
|
||||||
cfg->t12_timing = 20;
|
|
||||||
/* 150 ms backlight off to LVDS inactive. */
|
|
||||||
cfg->t4_timing = 3;
|
|
||||||
/* Delay T5 (LVDS to VDD inactive) by 16 ms. */
|
|
||||||
cfg->t5_delay = 1;
|
|
||||||
/* Enable backlight control. */
|
|
||||||
cfg->backlight_ctrl = 0;
|
|
||||||
|
|
||||||
return PTN_CFG_MODIFIED;
|
|
||||||
}
|
|
||||||
@@ -1,31 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2014-2019 Siemens AG
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _LCD_PANEL_H_
|
|
||||||
#define _LCD_PANEL_H_
|
|
||||||
|
|
||||||
/* This GPIOs are used for LCD panel type encoding */
|
|
||||||
#define LCD_TYPE_GPIO_BIT0 40
|
|
||||||
#define LCD_TYPE_GPIO_BIT1 41
|
|
||||||
#define LCD_TYPE_GPIO_BIT2 42
|
|
||||||
#define LCD_TYPE_GPIO_BIT3 43
|
|
||||||
|
|
||||||
#define LCD_PANEL_TYPE_10_INCH 4
|
|
||||||
#define LCD_PANEL_TYPE_12_INCH 7
|
|
||||||
#define LCD_PANEL_TYPE_15_INCH 6
|
|
||||||
#define LCD_PANEL_TYPE_19_INCH 1
|
|
||||||
#define LCD_PANEL_TYPE_EDID 15
|
|
||||||
|
|
||||||
#endif /* _LCD_PANEL_H_ */
|
|
||||||
@@ -1,79 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <types.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#if CONFIG(VGA_ROM_RUN)
|
|
||||||
#include <x86emu/x86emu.h>
|
|
||||||
#endif
|
|
||||||
#include <hwilib.h>
|
|
||||||
#include <i210.h>
|
|
||||||
|
|
||||||
/** \brief This function will search for a MAC address which can be assigned
|
|
||||||
* to a MACPHY.
|
|
||||||
* @param dev pointer to PCI device
|
|
||||||
* @param mac buffer where to store the MAC address
|
|
||||||
* @return cb_err CB_ERR or CB_SUCCESS
|
|
||||||
*/
|
|
||||||
enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6])
|
|
||||||
{
|
|
||||||
uint8_t mac_adr[6];
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
/* Open main hwinfo block */
|
|
||||||
if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
|
|
||||||
return CB_ERR;
|
|
||||||
/* Get first MAC address from hwinfo. */
|
|
||||||
if (hwilib_get_field(Mac1, mac_adr, sizeof(mac_adr)) != sizeof(mac_adr))
|
|
||||||
return CB_ERR;
|
|
||||||
/* Ensure the first MAC-Address is not completely 0x00 or 0xff */
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
if (mac_adr[i] != 0xFF)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (i == 6){
|
|
||||||
return CB_ERR;
|
|
||||||
}
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
if (mac_adr[i] != 0x00)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (i == 6){
|
|
||||||
return CB_ERR;
|
|
||||||
} else {
|
|
||||||
memcpy(mac, mac_adr, 6);
|
|
||||||
return CB_SUCCESS;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
|
||||||
* This is the earliest point to add customization.
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void mainboard_final(void *chip_info)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
.final = mainboard_final,
|
|
||||||
};
|
|
||||||
@@ -1,202 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stddef.h>
|
|
||||||
#include <arch/cbfs.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <cpu/x86/mtrr.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
#include <soc/lpc.h>
|
|
||||||
#include <soc/pci_devs.h>
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include <soc/acpi.h>
|
|
||||||
#include <soc/baytrail.h>
|
|
||||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
|
||||||
#include <hwilib.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done before fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void early_mainboard_romstage_entry()
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Get function disables - most of these will be done automatically
|
|
||||||
* @param fd_mask
|
|
||||||
* @param fd2_mask
|
|
||||||
*/
|
|
||||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* /brief mainboard call for setup that needs to be done after fsp init
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void late_mainboard_romstage_entry()
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
const uint32_t mAzaliaVerbTableData13[] = {
|
|
||||||
/*
|
|
||||||
*ALC262 Verb Table - 10EC0262
|
|
||||||
*/
|
|
||||||
/* Pin Complex (NID 0x11) */
|
|
||||||
0x01171CF0,
|
|
||||||
0x01171D11,
|
|
||||||
0x01171E11,
|
|
||||||
0x01171F41,
|
|
||||||
/* Pin Complex (NID 0x12) */
|
|
||||||
0x01271CF0,
|
|
||||||
0x01271D11,
|
|
||||||
0x01271E11,
|
|
||||||
0x01271F41,
|
|
||||||
/* Pin Complex (NID 0x14) */
|
|
||||||
0x01471C10,
|
|
||||||
0x01471D40,
|
|
||||||
0x01471E01,
|
|
||||||
0x01471F01,
|
|
||||||
/* Pin Complex (NID 0x15) */
|
|
||||||
0x01571CF0,
|
|
||||||
0x01571D11,
|
|
||||||
0x01571E11,
|
|
||||||
0x01571F41,
|
|
||||||
/* Pin Complex (NID 0x16) */
|
|
||||||
0x01671CF0,
|
|
||||||
0x01671D11,
|
|
||||||
0x01671E11,
|
|
||||||
0x01671F41,
|
|
||||||
/* Pin Complex (NID 0x18) */
|
|
||||||
0x01871C20,
|
|
||||||
0x01871D98,
|
|
||||||
0x01871EA1,
|
|
||||||
0x01871F01,
|
|
||||||
/* Pin Complex (NID 0x19) */
|
|
||||||
0x01971C21,
|
|
||||||
0x01971D98,
|
|
||||||
0x01971EA1,
|
|
||||||
0x01971F02,
|
|
||||||
/* Pin Complex (NID 0x1A) */
|
|
||||||
0x01A71C2F,
|
|
||||||
0x01A71D30,
|
|
||||||
0x01A71E81,
|
|
||||||
0x01A71F01,
|
|
||||||
/* Pin Complex (NID 0x1B) */
|
|
||||||
0x01B71C1F,
|
|
||||||
0x01B71D40,
|
|
||||||
0x01B71E21,
|
|
||||||
0x01B71F02,
|
|
||||||
/* Pin Complex (NID 0x1C) */
|
|
||||||
0x01C71CF0,
|
|
||||||
0x01C71D11,
|
|
||||||
0x01C71E11,
|
|
||||||
0x01C71F41,
|
|
||||||
/* Pin Complex (NID 0x1D) */
|
|
||||||
0x01D71C01,
|
|
||||||
0x01D71DC6,
|
|
||||||
0x01D71E14,
|
|
||||||
0x01D71F40,
|
|
||||||
/* Pin Complex (NID 0x1E) */
|
|
||||||
0x01E71CF0,
|
|
||||||
0x01E71D11,
|
|
||||||
0x01E71E11,
|
|
||||||
0x01E71F41,
|
|
||||||
/* Pin Complex (NID 0x1F) */
|
|
||||||
0x01F71CF0,
|
|
||||||
0x01F71D11,
|
|
||||||
0x01F71E11,
|
|
||||||
0x01F71F41 };
|
|
||||||
|
|
||||||
const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { {
|
|
||||||
/*
|
|
||||||
* VerbTable: (RealTek ALC262)
|
|
||||||
* Revision ID = 0xFF, support all steps
|
|
||||||
* Codec Verb Table For AZALIA
|
|
||||||
* Codec Address: CAd value (0/1/2)
|
|
||||||
* Codec Vendor: 0x10EC0262
|
|
||||||
*/
|
|
||||||
{
|
|
||||||
0x10EC0262, /* Vendor ID/Device IDA */
|
|
||||||
0x0000, /* SubSystem ID */
|
|
||||||
0xFF, /* Revision IDA */
|
|
||||||
0x01, /* Front panel support (1 = yes, 2 = no) */
|
|
||||||
0x000B, /* Number of Rear Jacks = 11 */
|
|
||||||
0x0002 /* Number of Front Jacks = 2 */
|
|
||||||
},
|
|
||||||
(uint32_t *)mAzaliaVerbTableData13 } };
|
|
||||||
|
|
||||||
const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = {
|
|
||||||
.Pme = 1,
|
|
||||||
.DS = 1,
|
|
||||||
.DA = 0,
|
|
||||||
.HdmiCodec = 1,
|
|
||||||
.AzaliaVCi = 1,
|
|
||||||
.Rsvdbits = 0,
|
|
||||||
.AzaliaVerbTableNum = 1,
|
|
||||||
.AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable,
|
|
||||||
.ResetWaitTimer = 300 };
|
|
||||||
|
|
||||||
/** /brief customize fsp parameters here if needed
|
|
||||||
*/
|
|
||||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
|
||||||
{
|
|
||||||
uint8_t spd[0x80];
|
|
||||||
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
|
|
||||||
|
|
||||||
/* Initialize the Azalia Verb Tables to mainboard specific version. */
|
|
||||||
UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig;
|
|
||||||
|
|
||||||
/* Get SPD data from hwinfo block and set up memory down */
|
|
||||||
/* parameters for FSP accordingly. */
|
|
||||||
if (hwilib_find_blocks("hwinfo.hex")) {
|
|
||||||
printk(BIOS_ERR,
|
|
||||||
"HWInfo not found, use default timings for DDR3.\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) {
|
|
||||||
printk(BIOS_ERR,
|
|
||||||
"SPD not found in HWInfo, use defaults for DDR3.\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
/*Set up DDR timings from HWInfo. */
|
|
||||||
UpdData->PcdMemoryParameters.EnableMemoryDown = 1;
|
|
||||||
UpdData->PcdMemoryParameters.DRAMType = spd[2];
|
|
||||||
UpdData->PcdMemoryParameters.DIMM0Enable = spd[3] & 0x01;
|
|
||||||
UpdData->PcdMemoryParameters.DIMM1Enable = (spd[3] >> 1) & 0x01;
|
|
||||||
UpdData->PcdMemoryParameters.DIMMDensity = spd[4];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMDWidth = spd[5];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMSides = spd[7];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMBusWidth = spd[8];
|
|
||||||
UpdData->PcdMemoryParameters.DRAMSpeed = spd[12];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtCL = spd[14];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtWR = spd[17];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtRPtRCD = spd[18];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtRRD = spd[19];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtWTR = spd[26];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtRTP = spd[27];
|
|
||||||
UpdData->PcdMemoryParameters.DIMMtFAW = spd[28];
|
|
||||||
|
|
||||||
/*If one need output from MRC to be used in Intel RMT, simply */
|
|
||||||
/*enable the following line */
|
|
||||||
//UpdData->PcdMrcDebugMsg = 1;
|
|
||||||
}
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MAINBOARD_THERMAL_H
|
|
||||||
#define MAINBOARD_THERMAL_H
|
|
||||||
|
|
||||||
|
|
||||||
/* Temperature which OS will shutdown at */
|
|
||||||
#define CRITICAL_TEMPERATURE 100
|
|
||||||
|
|
||||||
/* Temperature which OS will throttle CPU */
|
|
||||||
#define PASSIVE_TEMPERATURE 90
|
|
||||||
|
|
||||||
/* Tj_max value for calculating PECI CPU temperature */
|
|
||||||
#define MAX_TEMPERATURE 100
|
|
||||||
|
|
||||||
#endif /* MAINBOARD_THERMAL_H */
|
|
||||||
Reference in New Issue
Block a user