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f10/f12: Remove whitespace from gcccar.inc

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Change-Id: I9fca0e12f02d6fff4644abacecd4a31cea64bbc1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Stefan Reinauer 2015-07-21 14:04:27 -07:00 committed by Patrick Georgi
parent 03597d0f01
commit eb5f45ac62
2 changed files with 252 additions and 252 deletions
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14
src/vendorcode/amd/agesa/f10/gcccar.inc
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@ -66,15 +66,15 @@ AMD_MTRR_DEFTYPE = 0x02FF
MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
HWCR = 0x0C0010015 /* Hardware Configuration */ HWCR = 0x0C0010015 /* Hardware Configuration */
INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
/* uses 16h - 19h */ /* uses 16h - 19h */
TOP_MEM = 0x0C001001A /* Top of Memory */ TOP_MEM = 0x0C001001A /* Top of Memory */
TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
LS_CFG = 0x0C0011020 /* Load-Store Configuration */ LS_CFG = 0x0C0011020 /* Load-Store Configuration */
DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
@ -83,10 +83,10 @@ IC_CFG = 0x0C0011021 /* Instruction Cache Config Reg
DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
DC_CFG = 0x0C0011022 /* Data Cache Configuration */ DC_CFG = 0x0C0011022 /* Data Cache Configuration */
DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
DIS_HW_PF = 13 /* Hardware prefetches bit */ DIS_HW_PF = 13 /* Hardware prefetches bit */
DE_CFG = 0x0C0011029 /* Decode Configuration */ DE_CFG = 0x0C0011029 /* Decode Configuration */
CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */