sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/volteer/var/volet: change GPP_B2 to PLTRST

Browse Source 
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang.

BUG=b:174776411
BRANCH=none
TEST=none

Change-Id: Ib0858afa1b5dc9de9db87485d3e0bf6032416746
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Nick Vaccaro
2021-06-11 18:14:43 -07:00
parent 123fd50152
commit ebca7915bf
1 changed files with 6 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/google/volteer/variants/volet/gpio.c
View File

@@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
PAD_CFG_GPO(GPP_B2, 1, PLTRST),
/* B3 : CPU_GP2 ==> PEN_DET_ODL */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B3, NONE, PLTRST),
/* B5 : ISH_I2C0_CVF_SDA */
@@ -234,11 +234,6 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* C8 : UART0 RX */
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* C9 : UART0 TX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
@@ -248,7 +243,7 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
PAD_CFG_GPO(GPP_B2, 1, PLTRST),
/* B11 : PMCALERT# ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
@@ -262,6 +257,10 @@ static const struct pad_config early_gpio_table[] = {
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C8 : UART0 RX */
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* C9 : UART0 TX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */