Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"
This reverts commit 2e10a6d6f3ec46bcaf75bd066319d51f001be764. Reason for revert: The FW version check is not supported except for ADL platform. Reverted change broke S0ix functionality; the original CL was added as HW W/A for ADL ONLY. BUG=b:306214725 TEST=S0ix cycles on Rex with TBT Device attached. Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -452,10 +452,6 @@ Scope (\_SB.PCI0)
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/* DMA0 is not in D3Cold now. */
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/* DMA0 is not in D3Cold now. */
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\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
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\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
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If (\_SB.PCI0.TDM0.IF30 != 1) {
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Return
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}
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Printf("Push TBT RPs to D3Cold together")
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Printf("Push TBT RPs to D3Cold together")
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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/* Put RP0 to D3 cold. */
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/* Put RP0 to D3 cold. */
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@ -511,10 +507,6 @@ Scope (\_SB.PCI0)
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/* DMA1 is not in D3Cold now */
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/* DMA1 is not in D3Cold now */
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\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
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\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
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If (\_SB.PCI0.TDM1.IF30 != 1) {
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Return
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}
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Printf("Push TBT RPs to D3Cold together")
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Printf("Push TBT RPs to D3Cold together")
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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/* Put RP2 to D3 cold. */
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/* Put RP2 to D3 cold. */
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@ -11,8 +11,7 @@ Field (DPME, AnyAcc, NoLock, Preserve)
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, 6,
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, 6,
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PMES, 1, /* 15, PME_STATUS */
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PMES, 1, /* 15, PME_STATUS */
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Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
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Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
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, 30,
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, 31,
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IF30, 1, /* ITBT FW Version Bit30 */
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INFR, 1, /* TBT NVM FW Ready */
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INFR, 1, /* TBT NVM FW Ready */
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Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
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Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
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TB2P, 32, /* TBT to PCIe */
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TB2P, 32, /* TBT to PCIe */
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@ -567,10 +567,6 @@ Scope (\_SB.PCI0)
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/* DMA0 is not in D3Cold now. */
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/* DMA0 is not in D3Cold now. */
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\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
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\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
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If (\_SB.PCI0.TDM0.IF30 != 1) {
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Return
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}
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Printf("Push TBT RPs to D3Cold together")
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Printf("Push TBT RPs to D3Cold together")
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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/* Put RP0 to D3 cold. */
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/* Put RP0 to D3 cold. */
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@ -626,10 +622,6 @@ Scope (\_SB.PCI0)
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/* DMA1 is not in D3Cold now */
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/* DMA1 is not in D3Cold now */
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\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
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\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
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If (\_SB.PCI0.TDM1.IF30 != 1) {
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Return
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}
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Printf("Push TBT RPs to D3Cold together")
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Printf("Push TBT RPs to D3Cold together")
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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/* Put RP2 to D3 cold. */
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/* Put RP2 to D3 cold. */
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@ -11,8 +11,7 @@ Field (DPME, AnyAcc, NoLock, Preserve)
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, 6,
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, 6,
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PMES, 1, /* 15, PME_STATUS */
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PMES, 1, /* 15, PME_STATUS */
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Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
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Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
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, 30,
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, 31,
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IF30, 1, /* ITBT FW Version Bit30 */
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INFR, 1, /* TBT NVM FW Ready */
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INFR, 1, /* TBT NVM FW Ready */
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Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
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Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
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TB2P, 32, /* TBT to PCIe */
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TB2P, 32, /* TBT to PCIe */
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