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Documentation/Intel/NativeRaminit: Style fixes

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Fix tables and minor markdown bugs.

Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Patrick Rudolph
2018-05-14 19:17:05 +02:00
committed by Martin Roth
parent 5dbe8ee725
commit ebdeb4d07d
4 changed files with 1474 additions and 645 deletions
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25
Documentation/Intel/NativeRaminit/Sandybridge.md
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@@ -18,16 +18,27 @@ The memory initialization code has to take care of lots of duties:
* Error handling
## Definitions
```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
|---------|-------------------------------------------------------------------|------------|--------------|
| SCK | DRAM system clock cycle time | s | - |
| tCK | DRAM system clock cycle time | 1/256th ns | - |
| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
+=========+===================================================================+============+==============+
| SCK | DRAM system clock cycle time | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| tCK | DRAM system clock cycle time | 1/256th ns | |
+---------+-------------------------------------------------------------------+------------+--------------+
| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
+---------+-------------------------------------------------------------------+------------+--------------+
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
+---------+-------------------------------------------------------------------+------------+--------------+
| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
| MULT | DRAM PLL multiplier | - | [3-12] |
| XMP | Extreme Memory Profiles | - | - |
+---------+-------------------------------------------------------------------+------------+--------------+
| MULT | DRAM PLL multiplier | | [3-12] |
+---------+-------------------------------------------------------------------+------------+--------------+
| XMP | Extreme Memory Profiles | | |
+---------+-------------------------------------------------------------------+------------+--------------+
```
## (Inoffical) register documentation
- [Sandy Bride - Register documentation](SandyBridge_registers.md)