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mainboard/roda: Use C89 comments style & remove commented code

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Change-Id: I4ce2705a8a07d0388bbdb459b63b59fc10a3aa39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16929
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
2016-10-07 18:22:44 +02:00
committed by Martin Roth
parent 5db945062c
commit ec16e9302b
7 changed files with 164 additions and 207 deletions
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20
src/mainboard/roda/rk886ex/irq_tables.c
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@@ -30,22 +30,22 @@ static const struct irq_routing_table intel_irq_routing_table = {
0xf, /* u8 checksum. */ 0xf, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
} }

219
src/mainboard/roda/rk886ex/m3885.c
View File

@@ -31,79 +31,79 @@
static u8 variables[] = { static u8 variables[] = {
/* Offs, AND, OR */ /* Offs, AND, OR */
0x08, 0x48, 0x6C, // Keyboard ScanCode Set & LED Data (kState1) 0x08, 0x48, 0x6C, /* Keyboard ScanCode Set & LED Data (kState1) */
0x0a, 0x01, 0x00, // Keyboard Shift flags (kState3) 0x0a, 0x01, 0x00, /* Keyboard Shift flags (kState3) */
0x0c, 0x80, 0x08, // Keyboard State flags (kState5) 0x0c, 0x80, 0x08, /* Keyboard State flags (kState5) */
0x11, 0xff, 0x06, // Make/Break Debounce #'s (debounce) 0x11, 0xff, 0x06, /* Make/Break Debounce #'s (debounce) */
0x13, 0xff, 0x00, // HotKey1 ScanCode (hotKey1) 0x13, 0xff, 0x00, /* HotKey1 ScanCode (hotKey1) */
0x14, 0xff, 0x00, // HotKey2 ScanCode (hotKey2) 0x14, 0xff, 0x00, /* HotKey2 ScanCode (hotKey2) */
0x15, 0xff, 0x3f, // HotKey3 ScanCode (hotKey3) 0x15, 0xff, 0x3f, /* HotKey3 ScanCode (hotKey3) */
0x16, 0xff, 0x00, // HotKey4 ScanCode (hotKey4) 0x16, 0xff, 0x00, /* HotKey4 ScanCode (hotKey4) */
0x17, 0xff, 0x00, // HotKey5 ScanCode (hotKey5) 0x17, 0xff, 0x00, /* HotKey5 ScanCode (hotKey5) */
0x18, 0xff, 0x0e, // HotKey6 ScanCode (hotKey6) 0x18, 0xff, 0x0e, /* HotKey6 ScanCode (hotKey6) */
0x19, 0xff, 0x9f, // HotKey1 Task = c5 Command Data (keyTsk1) 0x19, 0xff, 0x9f, /* HotKey1 Task = c5 Command Data (keyTsk1) */
0x1a, 0xff, 0x9f, // HotKey2 Task = c5 Command Data (keyTsk2) 0x1a, 0xff, 0x9f, /* HotKey2 Task = c5 Command Data (keyTsk2) */
0x1b, 0xff, 0x6a, // HotKey3 Task = c5 Command Data (keyTsk3) 0x1b, 0xff, 0x6a, /* HotKey3 Task = c5 Command Data (keyTsk3) */
0x1c, 0xff, 0x9f, // HotKey4 Task = c5 Command Data (keyTsk4) 0x1c, 0xff, 0x9f, /* HotKey4 Task = c5 Command Data (keyTsk4) */
0x1d, 0xff, 0x9f, // HotKey5 Task = c5 Command Data (keyTsk5) 0x1d, 0xff, 0x9f, /* HotKey5 Task = c5 Command Data (keyTsk5) */
0x1e, 0xff, 0x87, // FuncKey Task = c5 Command Data (funcTsk) 0x1e, 0xff, 0x87, /* FuncKey Task = c5 Command Data (funcTsk) */
0x1f, 0xff, 0x9f, // Delayed Task = c5 Command Data (dlyTsk1) 0x1f, 0xff, 0x9f, /* Delayed Task = c5 Command Data (dlyTsk1) */
0x20, 0xff, 0x9f, // Wake-Up Task = c5 Command Data (wakeTsk) 0x20, 0xff, 0x9f, /* Wake-Up Task = c5 Command Data (wakeTsk) */
//
0x21, 0xff, 0x08, // WigglePin Pulse Width * 2.4ms (tmPulse) 0x21, 0xff, 0x08, /* WigglePin Pulse Width * 2.4ms (tmPulse) */
0x24, 0xff, 0x30, // Keyboard State Flags (kState7) 0x24, 0xff, 0x30, /* Keyboard State Flags (kState7) */
//
0x2b, 0xff, 0x00, // 0x2b, 0xff, 0x00,
0x2c, 0xff, 0x80, // Set Fn-Key 8 0x2c, 0xff, 0x80, /* Set Fn-Key 8 */
0x2d, 0xff, 0x02, // Set Fn-Key 9 0x2d, 0xff, 0x02, /* Set Fn-Key 9 */
0x2e, 0xff, 0x00, // Set Fn-Key 1-8 task (0 = SMI) 0x2e, 0xff, 0x00, /* Set Fn-Key 1-8 task (0 = SMI) */
0x2f, 0xff, 0x00, // Set Fn-Key 9-12 task (1 = SCI) 0x2f, 0xff, 0x00, /* Set Fn-Key 9-12 task (1 = SCI) */
}; };
static u8 matrix[] = { static u8 matrix[] = {
0xc1,0xc0,0xd8,0xdb,0xbf,0x05,0x76,0xbf, // (0x00-0x07) 0xc1,0xc0,0xd8,0xdb,0xbf,0x05,0x76,0xbf, /* (0x00-0x07) */
0xbf,0x80,0x78,0xbf,0xbf,0x07,0x88,0xc2, // (0x08-0x0f) 0xbf,0x80,0x78,0xbf,0xbf,0x07,0x88,0xc2, /* (0x08-0x0f) */
0x03,0x09,0xd9,0x16,0xbf,0x06,0x0e,0x81, // (0x10-0x17) 0x03,0x09,0xd9,0x16,0xbf,0x06,0x0e,0x81, /* (0x10-0x17) */
0xbf,0xbf,0xee,0xbf,0xbf,0x55,0x9a,0x89, // (0x18-0x1f) 0xbf,0xbf,0xee,0xbf,0xbf,0x55,0x9a,0x89, /* (0x18-0x1f) */
0x1e,0x15,0x36,0xda,0xe8,0xbf,0x0d,0xbf, // (0x20-0x27) 0x1e,0x15,0x36,0xda,0xe8,0xbf,0x0d,0xbf, /* (0x20-0x27) */
0xbf,0xbf,0xbf,0xa3,0xbf,0x4e,0x66,0x8b, // (0x28-0x2f) 0xbf,0xbf,0xbf,0xa3,0xbf,0x4e,0x66,0x8b, /* (0x28-0x2f) */
0x1d,0x2e,0xe6,0xe7,0xe5,0x1c,0x58,0xbf, // (0x30-0x37) 0x1d,0x2e,0xe6,0xe7,0xe5,0x1c,0x58,0xbf, /* (0x30-0x37) */
0x82,0xbf,0xf0,0xbf,0xbf,0x5b,0x5d,0x8c, // (0x38-0x3f) 0x82,0xbf,0xf0,0xbf,0xbf,0x5b,0x5d,0x8c, /* (0x38-0x3f) */
0x22,0x25,0x2c,0x35,0xe1,0x1a,0x96,0xbf, // (0x40-0x47) 0x22,0x25,0x2c,0x35,0xe1,0x1a,0x96,0xbf, /* (0x40-0x47) */
0xbf,0xbf,0xec,0xbf,0xbf,0x54,0xf1,0x8f, // (0x48-0x4f) 0xbf,0xbf,0xec,0xbf,0xbf,0x54,0xf1,0x8f, /* (0x48-0x4f) */
0x1b,0x2a,0x2b,0x32,0xe9,0x31,0x29,0x61, // (0x50-0x57) 0x1b,0x2a,0x2b,0x32,0xe9,0x31,0x29,0x61, /* (0x50-0x57) */
0xbf,0xbf,0x8d,0xbf,0x86,0xc3,0x92,0x93, // (0x58-0x5f) 0xbf,0xbf,0x8d,0xbf,0x86,0xc3,0x92,0x93, /* (0x58-0x5f) */
0x21,0x23,0x34,0x33,0x41,0xe0,0xbf,0xbf, // (0x60-0x67) 0x21,0x23,0x34,0x33,0x41,0xe0,0xbf,0xbf, /* (0x60-0x67) */
0xbf,0x85,0xeb,0xbf,0xb6,0xbf,0x91,0xbf, // (0x68-0x6f) 0xbf,0x85,0xeb,0xbf,0xb6,0xbf,0x91,0xbf, /* (0x68-0x6f) */
0x26,0x24,0x2d,0xe3,0xe2,0xe4,0xbf,0xbf, // (0x70-0x77) 0x26,0x24,0x2d,0xe3,0xe2,0xe4,0xbf,0xbf, /* (0x70-0x77) */
0x87,0xbf,0xea,0xbf,0xbf,0x52,0x90,0x8e, // (0x78-0x7f) 0x87,0xbf,0xea,0xbf,0xbf,0x52,0x90,0x8e, /* (0x78-0x7f) */
}; };
static u8 function_ram[] = { static u8 function_ram[] = {
0x04,0xbd,0x0c,0xbe,0x7e,0x9a,0x8a,0xb6, // (0xc0-0xc3) 0x04,0xbd,0x0c,0xbe,0x7e,0x9a,0x8a,0xb6, /* (0xc0-0xc3) */
0x92,0x8f,0x93,0x8e,0x81,0x86,0x82,0x87, // (0xc4-0xc7) 0x92,0x8f,0x93,0x8e,0x81,0x86,0x82,0x87, /* (0xc4-0xc7) */
0x8a,0x9a,0x8d,0x7e,0x88,0x84,0x7e,0x78, // (0xc8-0xcb) 0x8a,0x9a,0x8d,0x7e,0x88,0x84,0x7e,0x78, /* (0xc8-0xcb) */
0x77,0x07,0x77,0x98,0x89,0xb2,0x05,0x9b, // (0xcc-0xcf) 0x77,0x07,0x77,0x98,0x89,0xb2,0x05,0x9b, /* (0xcc-0xcf) */
0x78,0x84,0x07,0x88,0x8a,0x7e,0x05,0xa6, // (0xd0-0xd3) 0x78,0x84,0x07,0x88,0x8a,0x7e,0x05,0xa6, /* (0xd0-0xd3) */
0x06,0xa7,0x04,0xa8,0x0c,0xa9,0x03,0xaa, // (0xd4-0xd7) 0x06,0xa7,0x04,0xa8,0x0c,0xa9,0x03,0xaa, /* (0xd4-0xd7) */
0x0b,0xc1,0x83,0xc0,0x0a,0xad,0x01,0xae, // (0xd8-0xdb) 0x0b,0xc1,0x83,0xc0,0x0a,0xad,0x01,0xae, /* (0xd8-0xdb) */
0x09,0xaf,0x78,0xb0,0x07,0xb1,0x1a,0x61, // (0xdc-0xdf) 0x09,0xaf,0x78,0xb0,0x07,0xb1,0x1a,0x61, /* (0xdc-0xdf) */
0x3b,0x69,0x42,0x72,0x4b,0x7a,0x3c,0x6b, // (0xe0-0xe3) 0x3b,0x69,0x42,0x72,0x4b,0x7a,0x3c,0x6b, /* (0xe0-0xe3) */
0x43,0x73,0x44,0x74,0x3d,0x6c,0x3e,0x75, // (0xe4-0xe7) 0x43,0x73,0x44,0x74,0x3d,0x6c,0x3e,0x75, /* (0xe4-0xe7) */
0x46,0x7d,0x3a,0x70,0x49,0x71,0x4a,0x94, // (0xe8-0xeb) 0x46,0x7d,0x3a,0x70,0x49,0x71,0x4a,0x94, /* (0xe8-0xeb) */
0x4c,0x79,0x4c,0x7c,0x45,0x7c,0x45,0x79, // (0xec-0xef) 0x4c,0x79,0x4c,0x7c,0x45,0x7c,0x45,0x79, /* (0xec-0xef) */
0x4d,0x7b,0x5a,0x95,0x4c,0x7b,0x45,0x7b, // (0xf0-0xf3) 0x4d,0x7b,0x5a,0x95,0x4c,0x7b,0x45,0x7b, /* (0xf0-0xf3) */
0x4d,0x79,0x4d,0x7c,0x4e,0x7b,0x54,0x95, // (0xf4-0xf7) 0x4d,0x79,0x4d,0x7c,0x4e,0x7b,0x54,0x95, /* (0xf4-0xf7) */
0x52,0x7c,0x45,0x94,0x4a,0x79,0xb3,0x95, // (0xf8-0xfb) 0x52,0x7c,0x45,0x94,0x4a,0x79,0xb3,0x95, /* (0xf8-0xfb) */
0xb4,0x7b,0xb5,0x7c,0x00,0x00,0x55,0x79, // (0xfc-0xff) 0xb4,0x7b,0xb5,0x7c,0x00,0x00,0x55,0x79, /* (0xfc-0xff) */
}; };
#define KBD_DATA 0x60 #define KBD_DATA 0x60
#define KBD_SC 0x64 #define KBD_SC 0x64
#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) #define KBD_IBF (1 << 1) /* 1: input buffer full (data ready for ec) */
#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) #define KBD_OBF (1 << 0) /* 1: output buffer full (data ready for host) */
static int send_kbd_command(u8 command) static int send_kbd_command(u8 command)
{ {
@@ -118,7 +118,6 @@ static int send_kbd_command(u8 command)
if (!timeout) { if (!timeout) {
printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n",
command); command);
// return -1;
} }
outb(command, KBD_SC); outb(command, KBD_SC);
@@ -130,7 +129,7 @@ static int send_kbd_data(u8 data)
int timeout; int timeout;
timeout = 0x7ff; timeout = 0x7ff;
while ((inb(KBD_SC) & KBD_IBF) && --timeout) { // wait for IBF = 0 while ((inb(KBD_SC) & KBD_IBF) && --timeout) { /* wait for IBF = 0 */
udelay(10); udelay(10);
if ((timeout & 0xff) == 0) if ((timeout & 0xff) == 0)
printk(BIOS_SPEW, "."); printk(BIOS_SPEW, ".");
@@ -138,7 +137,6 @@ static int send_kbd_data(u8 data)
if (!timeout) { if (!timeout) {
printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n", printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n",
data); data);
// return -1;
} }
outb(data, KBD_DATA); outb(data, KBD_DATA);
@@ -153,7 +151,7 @@ static u8 recv_kbd_data(void)
u8 data; u8 data;
timeout = 0x7fff; timeout = 0x7fff;
while (--timeout) { // Wait for OBF = 1 while (--timeout) { /* Wait for OBF = 1 */
if (inb(KBD_SC) & KBD_OBF) { if (inb(KBD_SC) & KBD_OBF) {
break; break;
} }
@@ -163,7 +161,6 @@ static u8 recv_kbd_data(void)
} }
if (!timeout) { if (!timeout) {
printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n"); printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n");
// return -1;
} }
data = inb(KBD_DATA); data = inb(KBD_DATA);
@@ -210,7 +207,6 @@ static u8 m3885_get_proc_ram(u8 index)
send_kbd_command(0xb8); send_kbd_command(0xb8);
send_kbd_data(index); send_kbd_data(index);
send_kbd_command(0xba); send_kbd_command(0xba);
// send_kbd_command(0xff);
ret = recv_kbd_data(); ret = recv_kbd_data();
printk(BIOS_SPEW, "m3885: get procram %02x = %02x\n", index, ret); printk(BIOS_SPEW, "m3885: get procram %02x = %02x\n", index, ret);
return ret; return ret;
@@ -222,7 +218,7 @@ static u8 m3885_read_port(void)
reg8 = m3885_get_variable(0x0c); reg8 = m3885_get_variable(0x0c);
reg8 &= ~(7 << 4); reg8 &= ~(7 << 4);
reg8 |= (4 << 4); // bank 4 reg8 |= (4 << 4); /* bank 4 */
m3885_set_variable(0x0c, reg8); m3885_set_variable(0x0c, reg8);
/* P6YSTATE */ /* P6YSTATE */
@@ -265,7 +261,7 @@ void m3885_configure_multikey(void)
printk(BIOS_DEBUG, "Could not load Function-RAM (%d).\n", maxvars); printk(BIOS_DEBUG, "Could not load Function-RAM (%d).\n", maxvars);
} }
// restore original bank /* restore original bank */
m3885_set_variable(0x0c, kstate5_flags); m3885_set_variable(0x0c, kstate5_flags);
maxvars = m3885_get_variable(0x00); maxvars = m3885_get_variable(0x00);
printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars); printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars);
@@ -274,7 +270,7 @@ void m3885_configure_multikey(void)
continue; continue;
reg8 = m3885_get_variable(variables[i + 0]); reg8 = m3885_get_variable(variables[i + 0]);
reg8 &= ~(variables[i + 1]); reg8 &= ~(variables[i + 1]);
reg8 |= variables[i + 2]; // & ~variables[i + 1]; reg8 |= variables[i + 2];
m3885_set_variable(variables[i + 0], reg8); m3885_set_variable(variables[i + 0], reg8);
} }
@@ -303,108 +299,87 @@ void m3885_configure_multikey(void)
m3885_set_proc_ram(0xf9, 0x0a); m3885_set_proc_ram(0xf9, 0x0a);
/* ReadPort */ /* ReadPort */
// m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (4 << 4));
/* AC PRESN# */ /* AC PRESN# */
if (m3885_read_port() & (1 << 0)) if (m3885_read_port() & (1 << 0))
reg8 = 0x8a; reg8 = 0x8a;
else else
reg8 = 0x9a; reg8 = 0x9a;
m3885_set_proc_ram(0xd0, reg8); // P60SPEC m3885_set_proc_ram(0xd0, reg8); /* P60SPEC */
/* SENSE1# */ /* SENSE1# */
if (m3885_read_port() & (1 << 2)) if (m3885_read_port() & (1 << 2))
reg8 = 0x8a; reg8 = 0x8a;
else else
reg8 = 0x9a; reg8 = 0x9a;
m3885_set_proc_ram(0xd2, reg8); // P62SPEC m3885_set_proc_ram(0xd2, reg8); /* P62SPEC */
/* SENSE2# */ /* SENSE2# */
if (m3885_read_port() & (1 << 3)) if (m3885_read_port() & (1 << 3))
reg8 = 0x8a; reg8 = 0x8a;
else else
reg8 = 0x9a; reg8 = 0x9a;
m3885_set_proc_ram(0xd3, reg8); // P63SPEC m3885_set_proc_ram(0xd3, reg8); /* P63SPEC */
/* Low Active Port */ /* Low Active Port */
m3885_set_proc_ram(0xd1, 0x88); // P61SPEC m3885_set_proc_ram(0xd1, 0x88); /* P61SPEC */
m3885_set_proc_ram(0xd6, 0x88); // P66SPEC m3885_set_proc_ram(0xd6, 0x88); /* P66SPEC */
m3885_set_proc_ram(0xd7, 0x88); // P67SPEC m3885_set_proc_ram(0xd7, 0x88); /* P67SPEC */
/* High Active Port */ /* High Active Port */
m3885_set_proc_ram(0xd4, 0x98); // P64SPEC m3885_set_proc_ram(0xd4, 0x98); /* P64SPEC */
m3885_set_proc_ram(0xd5, 0x98); // P65SPEC m3885_set_proc_ram(0xd5, 0x98); /* P65SPEC */
/* Set P60TASK-P67TASK */ /* Set P60TASK-P67TASK */
/* SCI */ /* SCI */
m3885_set_proc_ram(0xda, 0x80); // P62TASK SENSE1# m3885_set_proc_ram(0xda, 0x80); /* P62TASK SENSE1# */
m3885_set_proc_ram(0xdb, 0x80); // P63TASK SENSE2# m3885_set_proc_ram(0xdb, 0x80); /* P63TASK SENSE2# */
m3885_set_proc_ram(0xdd, 0x80); // P65TASK PROCHOT m3885_set_proc_ram(0xdd, 0x80); /* P65TASK PROCHOT */
m3885_set_proc_ram(0xde, 0x80); // P65TASK THERMTRIP# m3885_set_proc_ram(0xde, 0x80); /* P65TASK THERMTRIP# */
m3885_set_proc_ram(0xdf, 0x80); // P65TASK PME# m3885_set_proc_ram(0xdf, 0x80); /* P65TASK PME# */
/* SMI/SCI */ /* SMI/SCI */
m3885_set_proc_ram(0xd8, 0x81); // P60TASK, AC_PRESN# m3885_set_proc_ram(0xd8, 0x81); /* P60TASK, AC_PRESN# */
m3885_set_proc_ram(0xd9, 0x81); // P61TASK, LID# m3885_set_proc_ram(0xd9, 0x81); /* P61TASK, LID# */
m3885_set_proc_ram(0xdc, 0x81); // P64TASK, FDD/LPT# m3885_set_proc_ram(0xdc, 0x81); /* P64TASK, FDD/LPT# */
/* Thermal */ /* Thermal */
/* Bank 5 */ /* Bank 5 */
m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (5 << 4)); m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (5 << 4));
/* Thermal 0: Active cooling, Speed Step Down */ /* Thermal 0: Active cooling, Speed Step Down */
m3885_set_proc_ram(0x81, 0x9c); // THRM0 m3885_set_proc_ram(0x81, 0x9c); /* THRM0 */
m3885_set_proc_ram(0x82, 0x01); // THRM0 CMD m3885_set_proc_ram(0x82, 0x01); /* THRM0 CMD */
m3885_set_proc_ram(0x84, TH0LOW); // THRM0 LOW m3885_set_proc_ram(0x84, TH0LOW); /* THRM0 LOW */
m3885_set_proc_ram(0x85, TH0HIGH); // THRM0 HIGH m3885_set_proc_ram(0x85, TH0HIGH); /* THRM0 HIGH */
m3885_set_proc_ram(0x86, 0x81); // Set Task SMI#/SCI m3885_set_proc_ram(0x86, 0x81); /* Set Task SMI#/SCI */
m3885_set_proc_ram(0x87, TH0CRIT); // THRM0 CRIT m3885_set_proc_ram(0x87, TH0CRIT); /* THRM0 CRIT */
/* Thermal 1: Passive cooling, Fan On */ /* Thermal 1: Passive cooling, Fan On */
m3885_set_proc_ram(0x89, 0x9c); // THRM1 m3885_set_proc_ram(0x89, 0x9c); /* THRM1 */
m3885_set_proc_ram(0x8a, 0x01); // THRM1 CMD m3885_set_proc_ram(0x8a, 0x01); /* THRM1 CMD */
m3885_set_proc_ram(0x8c, TH1LOW); // THRM1 LOW m3885_set_proc_ram(0x8c, TH1LOW); /* THRM1 LOW */
m3885_set_proc_ram(0x8d, TH1HIGH); // THRM1 HIGH m3885_set_proc_ram(0x8d, TH1HIGH); /* THRM1 HIGH */
m3885_set_proc_ram(0x8e, 0x81); // Set Task SMI#/SCI m3885_set_proc_ram(0x8e, 0x81); /* Set Task SMI#/SCI */
/* Switch Task to SMI */ /* Switch Task to SMI */
udelay(100 * 1000); // 100ms udelay(100 * 1000); /* 100ms */
outb(KBD_SC, 0xca); outb(KBD_SC, 0xca);
udelay(100 * 1000); // 100ms udelay(100 * 1000); /* 100ms */
outb(KBD_DATA, 0x17); outb(KBD_DATA, 0x17);
/* Set P22 to high level, keyboard backlight default off */ /* Set P22 to high level, keyboard backlight default off */
udelay(100 * 1000); // 100ms udelay(100 * 1000); /* 100ms */
outb(KBD_SC, 0xc5); outb(KBD_SC, 0xc5);
udelay(100 * 1000); // 100ms udelay(100 * 1000); /* 100ms */
outb(KBD_DATA, 0x4a); outb(KBD_DATA, 0x4a);
} }
u8 m3885_gpio(u8 value) u8 m3885_gpio(u8 value)
{ {
#if 0
int timeout;
#endif
/* First write data */ /* First write data */
ec_write(M3885_CMDAT1, value); ec_write(M3885_CMDAT1, value);
/* Issue command: ACCESS GPIO */ /* Issue command: ACCESS GPIO */
ec_write(M3885_CMCMD, 0xc5); ec_write(M3885_CMCMD, 0xc5);
#if 0
/* CMCMD is 0 when the command is completed */
timeout = 0xf;
while (ec_read(M3885_CMCMD) && --timeout) {
udelay(10);
printk(BIOS_DEBUG, ".");
}
if (!timeout) {
printk(BIOS_DEBUG, "\nTimeout while waiting for M3885 command!\n");
}
/* If it was a read function: Pin state */
return ec_read(M3885_CMDAT1);
#else
return 0; return 0;
#endif
} }

14
src/mainboard/roda/rk886ex/mainboard.c
View File

@@ -28,18 +28,6 @@
static void backlight_enable(void) static void backlight_enable(void)
{ {
#if 0
// Disabled, don't let the X9511 burn out
int i;
/* P56 is Brightness Up, and it needs a Pulse instead of a
* Level
*/
for (i = 0; i < 28; i++) {
//m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56);
m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
}
#endif
printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f)); printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f));
} }
@@ -68,7 +56,6 @@ static void mainboard_final(device_t dev)
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {
/* Configure the MultiKey controller */ /* Configure the MultiKey controller */
// m3885_configure_multikey();
/* Enable LCD Backlight */ /* Enable LCD Backlight */
backlight_enable(); backlight_enable();
@@ -77,7 +64,6 @@ static void mainboard_enable(device_t dev)
outb(inb(0x60f) | (1 << 5), 0x60f); outb(inb(0x60f) | (1 << 5), 0x60f);
/* LCD panel type is SIO GPIO40-43 */ /* LCD panel type is SIO GPIO40-43 */
// display_id = inb(0x60f) & 0x0f;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3);
#if DUMP_RUNTIME_REGISTERS #if DUMP_RUNTIME_REGISTERS

6
src/mainboard/roda/rk886ex/mptable.c
View File

@@ -55,11 +55,11 @@ static void *smp_write_config_table(void *v)
/* Firewire 4:0.0 */ /* Firewire 4:0.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
// riser slot top 5:8.0 /* riser slot top 5:8.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
// riser slot middle 5:9.0 /* riser slot middle 5:9.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
// riser slot bottom 5:a.0 /* riser slot bottom 5:a.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
/* Onboard Ethernet */ /* Onboard Ethernet */

104
src/mainboard/roda/rk886ex/romstage.c
View File

@@ -14,7 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
// __PRE_RAM__ means: use "unsigned" for device, not a struct. /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@@ -41,47 +41,48 @@ void setup_ich7_gpios(void)
/* General Registers */ /* General Registers */
outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
// ------------------------------------------------------------ /* ------------------------------------------------------------
// 0 - GPO6 - Enable power of SATA channel 0 * 0 - GPO6 - Enable power of SATA channel 0
// 0 - GPO9 - Wireless LAN power on * 0 - GPO9 - Wireless LAN power on
// 0 - GPO15 - FAN on * 0 - GPO15 - FAN on
// 1 - GPO22 - FWH WP * 1 - GPO22 - FWH WP
// 1 - GPO24 - GPS on * 1 - GPO24 - GPS on
// 0 - GPO25 - External Antenna Mux on * 0 - GPO25 - External Antenna Mux on
// 0 - GPO26 - BT on * 0 - GPO26 - BT on
// 0 - GPO27 - GSM on * 0 - GPO27 - GSM on
*/
outl(0x01400000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ outl(0x01400000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
// ------------------------------------------------------------ /* ------------------------------------------------------------ */
/* Output Control Registers */ /* Output Control Registers */
outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */ /* Input Control Registers */
outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
// ------------------------------------------------------------ /* ------------------------------------------------------------ */
// 1 - GPO48 - FWH TBL# /* 1 - GPO48 - FWH TBL# */
outl(0x00010000, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ outl(0x00010000, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
// ------------------------------------------------------------ /* ------------------------------------------------------------ */
} }
static void ich7_enable_lpc(void) static void ich7_enable_lpc(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(lpt, 0) != 0) { if (read_option(lpt, 0) != 0) {
lpt_en = 1 << 2; // enable LPT lpt_en = 1 << 2; /* enable LPT */
} }
// Enable Serial IRQ /* Enable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// decode range /* decode range */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
// decode range /* decode range */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
// Enable 0x02e0 /* Enable 0x02e0 */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
// COM3 decode /* COM3 decode */
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
// COM4 decode /* COM4 decode */
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
} }
@@ -116,30 +117,30 @@ static void early_superio_config(void)
dev = PNP_DEV(0x2e, 0x00); dev = PNP_DEV(0x2e, 0x00);
pnp_enter_ext_func_mode(dev); pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes pnp_write_register(dev, 0x01, 0x94); /* Extended Parport modes */
pnp_write_register(dev, 0x02, 0x88); // UART power on pnp_write_register(dev, 0x02, 0x88); /* UART power on */
pnp_write_register(dev, 0x03, 0x72); // Floppy pnp_write_register(dev, 0x03, 0x72); /* Floppy */
pnp_write_register(dev, 0x04, 0x01); // EPP + SPP pnp_write_register(dev, 0x04, 0x01); /* EPP + SPP */
pnp_write_register(dev, 0x14, 0x03); // Floppy pnp_write_register(dev, 0x14, 0x03); /* Floppy */
pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy pnp_write_register(dev, 0x20, (0x3f0 >> 2)); /* Floppy */
pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base pnp_write_register(dev, 0x23, (0x378 >> 2)); /* PP base */
pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base pnp_write_register(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */
pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base pnp_write_register(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */
pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA pnp_write_register(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */
pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA pnp_write_register(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */
pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ pnp_write_register(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */
/* These are the SMI status registers in the SIO: */ /* These are the SMI status registers in the SIO: */
pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base pnp_write_register(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */
pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR pnp_write_register(dev, 0x31, 0x00); /* GPIO1 DIR */
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL pnp_write_register(dev, 0x32, 0x00); /* GPIO1 POL */
pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR pnp_write_register(dev, 0x33, 0x40); /* GPIO2 DIR */
pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL pnp_write_register(dev, 0x34, 0x00); /* GPIO2 POL */
pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR pnp_write_register(dev, 0x35, 0xff); /* GPIO3 DIR */
pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL pnp_write_register(dev, 0x36, 0x00); /* GPIO3 POL */
pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR pnp_write_register(dev, 0x37, 0xe0); /* GPIO4 DIR */
pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL pnp_write_register(dev, 0x38, 0x00); /* GPIO4 POL */
pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL pnp_write_register(dev, 0x39, 0x80); /* GPIO4 POL */
pnp_exit_ext_func_mode(dev); pnp_exit_ext_func_mode(dev);
} }
@@ -147,8 +148,6 @@ static void early_superio_config(void)
static void rcba_config(void) static void rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */ /* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042220; RCBA32(0x3100) = 0x00042220;
@@ -168,10 +167,7 @@ static void rcba_config(void)
/* Disable unused devices */ /* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required. RCBA32(0x3418) |= (1 << 0); /* Required. */
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
/* This should probably go into the ACPI OS Init trap */ /* This should probably go into the ACPI OS Init trap */
@@ -189,15 +185,15 @@ static void early_ich7_init(void)
uint8_t reg8; uint8_t reg8;
uint32_t reg32; uint32_t reg32;
// program secondary mlt XXX byte? /* program secondary mlt XXX byte? */
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status /* reset rtc power status */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
reg8 &= ~(1 << 2); reg8 &= ~(1 << 2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
// usb transient disconnect /* usb transient disconnect */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0); reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
@@ -231,7 +227,7 @@ static void early_ich7_init(void)
RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e0e) |= (1 << 7);
RCBA32(0x3e4e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7);
// next step only on ich7m b0 and later: /* next step only on ich7m b0 and later: */
reg32 = RCBA32(0x2034); reg32 = RCBA32(0x2034);
reg32 &= ~(0x0f << 16); reg32 &= ~(0x0f << 16);
reg32 |= (5 << 16); reg32 |= (5 << 16);
@@ -240,7 +236,7 @@ static void early_ich7_init(void)
static void init_artec_dongle(void) static void init_artec_dongle(void)
{ {
// Enable 4MB decoding /* Enable 4MB decoding */
outb(0xf1, 0x88); outb(0xf1, 0x88);
outb(0xf4, 0x88); outb(0xf4, 0x88);
} }

6
src/mainboard/roda/rk9/hda_verb.c
View File

@@ -18,9 +18,9 @@
const u32 cim_verb_data[] = { const u32 cim_verb_data[] = {
/* coreboot specific header */ /* coreboot specific header */
0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */
0x43528986, // Subsystem ID 0x43528986, /* Subsystem ID */
0x0000000c, // Number of entries 0x0000000c, /* Number of entries */
/* Pin Widget Verb Table */ /* Pin Widget Verb Table */

2
src/mainboard/roda/rk9/romstage.c
View File

@@ -14,7 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
// __PRE_RAM__ means: use "unsigned" for device, not a struct. /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>