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AGESA f14/f15tn/f16kb: Deduplicate RAM settings

Browse Source 
On AGESA f14/f15tn, various RAM-related options were defined in an enum.
However, the preprocessor mess can't compare enum values. To make AGESA
build, each board redefined them as macros, shadowing the enum elements.
Clean this up by replacing the enums with macros in AGESA headers, and
delete the now-redundant redefinitions from all the mainboards.

Note that AGESA f16kb already uses macros, but each mainboard still had
commented-out definitions. Remove them as well, as they are unnecessary.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-05-21 16:30:00 +02:00 committed by Nico Huber
parent 6482916111
commit ec6e03e4d8
27 changed files with 53 additions and 701 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/amd/inagua/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

27
src/mainboard/amd/olivehill/buildOpts.c
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@ -205,33 +205,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/amd/parmer/buildOpts.c
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@ -207,33 +207,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

24
src/mainboard/amd/persimmon/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

24
src/mainboard/amd/south_station/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

27
src/mainboard/amd/thatcher/buildOpts.c
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@ -207,33 +207,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

24
src/mainboard/amd/union_station/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

24
src/mainboard/asrock/e350m1/buildOpts.c
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@ -173,29 +173,5 @@
// This string MUST be exactly 12 characters long // This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

27
src/mainboard/asrock/imb-a180/buildOpts.c
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@ -205,33 +205,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/asus/am1i-a/buildOpts.c
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@ -218,33 +218,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/asus/f2a85-m/buildOpts.c
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@ -207,33 +207,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/bap/ode_e20XX/buildOpts.c
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@ -205,33 +205,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/biostar/a68n_5200/buildOpts.c
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@ -205,33 +205,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/biostar/am1ml/buildOpts.c
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@ -205,33 +205,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

24
src/mainboard/elmex/pcm205400/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

24
src/mainboard/gizmosphere/gizmo/buildOpts.c
View File

@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

27
src/mainboard/gizmosphere/gizmo2/buildOpts.c
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@ -205,33 +205,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/hp/abm/buildOpts.c
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@ -210,33 +210,6 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
//#define DDR400_FREQUENCY 200 ///< DDR 400
//#define DDR533_FREQUENCY 266 ///< DDR 533
//#define DDR667_FREQUENCY 333 ///< DDR 667
//#define DDR800_FREQUENCY 400 ///< DDR 800
//#define DDR1066_FREQUENCY 533 ///< DDR 1066
//#define DDR1333_FREQUENCY 667 ///< DDR 1333
//#define DDR1600_FREQUENCY 800 ///< DDR 1600
//#define DDR1866_FREQUENCY 933 ///< DDR 1866
//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
//
///* QUANDRANK_TYPE */
//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
//
///* USER_MEMORY_TIMING_MODE */
//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
//
///* POWER_DOWN_MODE */
//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

27
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
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@ -208,33 +208,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

30
src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
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@ -160,36 +160,6 @@
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
/**
* AGESA configuration values selection.
* Uncomment and specify the value for the configuration options
* needed by the system.
*/
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 /**< DDR 400 */
#define DDR533_FREQUENCY 266 /**< DDR 533 */
#define DDR667_FREQUENCY 333 /**< DDR 667 */
#define DDR800_FREQUENCY 400 /**< DDR 800 */
#define DDR1066_FREQUENCY 533 /**< DDR 1066 */
#define DDR1333_FREQUENCY 667 /**< DDR 1333 */
#define DDR1600_FREQUENCY 800 /**< DDR 1600 */
#define DDR1866_FREQUENCY 933 /**< DDR 1866 */
#define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */
#define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 /**< Use best rate possible */
#define TIMING_MODE_LIMITED 1 /**< Set user top limit */
#define TIMING_MODE_SPECIFIC 2 /**< Set user specified speed */
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */
#define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */
/* AGESA nonsense: this header depends on the definitions above */ /* AGESA nonsense: this header depends on the definitions above */
/* Instantiate all solution relevant data. */ /* Instantiate all solution relevant data. */
#include <PlatformInstall.h> #include <PlatformInstall.h>

27
src/mainboard/lenovo/g505s/buildOpts.c
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@ -208,33 +208,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

24
src/mainboard/lippert/frontrunner-af/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

24
src/mainboard/lippert/toucan-af/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

27
src/mainboard/msi/ms7721/buildOpts.c
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@ -207,33 +207,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* /*
* Agesa optional capabilities selection. * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build. * Uncomment and mark FALSE those features you wish to include in the build.

24
src/mainboard/pcengines/apu1/buildOpts.c
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@ -167,29 +167,5 @@
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include <PlatformInstall.h> #include <PlatformInstall.h>

50
src/vendorcode/amd/agesa/f14/AGESA.h
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@ -1015,37 +1015,37 @@ typedef enum {
} TECHNOLOGY_TYPE; } TECHNOLOGY_TYPE;
/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
typedef enum { typedef unsigned int MEMORY_BUS_SPEED;
DDR400_FREQUENCY = 200, ///< DDR 400
DDR533_FREQUENCY = 266, ///< DDR 533 #define DDR400_FREQUENCY 200 ///< DDR 400
DDR667_FREQUENCY = 333, ///< DDR 667 #define DDR533_FREQUENCY 266 ///< DDR 533
DDR800_FREQUENCY = 400, ///< DDR 800 #define DDR667_FREQUENCY 333 ///< DDR 667
DDR1066_FREQUENCY = 533, ///< DDR 1066 #define DDR800_FREQUENCY 400 ///< DDR 800
DDR1333_FREQUENCY = 667, ///< DDR 1333 #define DDR1066_FREQUENCY 533 ///< DDR 1066
DDR1600_FREQUENCY = 800, ///< DDR 1600 #define DDR1333_FREQUENCY 667 ///< DDR 1333
DDR1866_FREQUENCY = 933, ///< DDR 1866 #define DDR1600_FREQUENCY 800 ///< DDR 1600
UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency #define DDR1866_FREQUENCY 933 ///< DDR 1866
} MEMORY_BUS_SPEED; #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
typedef enum { typedef unsigned int QUANDRANK_TYPE;
QUADRANK_REGISTERED, ///< Quadrank registered DIMM
QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
} QUANDRANK_TYPE; #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
typedef enum { typedef unsigned int USER_MEMORY_TIMING_MODE;
TIMING_MODE_AUTO, ///< Use best rate possible
TIMING_MODE_LIMITED, ///< Set user top limit #define TIMING_MODE_AUTO 0 ///< Use best rate possible
TIMING_MODE_SPECIFIC ///< Set user specified speed #define TIMING_MODE_LIMITED 1 ///< Set user top limit
} USER_MEMORY_TIMING_MODE; #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/// Build Configuration values for BLDCFG_POWER_DOWN_MODE /// Build Configuration values for BLDCFG_POWER_DOWN_MODE
typedef enum { typedef unsigned int POWER_DOWN_MODE;
POWER_DOWN_BY_CHANNEL, ///< Channel power down mode
POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
} POWER_DOWN_MODE; #define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode
/// Low voltage support /// Low voltage support
typedef enum { typedef enum {

56
src/vendorcode/amd/agesa/f15tn/AGESA.h
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@ -1382,40 +1382,40 @@ typedef enum {
} TECHNOLOGY_TYPE; } TECHNOLOGY_TYPE;
/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
typedef enum { typedef unsigned int MEMORY_BUS_SPEED;
DDR400_FREQUENCY = 200, ///< DDR 400
DDR533_FREQUENCY = 266, ///< DDR 533 #define DDR400_FREQUENCY 200 ///< DDR 400
DDR667_FREQUENCY = 333, ///< DDR 667 #define DDR533_FREQUENCY 266 ///< DDR 533
DDR800_FREQUENCY = 400, ///< DDR 800 #define DDR667_FREQUENCY 333 ///< DDR 667
DDR1066_FREQUENCY = 533, ///< DDR 1066 #define DDR800_FREQUENCY 400 ///< DDR 800
DDR1333_FREQUENCY = 667, ///< DDR 1333 #define DDR1066_FREQUENCY 533 ///< DDR 1066
DDR1600_FREQUENCY = 800, ///< DDR 1600 #define DDR1333_FREQUENCY 667 ///< DDR 1333
DDR1866_FREQUENCY = 933, ///< DDR 1866 #define DDR1600_FREQUENCY 800 ///< DDR 1600
DDR2100_FREQUENCY = 1050, ///< DDR 2100 #define DDR1866_FREQUENCY 933 ///< DDR 1866
DDR2133_FREQUENCY = 1066, ///< DDR 2133 #define DDR2100_FREQUENCY 1050 ///< DDR 2100
DDR2400_FREQUENCY = 1200, ///< DDR 2400 #define DDR2133_FREQUENCY 1066 ///< DDR 2133
UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency #define DDR2400_FREQUENCY 1200 ///< DDR 2400
} MEMORY_BUS_SPEED; #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
typedef enum { typedef unsigned int QUANDRANK_TYPE;
QUADRANK_REGISTERED, ///< Quadrank registered DIMM
QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
} QUANDRANK_TYPE; #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
typedef enum { typedef unsigned int USER_MEMORY_TIMING_MODE;
TIMING_MODE_AUTO, ///< Use best rate possible
TIMING_MODE_LIMITED, ///< Set user top limit #define TIMING_MODE_AUTO 0 ///< Use best rate possible
TIMING_MODE_SPECIFIC ///< Set user specified speed #define TIMING_MODE_LIMITED 1 ///< Set user top limit
} USER_MEMORY_TIMING_MODE; #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/// Build Configuration values for BLDCFG_POWER_DOWN_MODE /// Build Configuration values for BLDCFG_POWER_DOWN_MODE
typedef enum { typedef unsigned int POWER_DOWN_MODE;
POWER_DOWN_BY_CHANNEL, ///< Channel power down mode
POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
} POWER_DOWN_MODE; #define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode
/// Low voltage support /// Low voltage support
typedef enum { typedef enum {