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Uwe Hermann:

Browse Source 
here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2006-08-23 14:28:37 +00:00
parent 6a1540b606
commit eca92fb371
17 changed files with 992 additions and 1058 deletions
Download Patch File Download Diff File Expand all files Collapse all files

110
src/include/assert.h
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@ -1,59 +1,51 @@
/* /*
* $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/assert.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $ * assert.h: Debugging macros
* *
* assert.h: Debugging macros * Copyright (C) 2005 Digital Design Corporation
* *
* Copyright (C) 2005 Digital Design Corporation * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* This program is free software; you can redistribute it and/or modify * the Free Software Foundation; either version 2 of the License, or
* it under the terms of the GNU General Public License as published by * (at your option) any later version.
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* This program is distributed in the hope that it will be useful, * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* but WITHOUT ANY WARRANTY; without even the implied warranty of * GNU General Public License for more details.
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* You should have received a copy of the GNU General Public License * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* #ifndef __ASSERT_H_DEFINED
* $Log: assert.h,v $ #define __ASSERT_H_DEFINED
* Revision 1.1 2005/07/11 16:03:54 smagnani
* Initial revision. // ROMCC doesn't support __FILE__ or __LINE__ :^{
*
* #if DEBUG
*/ #ifdef __ROMCC__
#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); }
#ifndef __ASSERT_H_DEFINED #else
#define __ASSERT_H_DEFINED #define ASSERT(x) { \
if (!(x)) \
// ROMCC doesn't support __FILE__ or __LINE__ :^{ { \
printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
#if DEBUG die(""); \
#ifdef __ROMCC__ } \
#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); } }
#else #endif // __ROMCC__
#define ASSERT(x) { \ #else // !DEBUG
if (!(x)) \ #define ASSERT(x) { }
{ \ #endif
printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
die(""); \ #ifdef __ROMCC__
} \ #define BUG() { die("BUG encountered: system halted\r\n"); }
} #else
#endif // __ROMCC__ #define BUG() { \
#else // !DEBUG printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
#define ASSERT(x) { } die(""); \
#endif }
#endif
#ifdef __ROMCC__
#define BUG() { die("BUG encountered: system halted\r\n"); } #endif // __ASSERT_H_DEFINED
#else
#define BUG() { \
printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
die(""); \
}
#endif
#endif // __ASSERT_H_DEFINED

115
src/include/sdram_mode.h
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@ -1,62 +1,53 @@
/* /*
* $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $ * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
* *
* sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register * Copyright (C) 2005 Digital Design Corporation
* *
* * This program is free software; you can redistribute it and/or modify
* Copyright (C) 2005 Digital Design Corporation * it under the terms of the GNU General Public License as published by
* * the Free Software Foundation; either version 2 of the License, or
* This program is free software; you can redistribute it and/or modify * (at your option) any later version.
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or * This program is distributed in the hope that it will be useful,
* (at your option) any later version. * but WITHOUT ANY WARRANTY; without even the implied warranty of
* * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* This program is distributed in the hope that it will be useful, * GNU General Public License for more details.
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * You should have received a copy of the GNU General Public License
* GNU General Public License for more details. * along with this program; if not, write to the Free Software
* * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* You should have received a copy of the GNU General Public License */
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #ifndef __SDRAMMODE_H_DEFINED
* #define __SDRAMMODE_H_DEFINED
* $Log: sdram_mode.h,v $
* Revision 1.1 2005/07/11 16:03:54 smagnani // SDRAM Mode Register definitions, per JESD79D
* Initial revision. // These are transmitted via A0-A13
*
* // Burst length
*/ #define SDRAM_BURST_2 (1<<0)
#define SDRAM_BURST_4 (2<<0)
#ifndef __SDRAMMODE_H_DEFINED #define SDRAM_BURST_8 (3<<0)
#define __SDRAMMODE_H_DEFINED
#define SDRAM_BURST_SEQUENTIAL (0<<3)
// SDRAM Mode Register definitions, per JESD79D #define SDRAM_BURST_INTERLEAVED (1<<3)
// These are transmitted via A0-A13
#define SDRAM_CAS_2_0 (2<<4)
// Burst length #define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */
#define SDRAM_BURST_2 (1<<0) #define SDRAM_CAS_1_5 (5<<4) /* Optional */
#define SDRAM_BURST_4 (2<<0) #define SDRAM_CAS_2_5 (6<<4)
#define SDRAM_BURST_8 (3<<0) #define SDRAM_CAS_MASK (7<<4)
#define SDRAM_BURST_SEQUENTIAL (0<<3) #define SDRAM_MODE_NORMAL (0 << 7)
#define SDRAM_BURST_INTERLEAVED (1<<3) #define SDRAM_MODE_TEST (1 << 7)
#define SDRAM_MODE_DLL_RESET (2 << 7)
#define SDRAM_CAS_2_0 (2<<4)
#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */ // Extended Mode Register
#define SDRAM_CAS_1_5 (5<<4) /* Optional */
#define SDRAM_CAS_2_5 (6<<4) #define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
#define SDRAM_CAS_MASK (7<<4) #define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
#define SDRAM_MODE_NORMAL (0 << 7) #define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
#define SDRAM_MODE_TEST (1 << 7) #define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
#define SDRAM_MODE_DLL_RESET (2 << 7)
#endif // __SDRAMMODE_H_DEFINED
// Extended Mode Register
#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
#endif // __SDRAMMODE_H_DEFINED

170
src/include/spd.h
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@ -1,89 +1,81 @@
/* /*
* $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/spd.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $ * spd.h: Definitions for Serial Presence Detect (SPD) data
* * stored on SDRAM modules
* spd.h: Definitions for Serial Presence Detect (SPD) data *
* stored on SDRAM modules * Copyright (C) 2005 Digital Design Corporation
* *
* Copyright (C) 2005 Digital Design Corporation * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* This program is free software; you can redistribute it and/or modify * the Free Software Foundation; either version 2 of the License, or
* it under the terms of the GNU General Public License as published by * (at your option) any later version.
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* This program is distributed in the hope that it will be useful, * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* but WITHOUT ANY WARRANTY; without even the implied warranty of * GNU General Public License for more details.
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* You should have received a copy of the GNU General Public License * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* #ifndef __SPD_H_DEFINED
* $Log: spd.h,v $ #define __SPD_H_DEFINED
* Revision 1.1 2005/07/11 16:03:54 smagnani
* Initial revision. // Byte numbers
* #define SPD_MEMORY_TYPE 2
* #define SPD_NUM_ROWS 3
*/ #define SPD_NUM_COLUMNS 4
#define SPD_NUM_DIMM_BANKS 5
#ifndef __SPD_H_DEFINED #define SPD_MODULE_DATA_WIDTH_LSB 6
#define __SPD_H_DEFINED #define SPD_MODULE_DATA_WIDTH_MSB 7
#define SPD_MODULE_VOLTAGE 8
// Byte numbers #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
#define SPD_MEMORY_TYPE 2 #define SPD_DIMM_CONFIG_TYPE 11
#define SPD_NUM_ROWS 3 #define SPD_REFRESH 12
#define SPD_NUM_COLUMNS 4 #define SPD_PRIMARY_DRAM_WIDTH 13
#define SPD_NUM_DIMM_BANKS 5 #define SPD_SUPPORTED_BURST_LENGTHS 16
#define SPD_MODULE_DATA_WIDTH_LSB 6 #define SPD_NUM_BANKS_PER_DRAM 17
#define SPD_MODULE_DATA_WIDTH_MSB 7 #define SPD_ACCEPTABLE_CAS_LATENCIES 18
#define SPD_MODULE_VOLTAGE 8 #define SPD_MODULE_ATTRIBUTES 21
#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 #define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23
#define SPD_DIMM_CONFIG_TYPE 11 #define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25
#define SPD_REFRESH 12 #define SPD_MIN_ROW_PRECHARGE_TIME 27
#define SPD_PRIMARY_DRAM_WIDTH 13 #define SPD_MIN_RAS_TO_CAS_DELAY 29
#define SPD_SUPPORTED_BURST_LENGTHS 16 #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30
#define SPD_NUM_BANKS_PER_DRAM 17 #define SPD_ADDRESS_CMD_HOLD 33
#define SPD_ACCEPTABLE_CAS_LATENCIES 18
#define SPD_MODULE_ATTRIBUTES 21
#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23 // SPD_MEMORY_TYPE values
#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25 #define MEMORY_TYPE_SDRAM_DDR 7
#define SPD_MIN_ROW_PRECHARGE_TIME 27
#define SPD_MIN_RAS_TO_CAS_DELAY 29 // SPD_MODULE_VOLTAGE values
#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 #define SPD_VOLTAGE_SSTL2 4
#define SPD_ADDRESS_CMD_HOLD 33
// SPD_DIMM_CONFIG_TYPE values
#define ERROR_SCHEME_NONE 0
// SPD_MEMORY_TYPE values #define ERROR_SCHEME_PARITY 1
#define MEMORY_TYPE_SDRAM_DDR 7 #define ERROR_SCHEME_ECC 2
// SPD_MODULE_VOLTAGE values // SPD_ACCEPTABLE_CAS_LATENCIES values
#define SPD_VOLTAGE_SSTL2 4 #define SPD_CAS_LATENCY_1_0 0x01
#define SPD_CAS_LATENCY_1_5 0x02
// SPD_DIMM_CONFIG_TYPE values #define SPD_CAS_LATENCY_2_0 0x04
#define ERROR_SCHEME_NONE 0 #define SPD_CAS_LATENCY_2_5 0x08
#define ERROR_SCHEME_PARITY 1 #define SPD_CAS_LATENCY_3_0 0x10
#define ERROR_SCHEME_ECC 2 #define SPD_CAS_LATENCY_3_5 0x20
#define SPD_CAS_LATENCY_4_0 0x40
// SPD_ACCEPTABLE_CAS_LATENCIES values
#define SPD_CAS_LATENCY_1_0 0x01 // SPD_SUPPORTED_BURST_LENGTHS values
#define SPD_CAS_LATENCY_1_5 0x02 #define SPD_BURST_LENGTH_1 1
#define SPD_CAS_LATENCY_2_0 0x04 #define SPD_BURST_LENGTH_2 2
#define SPD_CAS_LATENCY_2_5 0x08 #define SPD_BURST_LENGTH_4 4
#define SPD_CAS_LATENCY_3_0 0x10 #define SPD_BURST_LENGTH_8 8
#define SPD_CAS_LATENCY_3_5 0x20 #define SPD_BURST_LENGTH_PAGE (1<<7)
#define SPD_CAS_LATENCY_4_0 0x40
// SPD_SUPPORTED_BURST_LENGTHS values // SPD_MODULE_ATTRIBUTES values
#define SPD_BURST_LENGTH_1 1 #define MODULE_BUFFERED 1
#define SPD_BURST_LENGTH_2 2 #define MODULE_REGISTERED 2
#define SPD_BURST_LENGTH_4 4
#define SPD_BURST_LENGTH_8 8 #endif // __SPD_H_DEFINED
#define SPD_BURST_LENGTH_PAGE (1<<7)
// SPD_MODULE_ATTRIBUTES values
#define MODULE_BUFFERED 1
#define MODULE_REGISTERED 2
#endif // __SPD_H_DEFINED

5
src/northbridge/intel/e7501/e7501.h
View File

@ -1,6 +1,4 @@
/* /*
* $Header$
*
* e7501.h: PCI configuration space for the Intel E7501 memory controller * e7501.h: PCI configuration space for the Intel E7501 memory controller
* *
* Copyright (C) 2005 Digital Design Corporation * Copyright (C) 2005 Digital Design Corporation
@ -18,9 +16,6 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* $Log$
*
*/ */

14
src/southbridge/intel/i82801ca/cmos_failover.c
View File

@ -1,19 +1,19 @@
//kind of cmos_err for ich3 //kind of cmos_err for ich3
#include "i82801ca.h" #include "i82801ca.h"
static void check_cmos_failed(void) static void check_cmos_failed(void)
{ {
#if HAVE_OPTION_TABLE #if HAVE_OPTION_TABLE
uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3); uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
if( byte & RTC_BATTERY_DEAD) { if( byte & RTC_BATTERY_DEAD) {
// Set boot_option and last_boot to 'Fallback', // Set boot_option and last_boot to 'Fallback',
// clear reboot_bits // clear reboot_bits
byte = cmos_read(RTC_BOOT_BYTE); byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c; byte &= 0x0c;
byte |= MAX_REBOOT_CNT << 4; byte |= MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE); cmos_write(byte, RTC_BOOT_BYTE);
} }
#endif #endif
} }

26
src/southbridge/intel/i82801ca/i82801ca.c
View File

@ -7,8 +7,8 @@
void i82801ca_enable(device_t dev) void i82801ca_enable(device_t dev)
{ {
unsigned int index = 0; unsigned int index = 0;
uint8_t bHasDisableBit = 0; uint8_t bHasDisableBit = 0;
uint16_t cur_disable_mask, new_disable_mask; uint16_t cur_disable_mask, new_disable_mask;
// all 82801ca devices are in bus 0 // all 82801ca devices are in bus 0
@ -19,22 +19,22 @@ void i82801ca_enable(device_t dev)
// Calculate disable bit position for specified device:function // Calculate disable bit position for specified device:function
// NOTE: For ICH-3, only the following devices can be disabled: // NOTE: For ICH-3, only the following devices can be disabled:
// D31:F1, D31:F3, D31:F5, D31:F6, // D31:F1, D31:F3, D31:F5, D31:F6,
// D29:F0, D29:F1, D29:F2 // D29:F0, D29:F1, D29:F2
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) { if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.u.pci.devfn); index = PCI_FUNC(dev->path.u.pci.devfn);
if ((index == 1) || (index == 3) || (index == 5) || (index == 6)) if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
bHasDisableBit = 1; bHasDisableBit = 1;
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) { } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn); index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
if (PCI_FUNC(dev->path.u.pci.devfn) < 3) if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
bHasDisableBit = 1; bHasDisableBit = 1;
} }
if (bHasDisableBit) { if (bHasDisableBit) {
cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
new_disable_mask = cur_disable_mask & ~(1<<index); // enable it new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
@ -43,7 +43,7 @@ void i82801ca_enable(device_t dev)
} }
if (new_disable_mask != cur_disable_mask) { if (new_disable_mask != cur_disable_mask) {
pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
} }
} }
} }

64
src/southbridge/intel/i82801ca/i82801ca.h
View File

@ -1,10 +1,10 @@
#ifndef I82801CA_H #ifndef I82801CA_H
#define I82801CA_H #define I82801CA_H
#ifndef __ROMCC__ #ifndef __ROMCC__
#include "chip.h" #include "chip.h"
extern void i82801ca_enable(device_t dev); extern void i82801ca_enable(device_t dev);
#endif #endif
#define PCI_DMA_CFG 0x90 #define PCI_DMA_CFG 0x90
@ -26,37 +26,37 @@ extern void i82801ca_enable(device_t dev);
#define FUNC_DIS 0xF2 #define FUNC_DIS 0xF2
// GEN_PMCON_3 bits // GEN_PMCON_3 bits
#define RTC_BATTERY_DEAD (1<<2) #define RTC_BATTERY_DEAD (1<<2)
#define RTC_POWER_FAILED (1<<1) #define RTC_POWER_FAILED (1<<1)
#define SLEEP_AFTER_POWER_FAIL (1<<0) #define SLEEP_AFTER_POWER_FAIL (1<<0)
/********************************************************************/ /********************************************************************/
/* IDE Controller */ /* IDE Controller */
/********************************************************************/ /********************************************************************/
// PCI Configuration Space (D31:F1) // PCI Configuration Space (D31:F1)
#define IDE_TIM_PRI 0x40 // IDE timings, primary #define IDE_TIM_PRI 0x40 // IDE timings, primary
#define IDE_TIM_SEC 0x42 // IDE timings, secondary #define IDE_TIM_SEC 0x42 // IDE timings, secondary
// IDE_TIM bits // IDE_TIM bits
#define IDE_DECODE_ENABLE (1<<15) #define IDE_DECODE_ENABLE (1<<15)
/********************************************************************/ /********************************************************************/
/* SMBus */ /* SMBus */
/********************************************************************/ /********************************************************************/
// PCI Configuration Space (D31:F3) // PCI Configuration Space (D31:F3)
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
// HOSTC bits // HOSTC bits
#define I2C_EN (1<<2) #define I2C_EN (1<<2)
#define SMB_SMI_EN (1<<1) #define SMB_SMI_EN (1<<1)
#define HST_EN (1<<0) #define HST_EN (1<<0)
#define SMBUS_IO_BASE 0x1000 #define SMBUS_IO_BASE 0x1000
// I/O registers (relative to SMBUS_IO_BASE) // I/O registers (relative to SMBUS_IO_BASE)
#define SMBHSTSTAT 0 #define SMBHSTSTAT 0
#define SMBHSTCTL 2 #define SMBHSTCTL 2
@ -69,7 +69,7 @@ extern void i82801ca_enable(device_t dev);
#define SMBSLVDATA 10 #define SMBSLVDATA 10
#define SMLINK_PIN_CTL 14 #define SMLINK_PIN_CTL 14
#define SMBUS_PIN_CTL 15 #define SMBUS_PIN_CTL 15
/* Between 1-10 seconds, We should never timeout normally /* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs. * Longer than this is just painful when a timeout condition occurs.
*/ */

2
src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
View File

@ -1,5 +1,5 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include "i82801ca.h" #include "i82801ca.h"
static void enable_smbus(void) static void enable_smbus(void)
{ {

2
src/southbridge/intel/i82801ca/i82801ca_ide.c
View File

@ -10,7 +10,7 @@ static void ide_init(struct device *dev)
{ {
/* Enable ide devices so the linux ide driver will work */ /* Enable ide devices so the linux ide driver will work */
uint16_t ideTimingConfig; uint16_t ideTimingConfig;
int enable_primary = 1; int enable_primary = 1;
int enable_secondary = 1; int enable_secondary = 1;
ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);

94
src/southbridge/intel/i82801ca/i82801ca_lpc.c
View File

@ -1,7 +1,7 @@
/* /*
* (C) 2003 Linux Networx, SuSE Linux AG * (C) 2003 Linux Networx, SuSE Linux AG
* (C) 2004 Tyan Computer * (C) 2004 Tyan Computer
* (c) 2005 Digital Design Corporation * (c) 2005 Digital Design Corporation
*/ */
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
@ -14,14 +14,14 @@
#include "i82801ca.h" #include "i82801ca.h"
#define NMI_OFF 0 #define NMI_OFF 0
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif #endif
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_ON 1
void i82801ca_enable_ioapic( struct device *dev) void i82801ca_enable_ioapic( struct device *dev)
{ {
@ -60,20 +60,20 @@ void i82801ca_enable_serial_irqs( struct device *dev)
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: i82801ca_lpc_route_dma // Function: i82801ca_lpc_route_dma
// Parameters: dev // Parameters: dev
// mask - identifies whether each channel should be used for PCI DMA // mask - identifies whether each channel should be used for PCI DMA
// (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
// Channel 4 is not used (reserved). // Channel 4 is not used (reserved).
// Return Value: None // Return Value: None
// Description: Route all DMA channels to either PCI or LPC. // Description: Route all DMA channels to either PCI or LPC.
// //
void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
{ {
uint16_t dmaConfig; uint16_t dmaConfig;
int channelIndex; int channelIndex;
dmaConfig = pci_read_config16(dev, PCI_DMA_CFG); dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
dmaConfig &= 0x300; // Preserve reserved bits dmaConfig &= 0x300; // Preserve reserved bits
for(channelIndex = 0; channelIndex < 8; channelIndex++) { for(channelIndex = 0; channelIndex < 8; channelIndex++) {
@ -87,26 +87,26 @@ void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
void i82801ca_rtc_init(struct device *dev) void i82801ca_rtc_init(struct device *dev)
{ {
uint32_t dword; uint32_t dword;
int rtc_failed; int rtc_failed;
int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD; rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
if (rtc_failed) { if (rtc_failed) {
// Clear the RTC_BATTERY_DEAD bit, but preserve // Clear the RTC_BATTERY_DEAD bit, but preserve
// the RTC_POWER_FAILED, G3 state, and reserved bits // the RTC_POWER_FAILED, G3 state, and reserved bits
// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits // NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
pmcon3 &= ~RTC_POWER_FAILED; pmcon3 &= ~RTC_POWER_FAILED;
} }
get_option(&pwr_on, "power_on_after_fail"); get_option(&pwr_on, "power_on_after_fail");
pmcon3 &= ~SLEEP_AFTER_POWER_FAIL; pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
if (!pwr_on) { if (!pwr_on) {
pmcon3 |= SLEEP_AFTER_POWER_FAIL; pmcon3 |= SLEEP_AFTER_POWER_FAIL;
} }
pci_write_config8(dev, GEN_PMCON_3, pmcon3); pci_write_config8(dev, GEN_PMCON_3, pmcon3);
printk_info("set power %s after power fail\n", printk_info("set power %s after power fail\n",
pwr_on ? "on" : "off"); pwr_on ? "on" : "off");
// See if the Safe Mode jumper is set // See if the Safe Mode jumper is set
dword = pci_read_config32(dev, GEN_STS); dword = pci_read_config32(dev, GEN_STS);
@ -142,14 +142,14 @@ void i82801ca_1f0_misc(struct device *dev)
// Enable access to the upper 128 byte bank of CMOS RAM // Enable access to the upper 128 byte bank of CMOS RAM
pci_write_config8(dev, RTC_CONF, 0x04); pci_write_config8(dev, RTC_CONF, 0x04);
// Decode 0x3F8-0x3FF (COM1) for COMA port, // Decode 0x3F8-0x3FF (COM1) for COMA port,
// 0x2F8-0x2FF (COM2) for COMB // 0x2F8-0x2FF (COM2) for COMB
pci_write_config8(dev, COM_DEC, 0x10); pci_write_config8(dev, COM_DEC, 0x10);
// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
// Enable COMA, COMB, LPT, floppy; // LPT decode defaults to 0x378-0x37F and 0x778-0x77F
// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
// Enable COMA, COMB, LPT, floppy;
// disable microcontroller, Super I/O, sound, gameport // disable microcontroller, Super I/O, sound, gameport
pci_write_config16(dev, LPC_EN, 0x000F); pci_write_config16(dev, LPC_EN, 0x000F);
} }
@ -179,18 +179,18 @@ static void lpc_init(struct device *dev)
pci_write_config8(dev, GEN_PMCON_3, byte); pci_write_config8(dev, GEN_PMCON_3, byte);
printk_info("set power %s after power fail\n", pwr_on?"on":"off"); printk_info("set power %s after power fail\n", pwr_on?"on":"off");
/* Set up NMI on errors */ /* Set up NMI on errors */
byte = inb(0x61); byte = inb(0x61);
byte &= ~(1 << 3); /* IOCHK# NMI Enable */ byte &= ~(1 << 3); /* IOCHK# NMI Enable */
byte &= ~(1 << 2); /* PCI SERR# Enable */ byte &= ~(1 << 2); /* PCI SERR# Enable */
outb(byte, 0x61); outb(byte, 0x61);
byte = inb(0x70); byte = inb(0x70);
nmi_option = NMI_OFF; nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi"); get_option(&nmi_option, "nmi");
if (nmi_option) { if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */ byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70); outb(byte, 0x70);
} }
/* Initialize the real time clock */ /* Initialize the real time clock */
i82801ca_rtc_init(dev); i82801ca_rtc_init(dev);

4
src/southbridge/intel/i82801ca/i82801ca_smbus.c
View File

@ -1,7 +1,7 @@
#include <smbus.h> #include <smbus.h>
#include <pci.h> #include <pci.h>
#include <arch/io.h> #include <arch/io.h>
#include "i82801ca.h" #include "i82801ca.h"
#define PM_BUS 0 #define PM_BUS 0
#define PM_DEVFN PCI_DEVFN(0x1f,3) #define PM_DEVFN PCI_DEVFN(0x1f,3)
@ -9,7 +9,7 @@
void smbus_enable(void) void smbus_enable(void)
{ {
/* iobase addr */ /* iobase addr */
pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* smbus enable */ /* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);

87
src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
View File

@ -1,62 +1,57 @@
/* /*
* $Header$ * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
* *
* lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip * Copyright (C) 2005 Digital Design Corporation
* *
* Copyright (C) 2005 Digital Design Corporation * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* This program is free software; you can redistribute it and/or modify * the Free Software Foundation; either version 2 of the License, or
* it under the terms of the GNU General Public License as published by * (at your option) any later version.
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* This program is distributed in the hope that it will be useful, * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* but WITHOUT ANY WARRANTY; without even the implied warranty of * GNU General Public License for more details.
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* You should have received a copy of the GNU General Public License * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* $Log$
*
*/
#include <arch/romcc_io.h> #include <arch/romcc_io.h>
#include "lpc47b272.h" #include "lpc47b272.h"
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: pnp_enter_conf_state // Function: pnp_enter_conf_state
// Parameters: dev - high 8 bits = Super I/O port // Parameters: dev - high 8 bits = Super I/O port
// Return Value: None // Return Value: None
// Description: Enable access to the LPC47B272's configuration registers. // Description: Enable access to the LPC47B272's configuration registers.
// //
static inline void pnp_enter_conf_state(device_t dev) { static inline void pnp_enter_conf_state(device_t dev) {
unsigned port = dev>>8; unsigned port = dev>>8;
outb(0x55, port); outb(0x55, port);
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: pnp_exit_conf_state // Function: pnp_exit_conf_state
// Parameters: dev - high 8 bits = Super I/O port // Parameters: dev - high 8 bits = Super I/O port
// Return Value: None // Return Value: None
// Description: Disable access to the LPC47B272's configuration registers. // Description: Disable access to the LPC47B272's configuration registers.
// //
static void pnp_exit_conf_state(device_t dev) { static void pnp_exit_conf_state(device_t dev) {
unsigned port = dev>>8; unsigned port = dev>>8;
outb(0xaa, port); outb(0xaa, port);
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: lpc47b272_enable_serial // Function: lpc47b272_enable_serial
// Parameters: dev - high 8 bits = Super I/O port, // Parameters: dev - high 8 bits = Super I/O port,
// low 8 bits = logical device number (per lpc47b272.h) // low 8 bits = logical device number (per lpc47b272.h)
// iobase - processor I/O port address to assign to this serial device // iobase - processor I/O port address to assign to this serial device
// Return Value: bool // Return Value: bool
// Description: Configure the base I/O port of the specified serial device // Description: Configure the base I/O port of the specified serial device
// and enable the serial device. // and enable the serial device.
// //
static void lpc47b272_enable_serial(device_t dev, unsigned iobase) static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{ {
pnp_enter_conf_state(dev); pnp_enter_conf_state(dev);

183
src/superio/smsc/lpc47b272/superio.c
View File

@ -1,30 +1,25 @@
/* /*
* $Header$ * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
* *
* superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
*
* Copyright 2000 AG Electronics Ltd. * Copyright 2000 AG Electronics Ltd.
* Copyright 2003-2004 Linux Networx * Copyright 2003-2004 Linux Networx
* Copyright 2004 Tyan * Copyright 2004 Tyan
* Copyright (C) 2005 Digital Design Corporation * Copyright (C) 2005 Digital Design Corporation
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* */
* $Log$
*
*/
#include <arch/io.h> #include <arch/io.h>
#include <device/device.h> #include <device/device.h>
@ -38,16 +33,16 @@
#include "chip.h" #include "chip.h"
#include "lpc47b272.h" #include "lpc47b272.h"
// Forward declarations // Forward declarations
static void enable_dev(device_t dev); static void enable_dev(device_t dev);
void lpc47b272_pnp_set_resources(device_t dev); void lpc47b272_pnp_set_resources(device_t dev);
void lpc47b272_pnp_set_resources(device_t dev); void lpc47b272_pnp_set_resources(device_t dev);
void lpc47b272_pnp_enable_resources(device_t dev); void lpc47b272_pnp_enable_resources(device_t dev);
void lpc47b272_pnp_enable(device_t dev); void lpc47b272_pnp_enable(device_t dev);
static void lpc47b272_init(device_t dev); static void lpc47b272_init(device_t dev);
static void pnp_enter_conf_state(device_t dev); static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev);
static void dump_pnp_device(device_t dev); static void dump_pnp_device(device_t dev);
@ -73,30 +68,30 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, }, { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, },
}; };
/**********************************************************************************/ /**********************************************************************************/
/* PUBLIC INTERFACE */ /* PUBLIC INTERFACE */
/**********************************************************************************/ /**********************************************************************************/
//----------------------------------------------------------------------------------
// Function: enable_dev
// Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None
// Description: Create device structures and allocate resources to devices
// specified in the pnp_dev_info array (above).
//
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &pnp_ops,
sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
pnp_dev_info);
}
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: lpc47b272_pnp_set_resources // Function: enable_dev
// Parameters: dev - pointer to structure describing a Super I/O device // Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None // Return Value: None
// Description: Configure the specified Super I/O device with the resources // Description: Create device structures and allocate resources to devices
// (I/O space, etc.) that have been allocated for it. // specified in the pnp_dev_info array (above).
//
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &pnp_ops,
sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
pnp_dev_info);
}
//----------------------------------------------------------------------------------
// Function: lpc47b272_pnp_set_resources
// Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None
// Description: Configure the specified Super I/O device with the resources
// (I/O space, etc.) that have been allocated for it.
// //
void lpc47b272_pnp_set_resources(device_t dev) void lpc47b272_pnp_set_resources(device_t dev)
{ {
@ -126,14 +121,14 @@ void lpc47b272_pnp_enable(device_t dev)
pnp_exit_conf_state(dev); pnp_exit_conf_state(dev);
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: lpc47b272_init // Function: lpc47b272_init
// Parameters: dev - pointer to structure describing a Super I/O device // Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None // Return Value: None
// Description: Initialize the specified Super I/O device. // Description: Initialize the specified Super I/O device.
// Devices other than COM ports and the keyboard controller are // Devices other than COM ports and the keyboard controller are
// ignored. For COM ports, we configure the baud rate. // ignored. For COM ports, we configure the baud rate.
// //
static void lpc47b272_init(device_t dev) static void lpc47b272_init(device_t dev)
{ {
struct superio_smsc_lpc47b272_config *conf = dev->chip_info; struct superio_smsc_lpc47b272_config *conf = dev->chip_info;
@ -160,68 +155,68 @@ static void lpc47b272_init(device_t dev)
break; break;
} }
} }
/**********************************************************************************/
/* PRIVATE FUNCTIONS */
/**********************************************************************************/
//---------------------------------------------------------------------------------- /**********************************************************************************/
// Function: pnp_enter_conf_state /* PRIVATE FUNCTIONS */
// Parameters: dev - pointer to structure describing a Super I/O device /**********************************************************************************/
// Return Value: None
// Description: Enable access to the LPC47B272's configuration registers. //----------------------------------------------------------------------------------
// // Function: pnp_enter_conf_state
static void pnp_enter_conf_state(device_t dev) // Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None
// Description: Enable access to the LPC47B272's configuration registers.
//
static void pnp_enter_conf_state(device_t dev)
{ {
outb(0x55, dev->path.u.pnp.port); outb(0x55, dev->path.u.pnp.port);
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: pnp_exit_conf_state // Function: pnp_exit_conf_state
// Parameters: dev - pointer to structure describing a Super I/O device // Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None // Return Value: None
// Description: Disable access to the LPC47B272's configuration registers. // Description: Disable access to the LPC47B272's configuration registers.
// //
static void pnp_exit_conf_state(device_t dev) static void pnp_exit_conf_state(device_t dev)
{ {
outb(0xaa, dev->path.u.pnp.port); outb(0xaa, dev->path.u.pnp.port);
} }
#if 0 #if 0
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: dump_pnp_device // Function: dump_pnp_device
// Parameters: dev - pointer to structure describing a Super I/O device // Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None // Return Value: None
// Description: Print the values of all of the LPC47B272's configuration registers. // Description: Print the values of all of the LPC47B272's configuration registers.
// NOTE: The LPC47B272 must be in configuration mode when this // NOTE: The LPC47B272 must be in configuration mode when this
// function is called. // function is called.
// //
static void dump_pnp_device(device_t dev) static void dump_pnp_device(device_t dev)
{ {
int register_index; int register_index;
print_debug("\r\n"); print_debug("\r\n");
for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) { for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value; uint8_t register_value;
if ((register_index & 0x0f) == 0) { if ((register_index & 0x0f) == 0) {
print_debug_hex8(register_index); print_debug_hex8(register_index);
print_debug_char(':'); print_debug_char(':');
} }
// Skip over 'register' that would cause exit from configuration mode // Skip over 'register' that would cause exit from configuration mode
if (register_index == 0xaa) if (register_index == 0xaa)
register_value = 0xaa; register_value = 0xaa;
else else
register_value = pnp_read_config(dev, register_index); register_value = pnp_read_config(dev, register_index);
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(register_value); print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) { if ((register_index & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\r\n");
} }
} }
print_debug("\r\n"); print_debug("\r\n");
} }
#endif #endif

87
src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
View File

@ -1,63 +1,58 @@
/* /*
* $Header$ * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
*
* lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
* derived from lpc47n217 * derived from lpc47n217
* *
* Copyright (C) 2005 Digital Design Corporation * Copyright (C) 2005 Digital Design Corporation
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* */
* $Log$
*
*/
#include <arch/romcc_io.h> #include <arch/romcc_io.h>
#include "lpc47m10x.h" #include "lpc47m10x.h"
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: pnp_enter_conf_state // Function: pnp_enter_conf_state
// Parameters: dev - high 8 bits = Super I/O port // Parameters: dev - high 8 bits = Super I/O port
// Return Value: None // Return Value: None
// Description: Enable access to the LPC47M10X2's configuration registers. // Description: Enable access to the LPC47M10X2's configuration registers.
// //
static inline void pnp_enter_conf_state(device_t dev) { static inline void pnp_enter_conf_state(device_t dev) {
unsigned port = dev>>8; unsigned port = dev>>8;
outb(0x55, port); outb(0x55, port);
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: pnp_exit_conf_state // Function: pnp_exit_conf_state
// Parameters: dev - high 8 bits = Super I/O port // Parameters: dev - high 8 bits = Super I/O port
// Return Value: None // Return Value: None
// Description: Disable access to the LPC47M10X2's configuration registers. // Description: Disable access to the LPC47M10X2's configuration registers.
// //
static void pnp_exit_conf_state(device_t dev) { static void pnp_exit_conf_state(device_t dev) {
unsigned port = dev>>8; unsigned port = dev>>8;
outb(0xaa, port); outb(0xaa, port);
} }
//---------------------------------------------------------------------------------- //----------------------------------------------------------------------------------
// Function: lpc47b272_enable_serial // Function: lpc47b272_enable_serial
// Parameters: dev - high 8 bits = Super I/O port, // Parameters: dev - high 8 bits = Super I/O port,
// low 8 bits = logical device number (per lpc47b272.h) // low 8 bits = logical device number (per lpc47b272.h)
// iobase - processor I/O port address to assign to this serial device // iobase - processor I/O port address to assign to this serial device
// Return Value: bool // Return Value: bool
// Description: Configure the base I/O port of the specified serial device // Description: Configure the base I/O port of the specified serial device
// and enable the serial device. // and enable the serial device.
// //
static void lpc47b272_enable_serial(device_t dev, unsigned iobase) static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{ {
pnp_enter_conf_state(dev); pnp_enter_conf_state(dev);

5
src/superio/smsc/lpc47m10x/superio.c
View File

@ -1,6 +1,4 @@
/* /*
* $Header$
*
* superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
* *
* Copyright 2000 AG Electronics Ltd. * Copyright 2000 AG Electronics Ltd.
@ -22,9 +20,6 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* $Log$
*
*/ */
#include <arch/io.h> #include <arch/io.h>

302
src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
View File

@ -1,155 +1,147 @@
/* /*
* $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $ * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
* *
* lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip * Copyright (C) 2005 Digital Design Corporation
* *
* Copyright (C) 2005 Digital Design Corporation * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* This program is free software; you can redistribute it and/or modify * the Free Software Foundation; either version 2 of the License, or
* it under the terms of the GNU General Public License as published by * (at your option) any later version.
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* This program is distributed in the hope that it will be useful, * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* but WITHOUT ANY WARRANTY; without even the implied warranty of * GNU General Public License for more details.
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* You should have received a copy of the GNU General Public License * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* #include <arch/romcc_io.h>
* $Log: lpc47n217_early_serial.c,v $ #include <assert.h>
* Revision 1.1.1.1 2005/07/11 15:28:51 smagnani #include "lpc47n217.h"
* Initial revision.
* //----------------------------------------------------------------------------------
* // Function: pnp_enter_conf_state
*/ // Parameters: dev - high 8 bits = Super I/O port
// Return Value: None
#include <arch/romcc_io.h> // Description: Enable access to the LPC47N217's configuration registers.
#include <assert.h> //
#include "lpc47n217.h" static inline void pnp_enter_conf_state(device_t dev) {
unsigned port = dev>>8;
//---------------------------------------------------------------------------------- outb(0x55, port);
// Function: pnp_enter_conf_state }
// Parameters: dev - high 8 bits = Super I/O port
// Return Value: None //----------------------------------------------------------------------------------
// Description: Enable access to the LPC47N217's configuration registers. // Function: pnp_exit_conf_state
// // Parameters: dev - high 8 bits = Super I/O port
static inline void pnp_enter_conf_state(device_t dev) { // Return Value: None
unsigned port = dev>>8; // Description: Disable access to the LPC47N217's configuration registers.
outb(0x55, port); //
} static void pnp_exit_conf_state(device_t dev) {
unsigned port = dev>>8;
//---------------------------------------------------------------------------------- outb(0xaa, port);
// Function: pnp_exit_conf_state }
// Parameters: dev - high 8 bits = Super I/O port
// Return Value: None //----------------------------------------------------------------------------------
// Description: Disable access to the LPC47N217's configuration registers. // Function: lpc47n217_pnp_set_iobase
// // Parameters: dev - high 8 bits = Super I/O port,
static void pnp_exit_conf_state(device_t dev) { // low 8 bits = logical device number (per lpc47n217.h)
unsigned port = dev>>8; // iobase - base I/O port for the logical device
outb(0xaa, port); // Return Value: None
} // Description: Program the base I/O port for the specified logical device.
//
//---------------------------------------------------------------------------------- void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
// Function: lpc47n217_pnp_set_iobase {
// Parameters: dev - high 8 bits = Super I/O port, // LPC47N217 requires base ports to be a multiple of 4
// low 8 bits = logical device number (per lpc47n217.h) ASSERT(!(iobase & 0x3));
// iobase - base I/O port for the logical device
// Return Value: None switch(dev & 0xFF) {
// Description: Program the base I/O port for the specified logical device. case LPC47N217_PP:
// pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase) break;
{
// LPC47N217 requires base ports to be a multiple of 4 case LPC47N217_SP1:
ASSERT(!(iobase & 0x3)); pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
switch(dev & 0xFF) {
case LPC47N217_PP: case LPC47N217_SP2:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break; break;
case LPC47N217_SP1: default:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break;
break; }
}
case LPC47N217_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); //----------------------------------------------------------------------------------
break; // Function: lpc47n217_pnp_set_enable
// Parameters: dev - high 8 bits = Super I/O port,
default: // low 8 bits = logical device number (per lpc47n217.h)
break; // enable - 0 to disable, anythig else to enable
} // Return Value: None
} // Description: Enable or disable the specified logical device.
// Technically, a full disable requires setting the device's base
//---------------------------------------------------------------------------------- // I/O port below 0x100. We don't do that here, because we don't
// Function: lpc47n217_pnp_set_enable // have access to a data structure that specifies what the 'real'
// Parameters: dev - high 8 bits = Super I/O port, // base port is (when asked to enable the device). Also the function
// low 8 bits = logical device number (per lpc47n217.h) // is used only to disable the device while its true base port is
// enable - 0 to disable, anythig else to enable // programmed (see lpc47n217_enable_serial() below).
// Return Value: None //
// Description: Enable or disable the specified logical device. void lpc47n217_pnp_set_enable(device_t dev, int enable)
// Technically, a full disable requires setting the device's base {
// I/O port below 0x100. We don't do that here, because we don't uint8_t power_register = 0;
// have access to a data structure that specifies what the 'real' uint8_t power_mask = 0;
// base port is (when asked to enable the device). Also the function uint8_t current_power;
// is used only to disable the device while its true base port is uint8_t new_power;
// programmed (see lpc47n217_enable_serial() below).
// switch(dev & 0xFF) {
void lpc47n217_pnp_set_enable(device_t dev, int enable) case LPC47N217_PP:
{ power_register = 0x01;
uint8_t power_register = 0; power_mask = 0x04;
uint8_t power_mask = 0; break;
uint8_t current_power;
uint8_t new_power; case LPC47N217_SP1:
power_register = 0x02;
switch(dev & 0xFF) { power_mask = 0x08;
case LPC47N217_PP: break;
power_register = 0x01;
power_mask = 0x04; case LPC47N217_SP2:
break; power_register = 0x02;
power_mask = 0x80;
case LPC47N217_SP1: break;
power_register = 0x02;
power_mask = 0x08; default:
break; return;
}
case LPC47N217_SP2:
power_register = 0x02; current_power = pnp_read_config(dev, power_register);
power_mask = 0x80; new_power = current_power & ~power_mask; // disable by default
break;
if (enable)
default: new_power |= power_mask; // Enable
return;
} pnp_write_config(dev, power_register, new_power);
}
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; // disable by default //----------------------------------------------------------------------------------
// Function: lpc47n217_enable_serial
if (enable) // Parameters: dev - high 8 bits = Super I/O port,
new_power |= power_mask; // Enable // low 8 bits = logical device number (per lpc47n217.h)
// iobase - processor I/O port address to assign to this serial device
pnp_write_config(dev, power_register, new_power); // Return Value: bool
} // Description: Configure the base I/O port of the specified serial device
// and enable the serial device.
//---------------------------------------------------------------------------------- //
// Function: lpc47n217_enable_serial static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
// Parameters: dev - high 8 bits = Super I/O port, {
// low 8 bits = logical device number (per lpc47n217.h) // NOTE: Cannot use pnp_set_XXX() here because they assume chip
// iobase - processor I/O port address to assign to this serial device // support for logical devices, which the LPC47N217 doesn't have
// Return Value: bool
// Description: Configure the base I/O port of the specified serial device pnp_enter_conf_state(dev);
// and enable the serial device. lpc47n217_pnp_set_enable(dev, 0);
// lpc47n217_pnp_set_iobase(dev, iobase);
static void lpc47n217_enable_serial(device_t dev, unsigned iobase) lpc47n217_pnp_set_enable(dev, 1);
{ pnp_exit_conf_state(dev);
// NOTE: Cannot use pnp_set_XXX() here because they assume chip }
// support for logical devices, which the LPC47N217 doesn't have
pnp_enter_conf_state(dev);
lpc47n217_pnp_set_enable(dev, 0);
lpc47n217_pnp_set_iobase(dev, iobase);
lpc47n217_pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}

780
src/superio/smsc/lpc47n217/superio.c
View File

@ -1,394 +1,386 @@
/* /*
* $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $ * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
* *
* superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip * Based on LinuxBIOS code for SMSC 47B397:
* * Copyright 2000 AG Electronics Ltd.
* Based on LinuxBIOS code for SMSC 47B397: * Copyright 2003-2004 Linux Networx
* Copyright 2000 AG Electronics Ltd. * Copyright 2004 Tyan
* Copyright 2003-2004 Linux Networx *
* Copyright 2004 Tyan * Copyright (C) 2005 Digital Design Corporation
* *
* Copyright (C) 2005 Digital Design Corporation * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* This program is free software; you can redistribute it and/or modify * the Free Software Foundation; either version 2 of the License, or
* it under the terms of the GNU General Public License as published by * (at your option) any later version.
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* This program is distributed in the hope that it will be useful, * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* but WITHOUT ANY WARRANTY; without even the implied warranty of * GNU General Public License for more details.
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* You should have received a copy of the GNU General Public License * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* #include <arch/io.h>
* $Log: superio.c,v $ #include <device/device.h>
* Revision 1.1.1.1 2005/07/11 15:28:51 smagnani #include <device/pnp.h>
* Initial revision. #include <console/console.h>
* #include <device/smbus.h>
* #include <string.h>
*/ #include <bitops.h>
#include <uart8250.h>
#include <arch/io.h> #include <assert.h>
#include <device/device.h> #include "chip.h"
#include <device/pnp.h> #include "lpc47n217.h"
#include <console/console.h>
#include <device/smbus.h> // Forward declarations
#include <string.h> static void enable_dev(device_t dev);
#include <bitops.h> void lpc47n217_pnp_set_resources(device_t dev);
#include <uart8250.h> void lpc47n217_pnp_enable_resources(device_t dev);
#include <assert.h> void lpc47n217_pnp_enable(device_t dev);
#include "chip.h" static void lpc47n217_init(device_t dev);
#include "lpc47n217.h"
static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
// Forward declarations void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
static void enable_dev(device_t dev); void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
void lpc47n217_pnp_set_resources(device_t dev); void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
void lpc47n217_pnp_enable_resources(device_t dev); void lpc47n217_pnp_set_enable(device_t dev, int enable);
void lpc47n217_pnp_enable(device_t dev);
static void lpc47n217_init(device_t dev); static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
void lpc47n217_pnp_set_drq(device_t dev, unsigned drq); struct chip_operations superio_smsc_lpc47n217_ops = {
void lpc47n217_pnp_set_irq(device_t dev, unsigned irq); CHIP_NAME("smsc lpc47n217")
void lpc47n217_pnp_set_enable(device_t dev, int enable); .enable_dev = enable_dev,
};
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev); static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = lpc47n217_pnp_set_resources,
struct chip_operations superio_smsc_lpc47n217_ops = { .enable_resources = lpc47n217_pnp_enable_resources,
CHIP_NAME("smsc lpc47n217") .enable = lpc47n217_pnp_enable,
.enable_dev = enable_dev, .init = lpc47n217_init,
}; };
static struct device_operations ops = { static struct pnp_info pnp_dev_info[] = {
.read_resources = pnp_read_resources, { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
.set_resources = lpc47n217_pnp_set_resources, { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
.enable_resources = lpc47n217_pnp_enable_resources, { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
.enable = lpc47n217_pnp_enable, };
.init = lpc47n217_init,
}; /**********************************************************************************/
/* PUBLIC INTERFACE */
static struct pnp_info pnp_dev_info[] = { /**********************************************************************************/
{ &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, //----------------------------------------------------------------------------------
{ &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, } // Function: enable_dev
}; // Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None
/**********************************************************************************/ // Description: Create device structures and allocate resources to devices
/* PUBLIC INTERFACE */ // specified in the pnp_dev_info array (above).
/**********************************************************************************/ //
static void enable_dev(device_t dev)
//---------------------------------------------------------------------------------- {
// Function: enable_dev pnp_enable_devices(dev, &pnp_ops,
// Parameters: dev - pointer to structure describing a Super I/O device sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
// Return Value: None pnp_dev_info);
// Description: Create device structures and allocate resources to devices }
// specified in the pnp_dev_info array (above).
// //----------------------------------------------------------------------------------
static void enable_dev(device_t dev) // Function: lpc47n217_pnp_set_resources
{ // Parameters: dev - pointer to structure describing a Super I/O device
pnp_enable_devices(dev, &pnp_ops, // Return Value: None
sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), // Description: Configure the specified Super I/O device with the resources
pnp_dev_info); // (I/O space, etc.) that have been allocate for it.
} //
void lpc47n217_pnp_set_resources(device_t dev)
//---------------------------------------------------------------------------------- {
// Function: lpc47n217_pnp_set_resources int i;
// Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None pnp_enter_conf_state(dev);
// Description: Configure the specified Super I/O device with the resources
// (I/O space, etc.) that have been allocate for it. // NOTE: Cannot use pnp_set_resources() here because it assumes chip
// // support for logical devices, which the LPC47N217 doesn't have
void lpc47n217_pnp_set_resources(device_t dev) for(i = 0; i < dev->resources; i++)
{ lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
int i;
// dump_pnp_device(dev);
pnp_enter_conf_state(dev);
pnp_exit_conf_state(dev);
// NOTE: Cannot use pnp_set_resources() here because it assumes chip }
// support for logical devices, which the LPC47N217 doesn't have
for(i = 0; i < dev->resources; i++) void lpc47n217_pnp_enable_resources(device_t dev)
lpc47n217_pnp_set_resource(dev, &dev->resource[i]); {
pnp_enter_conf_state(dev);
// dump_pnp_device(dev);
// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
pnp_exit_conf_state(dev); // support for logical devices, which the LPC47N217 doesn't have
} lpc47n217_pnp_set_enable(dev, 1);
void lpc47n217_pnp_enable_resources(device_t dev) pnp_exit_conf_state(dev);
{ }
pnp_enter_conf_state(dev);
void lpc47n217_pnp_enable(device_t dev)
// NOTE: Cannot use pnp_enable_resources() here because it assumes chip {
// support for logical devices, which the LPC47N217 doesn't have pnp_enter_conf_state(dev);
lpc47n217_pnp_set_enable(dev, 1);
// NOTE: Cannot use pnp_set_enable() here because it assumes chip
pnp_exit_conf_state(dev); // support for logical devices, which the LPC47N217 doesn't have
}
if(dev->enabled) {
void lpc47n217_pnp_enable(device_t dev) lpc47n217_pnp_set_enable(dev, 1);
{ }
pnp_enter_conf_state(dev); else {
lpc47n217_pnp_set_enable(dev, 0);
// NOTE: Cannot use pnp_set_enable() here because it assumes chip }
// support for logical devices, which the LPC47N217 doesn't have
pnp_exit_conf_state(dev);
if(dev->enabled) { }
lpc47n217_pnp_set_enable(dev, 1);
} //----------------------------------------------------------------------------------
else { // Function: lpc47n217_init
lpc47n217_pnp_set_enable(dev, 0); // Parameters: dev - pointer to structure describing a Super I/O device
} // Return Value: None
// Description: Initialize the specified Super I/O device.
pnp_exit_conf_state(dev); // Devices other than COM ports are ignored.
} // For COM ports, we configure the baud rate.
//
//---------------------------------------------------------------------------------- static void lpc47n217_init(device_t dev)
// Function: lpc47n217_init {
// Parameters: dev - pointer to structure describing a Super I/O device struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
// Return Value: None struct resource *res0;
// Description: Initialize the specified Super I/O device.
// Devices other than COM ports are ignored. if (!dev->enabled)
// For COM ports, we configure the baud rate. return;
//
static void lpc47n217_init(device_t dev) switch(dev->path.u.pnp.device) {
{ case LPC47N217_SP1:
struct superio_smsc_lpc47n217_config* conf = dev->chip_info; res0 = find_resource(dev, PNP_IDX_IO0);
struct resource *res0; init_uart8250(res0->base, &conf->com1);
break;
if (!dev->enabled)
return; case LPC47N217_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
switch(dev->path.u.pnp.device) { init_uart8250(res0->base, &conf->com2);
case LPC47N217_SP1: break;
res0 = find_resource(dev, PNP_IDX_IO0); }
init_uart8250(res0->base, &conf->com1); }
break;
case LPC47N217_SP2: /**********************************************************************************/
res0 = find_resource(dev, PNP_IDX_IO0); /* PRIVATE FUNCTIONS */
init_uart8250(res0->base, &conf->com2); /**********************************************************************************/
break;
} static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
} {
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
printk_err("ERROR: %s %02x not allocated\n",
/**********************************************************************************/ dev_path(dev), resource->index);
/* PRIVATE FUNCTIONS */ return;
/**********************************************************************************/ }
static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) /* Now store the resource */
{ // NOTE: Cannot use pnp_set_XXX() here because they assume chip
if (!(resource->flags & IORESOURCE_ASSIGNED)) { // support for logical devices, which the LPC47N217 doesn't have
printk_err("ERROR: %s %02x not allocated\n",
dev_path(dev), resource->index); if (resource->flags & IORESOURCE_IO) {
return; lpc47n217_pnp_set_iobase(dev, resource->base);
} }
else if (resource->flags & IORESOURCE_DRQ) {
/* Now store the resource */ lpc47n217_pnp_set_drq(dev, resource->base);
// NOTE: Cannot use pnp_set_XXX() here because they assume chip }
// support for logical devices, which the LPC47N217 doesn't have else if (resource->flags & IORESOURCE_IRQ) {
lpc47n217_pnp_set_irq(dev, resource->base);
if (resource->flags & IORESOURCE_IO) { }
lpc47n217_pnp_set_iobase(dev, resource->base); else {
} printk_err("ERROR: %s %02x unknown resource type\n",
else if (resource->flags & IORESOURCE_DRQ) { dev_path(dev), resource->index);
lpc47n217_pnp_set_drq(dev, resource->base); return;
} }
else if (resource->flags & IORESOURCE_IRQ) { resource->flags |= IORESOURCE_STORED;
lpc47n217_pnp_set_irq(dev, resource->base);
} report_resource_stored(dev, resource, "");
else { }
printk_err("ERROR: %s %02x unknown resource type\n",
dev_path(dev), resource->index); void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
return; {
} ASSERT(!(iobase & 0x3));
resource->flags |= IORESOURCE_STORED;
switch(dev->path.u.pnp.device) {
report_resource_stored(dev, resource, ""); case LPC47N217_PP:
} pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
{ case LPC47N217_SP1:
ASSERT(!(iobase & 0x3)); pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
switch(dev->path.u.pnp.device) {
case LPC47N217_PP: case LPC47N217_SP2:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break; break;
case LPC47N217_SP1: default:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); BUG();
break; break;
}
case LPC47N217_SP2: }
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break; void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
{
default: if (dev->path.u.pnp.device == LPC47N217_PP) {
BUG(); const uint8_t PP_DMA_MASK = 0x0F;
break; const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
} uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
} uint8_t new_config;
void lpc47n217_pnp_set_drq(device_t dev, unsigned drq) ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
{ new_config = (current_config & ~PP_DMA_MASK) | drq;
if (dev->path.u.pnp.device == LPC47N217_PP) { pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
const uint8_t PP_DMA_MASK = 0x0F; } else {
const uint8_t PP_DMA_SELECTION_REGISTER = 0x26; BUG();
uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER); }
uint8_t new_config; }
ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
new_config = (current_config & ~PP_DMA_MASK) | drq; {
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config); uint8_t irq_config_register = 0;
} else { uint8_t irq_config_mask = 0;
BUG(); uint8_t current_config;
} uint8_t new_config;
}
switch(dev->path.u.pnp.device) {
void lpc47n217_pnp_set_irq(device_t dev, unsigned irq) case LPC47N217_PP:
{ irq_config_register = 0x27;
uint8_t irq_config_register = 0; irq_config_mask = 0x0F;
uint8_t irq_config_mask = 0; break;
uint8_t current_config;
uint8_t new_config; case LPC47N217_SP1:
irq_config_register = 0x28;
switch(dev->path.u.pnp.device) { irq_config_mask = 0xF0;
case LPC47N217_PP: irq <<= 4;
irq_config_register = 0x27; break;
irq_config_mask = 0x0F;
break; case LPC47N217_SP2:
irq_config_register = 0x28;
case LPC47N217_SP1: irq_config_mask = 0x0F;
irq_config_register = 0x28; break;
irq_config_mask = 0xF0;
irq <<= 4; default:
break; BUG();
return;
case LPC47N217_SP2: }
irq_config_register = 0x28;
irq_config_mask = 0x0F; ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range??
break;
current_config = pnp_read_config(dev, irq_config_register);
default: new_config = (current_config & ~irq_config_mask) | irq;
BUG(); pnp_write_config(dev, irq_config_register, new_config);
return; }
}
void lpc47n217_pnp_set_enable(device_t dev, int enable)
ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range?? {
uint8_t power_register = 0;
current_config = pnp_read_config(dev, irq_config_register); uint8_t power_mask = 0;
new_config = (current_config & ~irq_config_mask) | irq; uint8_t current_power;
pnp_write_config(dev, irq_config_register, new_config); uint8_t new_power;
}
switch(dev->path.u.pnp.device) {
void lpc47n217_pnp_set_enable(device_t dev, int enable) case LPC47N217_PP:
{ power_register = 0x01;
uint8_t power_register = 0; power_mask = 0x04;
uint8_t power_mask = 0; break;
uint8_t current_power;
uint8_t new_power; case LPC47N217_SP1:
power_register = 0x02;
switch(dev->path.u.pnp.device) { power_mask = 0x08;
case LPC47N217_PP: break;
power_register = 0x01;
power_mask = 0x04; case LPC47N217_SP2:
break; power_register = 0x02;
power_mask = 0x80;
case LPC47N217_SP1: break;
power_register = 0x02;
power_mask = 0x08; default:
break; BUG();
return;
case LPC47N217_SP2: }
power_register = 0x02;
power_mask = 0x80; current_power = pnp_read_config(dev, power_register);
break; new_power = current_power & ~power_mask; // disable by default
default: if (enable) {
BUG(); struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
return; lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
}
new_power |= power_mask; // Enable
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; // disable by default } else {
lpc47n217_pnp_set_iobase(dev, 0);
if (enable) { }
struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0); pnp_write_config(dev, power_register, new_power);
lpc47n217_pnp_set_iobase(dev, ioport_resource->base); }
new_power |= power_mask; // Enable
//----------------------------------------------------------------------------------
} else { // Function: pnp_enter_conf_state
lpc47n217_pnp_set_iobase(dev, 0); // Parameters: dev - pointer to structure describing a Super I/O device
} // Return Value: None
pnp_write_config(dev, power_register, new_power); // Description: Enable access to the LPC47N217's configuration registers.
} //
static void pnp_enter_conf_state(device_t dev)
{
//---------------------------------------------------------------------------------- outb(0x55, dev->path.u.pnp.port);
// Function: pnp_enter_conf_state }
// Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None //----------------------------------------------------------------------------------
// Description: Enable access to the LPC47N217's configuration registers. // Function: pnp_exit_conf_state
// // Parameters: dev - pointer to structure describing a Super I/O device
static void pnp_enter_conf_state(device_t dev) // Return Value: None
{ // Description: Disable access to the LPC47N217's configuration registers.
outb(0x55, dev->path.u.pnp.port); //
} static void pnp_exit_conf_state(device_t dev)
{
//---------------------------------------------------------------------------------- outb(0xaa, dev->path.u.pnp.port);
// Function: pnp_exit_conf_state }
// Parameters: dev - pointer to structure describing a Super I/O device
// Return Value: None #if 0
// Description: Disable access to the LPC47N217's configuration registers. //----------------------------------------------------------------------------------
// // Function: dump_pnp_device
static void pnp_exit_conf_state(device_t dev) // Parameters: dev - pointer to structure describing a Super I/O device
{ // Return Value: None
outb(0xaa, dev->path.u.pnp.port); // Description: Print the values of all of the LPC47N217's configuration registers.
} // NOTE: The LPC47N217 must be in configuration mode when this
// function is called.
#if 0 //
//---------------------------------------------------------------------------------- static void dump_pnp_device(device_t dev)
// Function: dump_pnp_device {
// Parameters: dev - pointer to structure describing a Super I/O device int register_index;
// Return Value: None print_debug("\r\n");
// Description: Print the values of all of the LPC47N217's configuration registers.
// NOTE: The LPC47N217 must be in configuration mode when this for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
// function is called. uint8_t register_value;
//
static void dump_pnp_device(device_t dev) if ((register_index & 0x0f) == 0) {
{ print_debug_hex8(register_index);
int register_index; print_debug_char(':');
print_debug("\r\n"); }
for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) { // Skip over 'register' that would cause exit from configuration mode
uint8_t register_value; if (register_index == 0xaa)
register_value = 0xaa;
if ((register_index & 0x0f) == 0) { else
print_debug_hex8(register_index); register_value = pnp_read_config(dev, register_index);
print_debug_char(':');
} print_debug_char(' ');
print_debug_hex8(register_value);
// Skip over 'register' that would cause exit from configuration mode if ((register_index & 0x0f) == 0x0f) {
if (register_index == 0xaa) print_debug("\r\n");
register_value = 0xaa; }
else }
register_value = pnp_read_config(dev, register_index);
print_debug("\r\n");
print_debug_char(' '); }
print_debug_hex8(register_value); #endif
if ((register_index & 0x0f) == 0x0f) {
print_debug("\r\n");
}
}
print_debug("\r\n");
}
#endif