diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
index 1aaec9b734..8c1f73513e 100644
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c
@@ -51,7 +51,7 @@ VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN
  *
  *
  */
-CODECENTRY AzaliaCodecAlc882Table[] =
+const static CODECENTRY AzaliaCodecAlc882Table[] =
 {
   {0x14, 0x01014010},
   {0x15, 0x01011012},
@@ -74,7 +74,7 @@ CODECENTRY AzaliaCodecAlc882Table[] =
  *
  *
  */
-CODECENTRY AzaliaCodecAlc262Table[] =
+const static CODECENTRY AzaliaCodecAlc262Table[] =
 {
   {0x14, 0x01014010},
   {0x15, 0x411111F0},
@@ -96,7 +96,7 @@ CODECENTRY AzaliaCodecAlc262Table[] =
  *
  *
  */
-CODECENTRY AzaliaCodecAlc269Table[] =
+const static CODECENTRY AzaliaCodecAlc269Table[] =
 {
   {0x12, 0x99A30960},
   {0x14, 0x99130110},
@@ -119,7 +119,7 @@ CODECENTRY AzaliaCodecAlc269Table[] =
  *
  *
  */
-CODECENTRY AzaliaCodecAlc861Table[] =
+const static CODECENTRY AzaliaCodecAlc861Table[] =
 {
   {0x01, 0x8086C601},
   {0x0B, 0x01014110},
@@ -142,7 +142,7 @@ CODECENTRY AzaliaCodecAlc861Table[] =
  *
  *
  */
-CODECENTRY AzaliaCodecAlc889Table[] =
+const static CODECENTRY AzaliaCodecAlc889Table[] =
 {
   {0x11, 0x411111F0},
   {0x14, 0x01014010},
@@ -166,7 +166,7 @@ CODECENTRY AzaliaCodecAlc889Table[] =
  *
  *
  */
-CODECENTRY AzaliaCodecAd1984Table[] =
+const static CODECENTRY AzaliaCodecAd1984Table[] =
 {
   {0x11, 0x0221401F},
   {0x12, 0x90170110},
@@ -188,7 +188,7 @@ CODECENTRY AzaliaCodecAd1984Table[] =
  *
  *
  */
-CODECENTRY FrontPanelAzaliaCodecTableList[] =
+const static CODECENTRY FrontPanelAzaliaCodecTableList[] =
 {
   {0x19, 0x02A19040},
   {0x1b, 0x02214020},
@@ -201,17 +201,17 @@ CODECENTRY FrontPanelAzaliaCodecTableList[] =
  *
  *
  */
-CODECTBLLIST azaliaCodecTableList[] =
+const static CODECTBLLIST azaliaCodecTableList[] =
 {
-  {0x010ec0880, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0882, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0883, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0885, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0889, &AzaliaCodecAlc889Table[0]},
-  {0x010ec0262, &AzaliaCodecAlc262Table[0]},
-  {0x010ec0269, &AzaliaCodecAlc269Table[0]},
-  {0x010ec0861, &AzaliaCodecAlc861Table[0]},
-  {0x011d41984, &AzaliaCodecAd1984Table[0]},
+  {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+  {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+  {0x010ec0883, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+  {0x010ec0885, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+  {0x010ec0889, (CODECENTRY*)&AzaliaCodecAlc889Table[0]},
+  {0x010ec0262, (CODECENTRY*)&AzaliaCodecAlc262Table[0]},
+  {0x010ec0269, (CODECENTRY*)&AzaliaCodecAlc269Table[0]},
+  {0x010ec0861, (CODECENTRY*)&AzaliaCodecAlc861Table[0]},
+  {0x011d41984, (CODECENTRY*)&AzaliaCodecAd1984Table[0]},
   { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
 };
 
diff --git a/src/vendorcode/amd/cimx/sb800/ECfanc.c b/src/vendorcode/amd/cimx/sb800/ECfanc.c
index 0b198c863e..44d1300626 100644
--- a/src/vendorcode/amd/cimx/sb800/ECfanc.c
+++ b/src/vendorcode/amd/cimx/sb800/ECfanc.c
@@ -31,7 +31,7 @@
  *
  *
  */
-UINT8 FunctionNumber[] =
+const static UINT8 FunctionNumber[] =
 {
   Fun_81,
   Fun_83,
@@ -46,7 +46,7 @@ UINT8 FunctionNumber[] =
  *
  *
  */
-UINT8 MaxZone[] =
+const static UINT8 MaxZone[] =
 {
   4,
   4,
@@ -61,7 +61,7 @@ UINT8 MaxZone[] =
  *
  *
  */
-UINT8 MaxRegister[] =
+const static UINT8 MaxRegister[] =
 {
   MSG_REG9,
   MSG_REGB,
diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc
index f6dcfc926b..9dab1b0280 100644
--- a/src/vendorcode/amd/cimx/sb800/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc
@@ -1,75 +1,86 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2010 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-# CIMX Root directory
-CIMX_ROOT = src/vendorcode/amd/cimx
-
-CIMX_INC  = -I$(src)/mainboard/$(MAINBOARDDIR)
-CIMX_INC  += -I$(src)/southbridge/amd/cimx_wrapper/sb800
-CIMX_INC  += -I$(CIMX_ROOT)/sb800
-#TODO merge withagesa lib functions
-CIMX_INC  += -I$(CIMX_ROOT)/lib
-
-# CIMX LIB files
-romstage-y += MEMLIB.c
-romstage-y += PCILIB.c
-romstage-y += IOLIB.c
-romstage-y += PMIOLIB.c
-romstage-y += AMDLIB.c
-romstage-y += SBPELIB.c
-romstage-y += AMDSBLIB.c
-romstage-y += SBPOR.c
-romstage-y += ECLIB.c
-romstage-y += EC.c
-ramstage-y += DISPATCHER.c
-
-ramstage-y += ACPILIB.c
-ramstage-y += AZALIA.c
-ramstage-y += DISPATCHER.c
-ramstage-y += ECfanc.c
-ramstage-y += ECfanLIB.c
-ramstage-y += GEC.c
-ramstage-y += Gpp.c
-ramstage-y += PMIO2LIB.c
-ramstage-y += SATA.c
-ramstage-y += SBCMN.c
-ramstage-y += SBMAIN.c
-ramstage-y += SBPOR.c
-ramstage-y += MEMLIB.c
-ramstage-y += PCILIB.c
-ramstage-y += IOLIB.c
-ramstage-y += PMIOLIB.c
-ramstage-y += AMDLIB.c
-ramstage-y += SBPELIB.c
-ramstage-y += AMDSBLIB.c
-ramstage-y += ECLIB.c
-ramstage-y += EC.c
-ramstage-y += SMM.c
-ramstage-y += USB.c
-#ramstage-y += LEGACY.c
-#ramstage-y += SbModInf.c
-
-CIMX_CFLAGS =
-export CIMX_ROOT
-export CIMX_INC
-export CIMX_CFLAGS
-CC := $(CC) $(CIMX_INC)
-
-#######################################################################
-
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+# CIMX Root directory
+CIMX_ROOT = src/vendorcode/amd/cimx
+
+CIMX_INC  = -I$(src)/mainboard/$(MAINBOARDDIR)
+CIMX_INC  += -I$(src)/southbridge/amd/cimx_wrapper/sb800
+CIMX_INC  += -I$(CIMX_ROOT)/sb800
+#TODO merge with agesa lib functions
+CIMX_INC  += -I$(CIMX_ROOT)/lib
+
+romstage-y += ACPILIB.c
+romstage-y += AZALIA.c
+romstage-y += DISPATCHER.c
+romstage-y += ECfanc.c
+romstage-y += ECfanLIB.c
+romstage-y += GEC.c
+romstage-y += Gpp.c
+romstage-y += PMIO2LIB.c
+romstage-y += SATA.c
+romstage-y += SBCMN.c
+romstage-y += SBMAIN.c
+romstage-y += SBPOR.c
+romstage-y += MEMLIB.c
+romstage-y += PCILIB.c
+romstage-y += IOLIB.c
+romstage-y += PMIOLIB.c
+romstage-y += AMDLIB.c
+romstage-y += SBPELIB.c
+romstage-y += AMDSBLIB.c
+romstage-y += ECLIB.c
+romstage-y += EC.c
+romstage-y += SMM.c
+romstage-y += USB.c
+
+ramstage-y += ACPILIB.c
+ramstage-y += AZALIA.c
+ramstage-y += DISPATCHER.c
+ramstage-y += ECfanc.c
+ramstage-y += ECfanLIB.c
+ramstage-y += GEC.c
+ramstage-y += Gpp.c
+ramstage-y += PMIO2LIB.c
+ramstage-y += SATA.c
+ramstage-y += SBCMN.c
+ramstage-y += SBMAIN.c
+ramstage-y += SBPOR.c
+ramstage-y += MEMLIB.c
+ramstage-y += PCILIB.c
+ramstage-y += IOLIB.c
+ramstage-y += PMIOLIB.c
+ramstage-y += AMDLIB.c
+ramstage-y += SBPELIB.c
+ramstage-y += AMDSBLIB.c
+ramstage-y += ECLIB.c
+ramstage-y += EC.c
+ramstage-y += SMM.c
+ramstage-y += USB.c
+#ramstage-y += LEGACY.c
+#ramstage-y += SbModInf.c
+
+CIMX_CFLAGS =
+export CIMX_ROOT
+export CIMX_INC
+export CIMX_CFLAGS
+CC := $(CC) $(CIMX_INC)
+
+#######################################################################
+
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 82891d4793..bdb76274c3 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -166,7 +166,7 @@ shutdownUnconnectedSataPortClock (
  *
  *
  */
-UINT32 sataIfCodeTable[] =
+const static UINT32 sataIfCodeTable[] =
 {
   0x01018F40, //sata class ID of IDE
   0x01040040, //sata class ID of RAID
@@ -182,7 +182,7 @@ UINT32 sataIfCodeTable[] =
  *
  *
  */
-UINT16 sataDeviceIDTable[] =
+const static UINT16 sataDeviceIDTable[] =
 {
   0x4390,  //sata device ID of IDE
   0x4392,  //sata device ID of RAID
@@ -198,7 +198,7 @@ UINT16 sataDeviceIDTable[] =
  *
  *
  */
-SATAPHYSETTING sataPhyTable[] =
+const static SATAPHYSETTING sataPhyTable[] =
 {
   {0x3006, 0x0056A607},
   {0x2006, 0x00061400},
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c
index 6ae736c81c..a596036d69 100644
--- a/src/vendorcode/amd/cimx/sb800/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c
@@ -73,7 +73,7 @@ VOID sbUsbPhySetting (IN  UINT32 Value);
  * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
  *
  */
-REG8MASK sbEarlyPostByteInitTable[] =
+const static REG8MASK sbEarlyPostByteInitTable[] =
 {
   // SMBUS Device (Bus 0, Dev 20, Func 0)
   {0x00, SMBUS_BUS_DEV_FUN, 0},
@@ -124,7 +124,7 @@ REG8MASK sbEarlyPostByteInitTable[] =
  * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
  *
  */
-AcpiRegWrite sbPmioEPostInitTable[] =
+const static AcpiRegWrite sbPmioEPostInitTable[] =
 {
   // HPET workaround
   {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
@@ -241,7 +241,7 @@ AcpiRegWrite sbPmioEPostInitTable[] =
  * abTblEntry800 - AB-Link Configuration Table for SB800
  *
  */
-ABTBLENTRY abTblEntry800[] =
+const static ABTBLENTRY abTblEntry800[] =
 {
   // RPR Enable downstream posted transactions to pass non-posted transactions.
   {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
@@ -287,7 +287,7 @@ ABTBLENTRY abTblEntry800[] =
  * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
  *
  */
-ABTBLENTRY SbPcieOrderRule[] =
+const static ABTBLENTRY SbPcieOrderRule[] =
 {
 // abPostPassNpDownStreamTbl
   {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},