mb/lenovo/w520: Add ThinkPad W520 support
Tested and working: * 4 RAM-slots * Speakers * PCIe Wifi * Camera * Fan * Touchpad, trackpoint and keyboard * Ethernet * Keyboard ACPI events * USB 3.0 * SD-card reader * Native graphics (LCD panel) * Harddisk in Ultrabay * SeaBIOS payloads ** Debian Live ** Debian testing 4.14.0-3-amd64 * GRUB ** Debian Live ** Debian testing 4.14.0-3-amd64 Not working: * Displayport and VGA output (requires VGA option ROM and ACPI switch call) Not tested: * Intel VGA option ROM * ACPI events related to ultrabay * Smart card reader * Docking station Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/23564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Nico Rikken
committed by
Patrick Georgi
Patrick Georgi
parent
3f7de0686d
commit
ecea3d450c
@@ -1,7 +1,5 @@
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if BOARD_LENOVO_T520
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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config BOARD_LENOVO_BASEBOARD_T520
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def_bool n
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA988B
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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@@ -23,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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# Workaround for EC/KBC IRQ1.
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select SERIRQ_CONTINUOUS_MODE
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if BOARD_LENOVO_BASEBOARD_T520
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config HAVE_IFD_BIN
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bool
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default n
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@@ -31,13 +31,24 @@ config HAVE_ME_BIN
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bool
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default n
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config VARIANT_DIR
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string
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default "t520" if BOARD_LENOVO_T520
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default "w520" if BOARD_LENOVO_W520
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config MAINBOARD_DIR
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string
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default lenovo/t520
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config DEVICETREE
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string
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default "variants/t520/devicetree.cb" if BOARD_LENOVO_T520
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default "variants/w520/devicetree.cb" if BOARD_LENOVO_W520
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config MAINBOARD_PART_NUMBER
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string
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default "ThinkPad T520"
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default "ThinkPad T520" if BOARD_LENOVO_T520
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default "ThinkPad W520" if BOARD_LENOVO_W520
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config MAX_CPUS
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int
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@@ -71,4 +82,4 @@ config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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endif # BOARD_LENOVO_T520
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endif
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@@ -1,2 +1,7 @@
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config BOARD_LENOVO_T520
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bool "ThinkPad T520"
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select BOARD_LENOVO_BASEBOARD_T520
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config BOARD_LENOVO_W520
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bool "ThinkPad W520"
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select BOARD_LENOVO_BASEBOARD_T520
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@@ -14,4 +14,5 @@
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##
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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romstage-y += gpio.c
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romstage-y += variants/$(VARIANT_DIR)/gpio.c
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romstage-y += variants/$(VARIANT_DIR)/romstage.c
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@@ -1,6 +1,8 @@
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Vendor name: Lenovo
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Board name: ThinkPad T520 baseboard
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Category: laptop
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ROM package: WSON-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Flashrom support: y
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Release year: 2011
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@@ -84,7 +84,7 @@ void mainboard_rcba_config(void)
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
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{ 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
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{ 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */
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{ 1, 2, -1 }, /* P2: wimax / WLAN */
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{ 1, 1, -1 }, /* P3: WWAN, no OC */
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{ 1, 1, -1 }, /* P4: smartcard, no OC */
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@@ -99,11 +99,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
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};
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void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
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read_spd (&spd[0], 0x50, id_only);
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read_spd (&spd[2], 0x51, id_only);
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}
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void mainboard_early_init(int s3resume)
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{
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hybrid_graphics_init();
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8
src/mainboard/lenovo/t520/variants/t520/board_info.txt
Normal file
8
src/mainboard/lenovo/t520/variants/t520/board_info.txt
Normal file
@@ -0,0 +1,8 @@
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Vendor name: Lenovo
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Board name: ThinkPad T520
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Category: laptop
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ROM package: WSON-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2011
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24
src/mainboard/lenovo/t520/variants/t520/romstage.c
Normal file
24
src/mainboard/lenovo/t520/variants/t520/romstage.c
Normal file
@@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <northbridge/intel/sandybridge/raminit_native.h>
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[2], 0x51, id_only);
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}
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8
src/mainboard/lenovo/t520/variants/w520/board_info.txt
Normal file
8
src/mainboard/lenovo/t520/variants/w520/board_info.txt
Normal file
@@ -0,0 +1,8 @@
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Vendor name: Lenovo
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Board name: ThinkPad W520
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Category: laptop
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ROM package: WSON-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2011
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168
src/mainboard/lenovo/t520/variants/w520/devicetree.cb
Normal file
168
src/mainboard/lenovo/t520/variants/w520/devicetree.cb
Normal file
@@ -0,0 +1,168 @@
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chip northbridge/intel/sandybridge
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "0" # LVDS
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register "gpu_panel_power_cycle_delay" = "5"
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register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
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register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
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register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA988B
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device lapic 0 on end
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end
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]
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device pci 02.0 on end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "alt_gp_smi_en" = "0x0000"
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register "gpi1_routing" = "2"
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register "gpi13_routing" = "2"
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# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
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register "sata_port_map" = "0x1f"
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# Set max SATA speed to 6.0 Gb/s
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register "sata_interface_speed_support" = "0x3"
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register "gen1_dec" = "0x7c1601"
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register "gen2_dec" = "0x0c15e1"
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register "gen4_dec" = "0x0c06a1"
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "101" # c2 not supported
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end
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device pci 16.2 off end
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device pci 16.3 off end
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 on end # PCIe Port #4 Express Card
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device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394
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device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY
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device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1f.0 on #LPC bridge
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa7"
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register "config1" = "0x09"
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register "config2" = "0xa0"
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register "config3" = "0xc2"
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register "beepmask0" = "0x00"
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register "beepmask1" = "0x86"
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register "has_power_management_beeps" = "0"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xd0"
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register "event5_enable" = "0xfc"
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register "event6_enable" = "0x00"
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register "event7_enable" = "0x01"
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register "event8_enable" = "0x7b"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0x01"
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register "eventb_enable" = "0x00"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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register "evente_enable" = "0x0d"
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register "has_bdc_detection" = "1"
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register "bdc_gpio_num" = "54"
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register "bdc_gpio_lvl" = "0"
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end
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chip drivers/lenovo/hybrid_graphics
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device pnp ff.f on end # dummy
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register "detect_gpio" = "21"
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register "has_panel_hybrid_gpio" = "1"
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register "panel_hybrid_gpio" = "52"
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register "panel_integrated_lvl" = "1"
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register "has_backlight_gpio" = "0"
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register "has_dgpu_power_gpio" = "0"
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register "has_thinker1" = "1"
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on # SMBUS controller
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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device i2c 57 on end
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device i2c 5c on end
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device i2c 5d on end
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device i2c 5e on end
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device i2c 5f on end
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end
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end # SMBus
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end
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end
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end
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221
src/mainboard/lenovo/t520/variants/w520/gpio.c
Normal file
221
src/mainboard/lenovo/t520/variants/w520/gpio.c
Normal file
@@ -0,0 +1,221 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_GPIO,
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.gpio3 = GPIO_MODE_GPIO,
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.gpio4 = GPIO_MODE_GPIO,
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.gpio5 = GPIO_MODE_GPIO,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_GPIO,
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.gpio11 = GPIO_MODE_NATIVE,
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.gpio12 = GPIO_MODE_NATIVE,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_NATIVE,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_NATIVE,
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.gpio21 = GPIO_MODE_GPIO,
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.gpio22 = GPIO_MODE_GPIO,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio2 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio4 = GPIO_DIR_INPUT,
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.gpio5 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio10 = GPIO_DIR_OUTPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio16 = GPIO_DIR_INPUT,
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.gpio17 = GPIO_DIR_INPUT,
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.gpio21 = GPIO_DIR_INPUT,
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.gpio22 = GPIO_DIR_OUTPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_INPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio8 = GPIO_LEVEL_HIGH,
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.gpio10 = GPIO_LEVEL_HIGH,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio22 = GPIO_LEVEL_LOW,
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.gpio24 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_LOW,
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.gpio29 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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.gpio24 = GPIO_RESET_RSMRST,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio0 = GPIO_INVERT,
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.gpio1 = GPIO_INVERT,
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.gpio7 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_NATIVE,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_GPIO,
|
||||
.gpio42 = GPIO_MODE_GPIO,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_NATIVE,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio41 = GPIO_DIR_OUTPUT,
|
||||
.gpio42 = GPIO_DIR_OUTPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_INPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_OUTPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio55 = GPIO_DIR_OUTPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio35 = GPIO_LEVEL_LOW,
|
||||
.gpio41 = GPIO_LEVEL_HIGH,
|
||||
.gpio42 = GPIO_LEVEL_HIGH,
|
||||
.gpio51 = GPIO_LEVEL_HIGH,
|
||||
.gpio52 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_HIGH,
|
||||
.gpio55 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_NATIVE,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
26
src/mainboard/lenovo/t520/variants/w520/romstage.c
Normal file
26
src/mainboard/lenovo/t520/variants/w520/romstage.c
Normal file
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[1], 0x52, id_only);
|
||||
read_spd(&spd[2], 0x51, id_only);
|
||||
read_spd(&spd[3], 0x53, id_only);
|
||||
}
|
||||
Reference in New Issue
Block a user