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soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA device

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Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name
resolves properly.

TEST=tested with rest of patch train

Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Matt DeVillier
2023-08-31 10:06:00 -05:00
committed by Martin L Roth
parent bed01d794f
commit ecf2b42e73
6 changed files with 15 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/alderlake/chip.c
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@ -94,6 +94,7 @@ const char *soc_acpi_name(const struct device *dev)
case SA_DEVFN_TBT2: return "TRP2"; case SA_DEVFN_TBT2: return "TRP2";
case SA_DEVFN_TBT3: return "TRP3"; case SA_DEVFN_TBT3: return "TRP3";
case SA_DEVFN_IPU: return "IPU0"; case SA_DEVFN_IPU: return "IPU0";
case SA_DEVFN_GNA: return "GNA";
case SA_DEVFN_DPTF: return "TCPU"; case SA_DEVFN_DPTF: return "TCPU";
case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_XHCI: return "XHCI";

1
src/soc/intel/jasperlake/chip.c
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@ -67,6 +67,7 @@ const char *soc_acpi_name(const struct device *dev)
case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_ROOT: return "MCHC";
case SA_DEVFN_IPU: return "IPU0"; case SA_DEVFN_IPU: return "IPU0";
case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_ISH: return "ISHB";
case SA_DEVFN_GNA: return "GNA";
case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C0: return "I2C0";
case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C1: return "I2C1";

10
src/soc/intel/jasperlake/include/soc/pci_devs.h
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@ -30,6 +30,10 @@
#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0)
#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
#define SA_DEV_SLOT_IPU 0x05
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
#define SA_DEV_SLOT_TBT 0x07 #define SA_DEV_SLOT_TBT 0x07
#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) #define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0)
#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) #define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1)
@ -40,9 +44,9 @@
#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
#define SA_DEV_SLOT_IPU 0x05 #define SA_DEV_SLOT_GNA 0x08
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) #define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
/* PCH Devices */ /* PCH Devices */
#define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEV_SLOT_SIO0 0x10

1
src/soc/intel/meteorlake/chip.c
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@ -83,6 +83,7 @@ const char *soc_acpi_name(const struct device *dev)
case PCI_DEVFN_TBT3: return "TRP3"; case PCI_DEVFN_TBT3: return "TRP3";
case PCI_DEVFN_IPU: return "IPU0"; case PCI_DEVFN_IPU: return "IPU0";
case PCI_DEVFN_ISH: return "ISHB"; case PCI_DEVFN_ISH: return "ISHB";
case PCI_DEVFN_GNA: return "GNA";
case PCI_DEVFN_XHCI: return "XHCI"; case PCI_DEVFN_XHCI: return "XHCI";
case PCI_DEVFN_I2C0: return "I2C0"; case PCI_DEVFN_I2C0: return "I2C0";
case PCI_DEVFN_I2C1: return "I2C1"; case PCI_DEVFN_I2C1: return "I2C1";

1
src/soc/intel/tigerlake/chip.c
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@ -83,6 +83,7 @@ const char *soc_acpi_name(const struct device *dev)
case SA_DEVFN_TBT2: return "TRP2"; case SA_DEVFN_TBT2: return "TRP2";
case SA_DEVFN_TBT3: return "TRP3"; case SA_DEVFN_TBT3: return "TRP3";
case SA_DEVFN_IPU: return "IPU0"; case SA_DEVFN_IPU: return "IPU0";
case SA_DEVFN_GNA: return "GNA";
case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C0: return "I2C0";

4
src/soc/intel/tigerlake/include/soc/pci_devs.h
View File

@ -57,6 +57,10 @@
#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
#define SA_DEV_SLOT_GNA 0x08
#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
#define SA_DEV_SLOT_TMT 0x0A #define SA_DEV_SLOT_TMT 0x0A
#define SA_DEVFN_TMT _SA_DEVFN(TMT) #define SA_DEVFN_TMT _SA_DEVFN(TMT)
#define SA_DEV_TMT _SA_DEV(TMT) #define SA_DEV_TMT _SA_DEV(TMT)