sb/intel/common/smi*: Use new PMBASE API
Use new PMBASE API functions in common SMI handler. Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Patrick Rudolph
parent
853bb4dc11
commit
ed3242e338
@@ -23,16 +23,15 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include <southbridge/intel/common/pmbase.h>
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#include "pmutil.h"
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#define DEBUG_PERIODIC_SMIS 0
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static u16 pmbase;
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u16 get_pmbase(void)
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{
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return pmbase;
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return lpc_get_pmbase();
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}
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void southbridge_smm_init(void)
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@@ -48,12 +47,9 @@ void southbridge_smm_init(void)
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printk(BIOS_DEBUG, "Initializing southbridge SMI...");
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pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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D31F0_PMBASE) & 0xff80;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase());
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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smi_en = read_pmbase32(SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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@@ -67,14 +63,14 @@ void southbridge_smm_init(void)
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dump_tco_status(reset_tco_status());
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/* Disable GPE0 PME_B0 */
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gpe0_en = inl(pmbase + GPE0_EN);
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gpe0_en = read_pmbase32(GPE0_EN);
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gpe0_en &= ~PME_B0_EN;
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outl(gpe0_en, pmbase + GPE0_EN);
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write_pmbase32(GPE0_EN, gpe0_en);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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write_pmbase16(PM1_EN, pm1_en);
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/* Enable SMI generation:
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* - on TCO events
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@@ -106,7 +102,7 @@ void southbridge_smm_init(void)
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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write_pmbase32(SMI_EN, smi_en);
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}
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void southbridge_trigger_smi(void)
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