sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/apollolake: use common Intel ACPI hardware definitions

Browse Source 
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15667
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:17:38 -05:00
parent 20a588b3de
commit ed35b7c546
4 changed files with 14 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/apollolake/Kconfig
View File

@ -7,6 +7,7 @@ if SOC_INTEL_APOLLOLAKE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32 select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32

13
src/soc/intel/apollolake/include/soc/pm.h
View File

@ -19,6 +19,7 @@
#define _SOC_APOLLOLAKE_PM_H_ #define _SOC_APOLLOLAKE_PM_H_
#include <stdint.h> #include <stdint.h>
#include <arch/acpi.h>
/* ACPI_BASE_ADDRESS */ /* ACPI_BASE_ADDRESS */
@ -35,13 +36,6 @@
#define TMROF_EN (1 << 0) #define TMROF_EN (1 << 0)
#define PM1_CNT 0x04 #define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP_SHIFT 10
#define SLP_TYP (7 << SLP_TYP_SHIFT)
#define SLP_TYP_S0 0
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define SCI_EN (1 << 0) #define SCI_EN (1 << 0)
#define PM1_TMR 0x08 #define PM1_TMR 0x08
@ -151,11 +145,6 @@
#define PMC_GPE_N_63_32 7 #define PMC_GPE_N_63_32 7
#define PMC_GPE_W_31_0 9 #define PMC_GPE_W_31_0 9
/* Generic sleep state types */
#define SLEEP_STATE_S0 0
#define SLEEP_STATE_S3 3
#define SLEEP_STATE_S5 5
/* Track power state from reset to log events. */ /* Track power state from reset to log events. */
struct chipset_power_state { struct chipset_power_state {
uint16_t pm1_sts; uint16_t pm1_sts;

20
src/soc/intel/apollolake/pmutil.c
View File

@ -307,17 +307,16 @@ void clear_pmc_status(void)
int chipset_prev_sleep_state(struct chipset_power_state *ps) int chipset_prev_sleep_state(struct chipset_power_state *ps)
{ {
/* Default to S0. */ /* Default to S0. */
int prev_sleep_state = SLEEP_STATE_S0; int prev_sleep_state = ACPI_S0;
if (ps->pm1_sts & WAK_STS) { if (ps->pm1_sts & WAK_STS) {
switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) case ACPI_S3:
case SLP_TYP_S3: if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
prev_sleep_state = SLEEP_STATE_S3; prev_sleep_state = ACPI_S3;
break; break;
#endif case ACPI_S5:
case SLP_TYP_S5: prev_sleep_state = ACPI_S5;
prev_sleep_state = SLEEP_STATE_S5;
break; break;
} }
@ -365,13 +364,10 @@ int fill_power_state(struct chipset_power_state *ps)
int vboot_platform_is_resuming(void) int vboot_platform_is_resuming(void)
{ {
int typ;
if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS))
return 0; return 0;
typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; return acpi_sleep_from_pm1(inl(ACPI_PMIO_BASE + PM1_CNT)) == ACPI_S3;
return typ == SLP_TYP_S3;
} }
/* /*

8
src/soc/intel/apollolake/romstage.c
View File

@ -136,7 +136,7 @@ asmlinkage void car_stage_entry(void)
fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
/* initialize cbmem by adding FSP reserved memory first thing */ /* initialize cbmem by adding FSP reserved memory first thing */
if (prev_sleep_state != SLEEP_STATE_S3) { if (prev_sleep_state != ACPI_S3) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem)); range_entry_size(&fsp_mem));
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
@ -158,7 +158,7 @@ asmlinkage void car_stage_entry(void)
/* Save MRC Data to CBMEM */ /* Save MRC Data to CBMEM */
if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) &&
(prev_sleep_state != SLEEP_STATE_S3)) (prev_sleep_state != ACPI_S3))
{ {
mrc_data = fsp_find_nv_storage_data(&mrc_data_size); mrc_data = fsp_find_nv_storage_data(&mrc_data_size);
if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0)
@ -168,7 +168,7 @@ asmlinkage void car_stage_entry(void)
/* Create romstage handof information */ /* Create romstage handof information */
handoff = romstage_handoff_find_or_add(); handoff = romstage_handoff_find_or_add();
if (handoff != NULL) if (handoff != NULL)
handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); handoff->s3_resume = (prev_sleep_state == ACPI_S3);
else else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
@ -233,7 +233,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
/* MRC cache found */ /* MRC cache found */
arch_upd->NvsBufferPtr = (void *)mrc_cache->data; arch_upd->NvsBufferPtr = (void *)mrc_cache->data;
arch_upd->BootMode = arch_upd->BootMode =
prev_sleep_state == SLEEP_STATE_S3 ? prev_sleep_state == ACPI_S3 ?
FSP_BOOT_ON_S3_RESUME: FSP_BOOT_ON_S3_RESUME:
FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n",